1 /* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci_ids.h>
15 #include <asm/pci-direct.h>
17 #include <asm/io_apic.h>
19 #include <asm/iommu.h>
23 static void __init fix_hypertransport_config(int num, int slot, int func)
27 * we found a hypertransport bus
28 * make sure that we are broadcasting
29 * interrupts to all cpus on the ht bus
30 * if we're using extended apic ids
32 htcfg = read_pci_config(num, slot, func, 0x68);
33 if (htcfg & (1 << 18)) {
34 printk(KERN_INFO "Detected use of extended apic ids "
35 "on hypertransport bus\n");
36 if ((htcfg & (1 << 17)) == 0) {
37 printk(KERN_INFO "Enabling hypertransport extended "
38 "apic interrupt broadcast\n");
39 printk(KERN_INFO "Note this is a bios bug, "
40 "please contact your hw vendor\n");
42 write_pci_config(num, slot, func, 0x68, htcfg);
49 static void __init via_bugs(int num, int slot, int func)
51 #ifdef CONFIG_GART_IOMMU
52 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
53 !gart_iommu_aperture_allowed) {
55 "Looks like a VIA chipset. Disabling IOMMU."
56 " Override with iommu=allowed\n");
57 gart_iommu_aperture_disabled = 1;
63 #ifdef CONFIG_X86_IO_APIC
65 static int __init nvidia_hpet_check(struct acpi_table_header *header)
69 #endif /* CONFIG_X86_IO_APIC */
70 #endif /* CONFIG_ACPI */
72 static void __init nvidia_bugs(int num, int slot, int func)
75 #ifdef CONFIG_X86_IO_APIC
77 * All timer overrides on Nvidia are
78 * wrong unless HPET is enabled.
79 * Unfortunately that's not true on many Asus boards.
80 * We don't know yet how to detect this automatically, but
81 * at least allow a command line override.
83 if (acpi_use_timer_override)
86 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
87 acpi_skip_timer_override = 1;
88 printk(KERN_INFO "Nvidia board "
89 "detected. Ignoring ACPI "
91 printk(KERN_INFO "If you got timer trouble "
92 "try acpi_use_timer_override\n");
96 /* RED-PEN skip them on mptables too? */
100 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
101 #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
102 static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
107 b = read_pci_config_byte(num, slot, func, 0xac);
109 write_pci_config_byte(num, slot, func, 0xac, b);
111 d = read_pci_config(num, slot, func, 0x70);
113 write_pci_config(num, slot, func, 0x70, d);
115 d = read_pci_config(num, slot, func, 0x8);
121 static void __init ati_bugs(int num, int slot, int func)
126 if (acpi_use_timer_override)
129 d = ati_ixp4x0_rev(num, slot, func);
131 acpi_skip_timer_override = 1;
133 /* check for IRQ0 interrupt swap */
134 outb(0x72, 0xcd6); b = inb(0xcd7);
136 acpi_skip_timer_override = 1;
139 if (acpi_skip_timer_override) {
140 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
141 printk(KERN_INFO "Ignoring ACPI timer override.\n");
142 printk(KERN_INFO "If you got timer trouble "
143 "try acpi_use_timer_override\n");
147 static u32 __init ati_sbx00_rev(int num, int slot, int func)
151 d = read_pci_config(num, slot, func, 0x70);
154 write_pci_config(num, slot, func, 0x70, d);
155 d = read_pci_config(num, slot, func, 0x8);
157 write_pci_config(num, slot, func, 0x70, old);
162 static void __init ati_bugs_contd(int num, int slot, int func)
166 if (acpi_use_timer_override)
169 rev = ati_sbx00_rev(num, slot, func);
173 /* check for IRQ0 interrupt swap */
174 d = read_pci_config(num, slot, func, 0x64);
176 acpi_skip_timer_override = 1;
178 if (acpi_skip_timer_override) {
179 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
180 printk(KERN_INFO "Ignoring ACPI timer override.\n");
181 printk(KERN_INFO "If you got timer trouble "
182 "try acpi_use_timer_override\n");
186 static void __init ati_bugs(int num, int slot, int func)
190 static void __init ati_bugs_contd(int num, int slot, int func)
196 * Force the read back of the CMP register in hpet_next_event()
197 * to work around the problem that the CMP register write seems to be
198 * delayed. See hpet_next_event() for details.
200 * We do this on all SMBUS incarnations for now until we have more
201 * information about the affected chipsets.
203 static void __init ati_hpet_bugs(int num, int slot, int func)
205 #ifdef CONFIG_HPET_TIMER
206 hpet_readback_cmp = 1;
210 #define QFLAG_APPLY_ONCE 0x1
211 #define QFLAG_APPLIED 0x2
212 #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
219 void (*f)(int num, int slot, int func);
223 * Only works for devices on the root bus. If you add any devices
224 * not on bus 0 readd another loop level in early_quirks(). But
225 * be careful because at least the Nvidia quirk here relies on
226 * only matching on bus 0.
228 static struct chipset early_qrk[] __initdata = {
229 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
230 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
231 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
232 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
233 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
234 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
236 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
238 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
239 { PCI_VENDOR_ID_ATI, PCI_ANY_ID,
240 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_hpet_bugs },
245 * check_dev_quirk - apply early quirks to a given PCI device
248 * @func: PCI function
250 * Check the vendor & device ID against the early quirks table.
252 * If the device is single function, let early_quirks() know so we don't
253 * poke at this device again.
255 static int __init check_dev_quirk(int num, int slot, int func)
263 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
266 return -1; /* no class, treat as single function */
268 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
270 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
272 for (i = 0; early_qrk[i].f != NULL; i++) {
273 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
274 (early_qrk[i].vendor == vendor)) &&
275 ((early_qrk[i].device == PCI_ANY_ID) ||
276 (early_qrk[i].device == device)) &&
277 (!((early_qrk[i].class ^ class) &
278 early_qrk[i].class_mask))) {
279 if ((early_qrk[i].flags &
280 QFLAG_DONE) != QFLAG_DONE)
281 early_qrk[i].f(num, slot, func);
282 early_qrk[i].flags |= QFLAG_APPLIED;
286 type = read_pci_config_byte(num, slot, func,
294 void __init early_quirks(void)
298 if (!early_pci_allowed())
301 /* Poor man's PCI discovery */
302 /* Only scan the root bus */
303 for (slot = 0; slot < 32; slot++)
304 for (func = 0; func < 8; func++) {
305 /* Only probe function 0 on single fn devices */
306 if (check_dev_quirk(0, slot, func))