2 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
12 #include <linux/linkage.h>
13 #include <linux/threads.h>
14 #include <linux/init.h>
15 #include <asm/segment.h>
16 #include <asm/pgtable.h>
19 #include <asm/cache.h>
20 #include <asm/processor-flags.h>
21 #include <asm/percpu.h>
23 #include "../entry/calling.h"
25 #ifdef CONFIG_PARAVIRT
26 #include <asm/asm-offsets.h>
27 #include <asm/paravirt.h>
28 #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
30 #define GET_CR2_INTO(reg) movq %cr2, reg
31 #define INTERRUPT_RETURN iretq
34 /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
35 * because we need identity-mapped pages.
39 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
41 L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
42 L4_START_KERNEL = pgd_index(__START_KERNEL_map)
43 L3_START_KERNEL = pud_index(__START_KERNEL_map)
51 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
52 * and someone has loaded an identity mapped page table
53 * for us. These identity mapped page tables map all of the
54 * kernel pages and possibly all of memory.
56 * %rsi holds a physical pointer to real_mode_data.
58 * We come here either directly from a 64bit bootloader, or from
59 * arch/x86/boot/compressed/head_64.S.
61 * We only come here initially at boot nothing else comes here.
63 * Since we may be loaded at an address different from what we were
64 * compiled to run at we first fixup the physical addresses in our page
65 * tables and then reload them.
68 /* Sanitize CPU configuration */
72 * Compute the delta between the address I am compiled to run at and the
73 * address I am actually running at.
75 leaq _text(%rip), %rbp
76 subq $_text - __START_KERNEL_map, %rbp
78 /* Is the address not 2M aligned? */
79 testl $~PMD_PAGE_MASK, %ebp
83 * Is the address too large?
85 leaq _text(%rip), %rax
86 shrq $MAX_PHYSMEM_BITS, %rax
90 * Fixup the physical addresses in the page table
92 addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
94 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
95 addq %rbp, level3_kernel_pgt + (511*8)(%rip)
97 addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
100 * Set up the identity mapping for the switchover. These
101 * entries should *NOT* have the global bit set! This also
102 * creates a bunch of nonsense entries but that is fine --
103 * it avoids problems around wraparound.
105 leaq _text(%rip), %rdi
106 leaq early_level4_pgt(%rip), %rbx
109 shrq $PGDIR_SHIFT, %rax
111 leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
112 movq %rdx, 0(%rbx,%rax,8)
113 movq %rdx, 8(%rbx,%rax,8)
117 shrq $PUD_SHIFT, %rax
118 andl $(PTRS_PER_PUD-1), %eax
119 movq %rdx, 4096(%rbx,%rax,8)
121 andl $(PTRS_PER_PUD-1), %eax
122 movq %rdx, 4096(%rbx,%rax,8)
126 shrq $PMD_SHIFT, %rdi
127 addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
128 leaq (_end - 1)(%rip), %rcx
129 shrq $PMD_SHIFT, %rcx
134 andq $(PTRS_PER_PMD - 1), %rdi
135 movq %rax, (%rbx,%rdi,8)
142 * Fixup the kernel text+data virtual addresses. Note that
143 * we might write invalid pmds, when the kernel is relocated
144 * cleanup_highmap() fixes this up along with the mappings
147 leaq level2_kernel_pgt(%rip), %rdi
149 /* See if it is a valid page table entry */
153 /* Go to the next page */
158 /* Fixup phys_base */
159 addq %rbp, phys_base(%rip)
161 movq $(early_level4_pgt - __START_KERNEL_map), %rax
163 ENTRY(secondary_startup_64)
165 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
166 * and someone has loaded a mapped page table.
168 * %rsi holds a physical pointer to real_mode_data.
170 * We come here either from startup_64 (using physical addresses)
171 * or from trampoline.S (using virtual addresses).
173 * Using virtual addresses from trampoline.S removes the need
174 * to have any identity mapped pages in the kernel page table
175 * after the boot processor executes this code.
178 /* Sanitize CPU configuration */
181 movq $(init_level4_pgt - __START_KERNEL_map), %rax
184 /* Enable PAE mode and PGE */
185 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
188 /* Setup early boot stage 4 level pagetables. */
189 addq phys_base(%rip), %rax
192 /* Ensure I am executing from virtual addresses */
197 /* Check if nx is implemented */
198 movl $0x80000001, %eax
202 /* Setup EFER (Extended Feature Enable Register) */
205 btsl $_EFER_SCE, %eax /* Enable System Call */
206 btl $20,%edi /* No Execute supported? */
209 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
210 1: wrmsr /* Make changes effective */
213 #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
214 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
216 movl $CR0_STATE, %eax
217 /* Make changes effective */
220 /* Setup a boot time stack */
221 movq stack_start(%rip), %rsp
223 /* zero EFLAGS after setting rsp */
228 * We must switch to a new descriptor in kernel space for the GDT
229 * because soon the kernel won't have access anymore to the userspace
230 * addresses where we're currently running on. We have to do that here
231 * because in 32bit we couldn't load a 64bit linear address.
233 lgdt early_gdt_descr(%rip)
235 /* set up data segments */
242 * We don't really need to load %fs or %gs, but load them anyway
243 * to kill any stale realmode selectors. This allows execution
251 * The base of %gs always points to the bottom of the irqstack
252 * union. If the stack protector canary is enabled, it is
253 * located at %gs:40. Note that, on SMP, the boot cpu uses
254 * init data section till per cpu areas are set up.
256 movl $MSR_GS_BASE,%ecx
257 movl initial_gs(%rip),%eax
258 movl initial_gs+4(%rip),%edx
261 /* rsi is pointer to real mode structure with interesting info.
265 /* Finally jump to run C code and to be on real kernel address
266 * Since we are running on identity-mapped space we have to jump
267 * to the full 64bit address, this is only possible as indirect
268 * jump. In addition we need to ensure %cs is set so we make this
271 * Note: do not change to far jump indirect with 64bit offset.
273 * AMD does not support far jump indirect with 64bit offset.
274 * AMD64 Architecture Programmer's Manual, Volume 3: states only
275 * JMP FAR mem16:16 FF /5 Far jump indirect,
276 * with the target specified by a far pointer in memory.
277 * JMP FAR mem16:32 FF /5 Far jump indirect,
278 * with the target specified by a far pointer in memory.
280 * Intel64 does support 64bit offset.
281 * Software Developer Manual Vol 2: states:
282 * FF /5 JMP m16:16 Jump far, absolute indirect,
283 * address given in m16:16
284 * FF /5 JMP m16:32 Jump far, absolute indirect,
285 * address given in m16:32.
286 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
287 * address given in m16:64.
289 movq initial_code(%rip),%rax
290 pushq $0 # fake return address to stop unwinder
291 pushq $__KERNEL_CS # set correct cs
292 pushq %rax # target address in negative space
295 #include "verify_cpu.S"
297 #ifdef CONFIG_HOTPLUG_CPU
299 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
300 * up already except stack. We just set up stack here. Then call
304 movq stack_start(%rip),%rsp
305 movq initial_code(%rip),%rax
306 pushq $0 # fake return address to stop unwinder
307 pushq $__KERNEL_CS # set correct cs
308 pushq %rax # target address in negative space
313 /* SMP bootup changes these two */
317 .quad x86_64_start_kernel
319 .quad INIT_PER_CPU_VAR(irq_stack_union)
322 .quad init_thread_union+THREAD_SIZE-8
330 ENTRY(early_idt_handler_array)
334 # 80(%rsp) error code
336 .rept NUM_EXCEPTION_VECTORS
337 .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1
338 pushq $0 # Dummy error code, to make stack frame uniform
340 pushq $i # 72(%rsp) Vector number
341 jmp early_idt_handler_common
343 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
345 ENDPROC(early_idt_handler_array)
347 early_idt_handler_common:
349 * The stack is the hardware frame, an error code or zero, and the
354 cmpl $2,early_recursion_flag(%rip)
356 incl early_recursion_flag(%rip)
358 /* The vector number is currently in the pt_regs->di slot. */
359 pushq %rsi /* pt_regs->si */
360 movq 8(%rsp), %rsi /* RSI = vector number */
361 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
362 pushq %rdx /* pt_regs->dx */
363 pushq %rcx /* pt_regs->cx */
364 pushq %rax /* pt_regs->ax */
365 pushq %r8 /* pt_regs->r8 */
366 pushq %r9 /* pt_regs->r9 */
367 pushq %r10 /* pt_regs->r10 */
368 pushq %r11 /* pt_regs->r11 */
369 pushq %rbx /* pt_regs->bx */
370 pushq %rbp /* pt_regs->bp */
371 pushq %r12 /* pt_regs->r12 */
372 pushq %r13 /* pt_regs->r13 */
373 pushq %r14 /* pt_regs->r14 */
374 pushq %r15 /* pt_regs->r15 */
376 cmpl $__KERNEL_CS,CS(%rsp)
379 cmpq $14,%rsi /* Page fault? */
381 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */
382 call early_make_pgtable
384 jz 20f /* All good */
387 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
388 call early_fixup_exception
390 jnz 20f # Found an exception entry
393 #ifdef CONFIG_EARLY_PRINTK
395 * On paravirt kernels, GET_CR2_INTO clobbers callee-clobbered regs.
396 * We only care about RSI, so we need to save it.
398 movq %rsi,%rbx /* Save vector number */
400 movq ORIG_RAX(%rsp),%r8 /* error code */
401 movq %rbx,%rsi /* vector number */
405 leaq early_idt_msg(%rip),%rdi
407 cmpl $2,early_recursion_flag(%rip)
410 #ifdef CONFIG_KALLSYMS
411 leaq early_idt_ripmsg(%rip),%rdi
412 movq RIP(%rsp),%rsi # %rip again
415 #endif /* EARLY_PRINTK */
419 20: /* Exception table entry found or page table generated */
420 decl early_recursion_flag(%rip)
421 jmp restore_regs_and_iret
422 ENDPROC(early_idt_handler_common)
427 early_recursion_flag:
430 #ifdef CONFIG_EARLY_PRINTK
432 .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
435 #endif /* CONFIG_EARLY_PRINTK */
437 #define NEXT_PAGE(name) \
441 /* Automate the creation of 1 to 1 mapping pmd entries */
442 #define PMDS(START, PERM, COUNT) \
445 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
450 NEXT_PAGE(early_level4_pgt)
452 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
454 NEXT_PAGE(early_dynamic_pgts)
455 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
460 NEXT_PAGE(init_level4_pgt)
463 NEXT_PAGE(init_level4_pgt)
464 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
465 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0
466 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
467 .org init_level4_pgt + L4_START_KERNEL*8, 0
468 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
469 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
471 NEXT_PAGE(level3_ident_pgt)
472 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
474 NEXT_PAGE(level2_ident_pgt)
475 /* Since I easily can, map the first 1G.
476 * Don't set NX because code runs from these pages.
478 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
481 NEXT_PAGE(level3_kernel_pgt)
482 .fill L3_START_KERNEL,8,0
483 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
484 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
485 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
487 NEXT_PAGE(level2_kernel_pgt)
489 * 512 MB kernel mapping. We spend a full page on this pagetable
492 * The kernel code+data+bss must not be bigger than that.
494 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
495 * If you want to increase this then increase MODULES_VADDR
498 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
499 KERNEL_IMAGE_SIZE/PMD_SIZE)
501 NEXT_PAGE(level2_fixmap_pgt)
503 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
504 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
507 NEXT_PAGE(level1_fixmap_pgt)
514 .globl early_gdt_descr
516 .word GDT_ENTRIES*8-1
517 early_gdt_descr_base:
518 .quad INIT_PER_CPU_VAR(gdt_page)
521 /* This must match the first entry in level2_kernel_pgt */
522 .quad 0x0000000000000000
524 #include "../../x86/xen/xen-head.S"
527 NEXT_PAGE(empty_zero_page)