1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/export.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/i8253.h>
8 #include <linux/slab.h>
9 #include <linux/hpet.h>
10 #include <linux/init.h>
11 #include <linux/cpu.h>
15 #include <asm/cpufeature.h>
16 #include <asm/irqdomain.h>
17 #include <asm/fixmap.h>
21 #define HPET_MASK CLOCKSOURCE_MASK(32)
25 #define FSEC_PER_NSEC 1000000L
27 #define HPET_DEV_USED_BIT 2
28 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
29 #define HPET_DEV_VALID 0x8
30 #define HPET_DEV_FSB_CAP 0x1000
31 #define HPET_DEV_PERI_CAP 0x2000
33 #define HPET_MIN_CYCLES 128
34 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
39 unsigned long hpet_address;
40 u8 hpet_blockid; /* OS timer block num */
41 bool hpet_msi_disable;
44 static unsigned int hpet_num_timers;
46 static void __iomem *hpet_virt_address;
49 struct clock_event_device evt;
57 static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
59 return container_of(evtdev, struct hpet_dev, evt);
62 inline unsigned int hpet_readl(unsigned int a)
64 return readl(hpet_virt_address + a);
67 static inline void hpet_writel(unsigned int d, unsigned int a)
69 writel(d, hpet_virt_address + a);
73 #include <asm/pgtable.h>
76 static inline void hpet_set_mapping(void)
78 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
81 static inline void hpet_clear_mapping(void)
83 iounmap(hpet_virt_address);
84 hpet_virt_address = NULL;
88 * HPET command line enable / disable
90 bool boot_hpet_disable;
92 static bool hpet_verbose;
94 static int __init hpet_setup(char *str)
97 char *next = strchr(str, ',');
101 if (!strncmp("disable", str, 7))
102 boot_hpet_disable = true;
103 if (!strncmp("force", str, 5))
104 hpet_force_user = true;
105 if (!strncmp("verbose", str, 7))
111 __setup("hpet=", hpet_setup);
113 static int __init disable_hpet(char *str)
115 boot_hpet_disable = true;
118 __setup("nohpet", disable_hpet);
120 static inline int is_hpet_capable(void)
122 return !boot_hpet_disable && hpet_address;
126 * HPET timer interrupt enable / disable
128 static bool hpet_legacy_int_enabled;
131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
133 int is_hpet_enabled(void)
135 return is_hpet_capable() && hpet_legacy_int_enabled;
137 EXPORT_SYMBOL_GPL(is_hpet_enabled);
139 static void _hpet_print_config(const char *function, int line)
142 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
143 l = hpet_readl(HPET_ID);
144 h = hpet_readl(HPET_PERIOD);
145 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
146 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
147 l = hpet_readl(HPET_CFG);
148 h = hpet_readl(HPET_STATUS);
149 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
150 l = hpet_readl(HPET_COUNTER);
151 h = hpet_readl(HPET_COUNTER+4);
152 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
154 for (i = 0; i < timers; i++) {
155 l = hpet_readl(HPET_Tn_CFG(i));
156 h = hpet_readl(HPET_Tn_CFG(i)+4);
157 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
159 l = hpet_readl(HPET_Tn_CMP(i));
160 h = hpet_readl(HPET_Tn_CMP(i)+4);
161 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
163 l = hpet_readl(HPET_Tn_ROUTE(i));
164 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
165 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
170 #define hpet_print_config() \
173 _hpet_print_config(__func__, __LINE__); \
177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
178 * timer 0 and timer 1 in case of RTC emulation.
182 static void hpet_reserve_msi_timers(struct hpet_data *hd);
184 static void hpet_reserve_platform_timers(unsigned int id)
186 struct hpet __iomem *hpet = hpet_virt_address;
187 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
188 unsigned int nrtimers, i;
191 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
193 memset(&hd, 0, sizeof(hd));
194 hd.hd_phys_address = hpet_address;
195 hd.hd_address = hpet;
196 hd.hd_nirqs = nrtimers;
197 hpet_reserve_timer(&hd, 0);
199 #ifdef CONFIG_HPET_EMULATE_RTC
200 hpet_reserve_timer(&hd, 1);
204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
205 * is wrong for i8259!) not the output IRQ. Many BIOS writers
206 * don't bother configuring *any* comparator interrupts.
208 hd.hd_irq[0] = HPET_LEGACY_8254;
209 hd.hd_irq[1] = HPET_LEGACY_RTC;
211 for (i = 2; i < nrtimers; timer++, i++) {
212 hd.hd_irq[i] = (readl(&timer->hpet_config) &
213 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
216 hpet_reserve_msi_timers(&hd);
222 static void hpet_reserve_platform_timers(unsigned int id) { }
228 static unsigned long hpet_freq;
230 static struct clock_event_device hpet_clockevent;
232 static void hpet_stop_counter(void)
234 u32 cfg = hpet_readl(HPET_CFG);
235 cfg &= ~HPET_CFG_ENABLE;
236 hpet_writel(cfg, HPET_CFG);
239 static void hpet_reset_counter(void)
241 hpet_writel(0, HPET_COUNTER);
242 hpet_writel(0, HPET_COUNTER + 4);
245 static void hpet_start_counter(void)
247 unsigned int cfg = hpet_readl(HPET_CFG);
248 cfg |= HPET_CFG_ENABLE;
249 hpet_writel(cfg, HPET_CFG);
252 static void hpet_restart_counter(void)
255 hpet_reset_counter();
256 hpet_start_counter();
259 static void hpet_resume_device(void)
264 static void hpet_resume_counter(struct clocksource *cs)
266 hpet_resume_device();
267 hpet_restart_counter();
270 static void hpet_enable_legacy_int(void)
272 unsigned int cfg = hpet_readl(HPET_CFG);
274 cfg |= HPET_CFG_LEGACY;
275 hpet_writel(cfg, HPET_CFG);
276 hpet_legacy_int_enabled = true;
279 static void hpet_legacy_clockevent_register(void)
281 /* Start HPET legacy interrupts */
282 hpet_enable_legacy_int();
285 * Start hpet with the boot cpu mask and make it
286 * global after the IO_APIC has been initialized.
288 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
289 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
290 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
291 global_clock_event = &hpet_clockevent;
292 printk(KERN_DEBUG "hpet clockevent registered\n");
295 static int hpet_set_periodic(struct clock_event_device *evt, int timer)
297 unsigned int cfg, cmp, now;
301 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
302 delta >>= evt->shift;
303 now = hpet_readl(HPET_COUNTER);
304 cmp = now + (unsigned int)delta;
305 cfg = hpet_readl(HPET_Tn_CFG(timer));
306 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
308 hpet_writel(cfg, HPET_Tn_CFG(timer));
309 hpet_writel(cmp, HPET_Tn_CMP(timer));
312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
314 * bit is automatically cleared after the first write.
315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
316 * Publication # 24674)
318 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
319 hpet_start_counter();
325 static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
329 cfg = hpet_readl(HPET_Tn_CFG(timer));
330 cfg &= ~HPET_TN_PERIODIC;
331 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
332 hpet_writel(cfg, HPET_Tn_CFG(timer));
337 static int hpet_shutdown(struct clock_event_device *evt, int timer)
341 cfg = hpet_readl(HPET_Tn_CFG(timer));
342 cfg &= ~HPET_TN_ENABLE;
343 hpet_writel(cfg, HPET_Tn_CFG(timer));
348 static int hpet_resume(struct clock_event_device *evt, int timer)
351 hpet_enable_legacy_int();
353 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
355 irq_domain_activate_irq(irq_get_irq_data(hdev->irq));
356 disable_irq(hdev->irq);
357 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
358 enable_irq(hdev->irq);
365 static int hpet_next_event(unsigned long delta,
366 struct clock_event_device *evt, int timer)
371 cnt = hpet_readl(HPET_COUNTER);
373 hpet_writel(cnt, HPET_Tn_CMP(timer));
376 * HPETs are a complete disaster. The compare register is
377 * based on a equal comparison and neither provides a less
378 * than or equal functionality (which would require to take
379 * the wraparound into account) nor a simple count down event
380 * mode. Further the write to the comparator register is
381 * delayed internally up to two HPET clock cycles in certain
382 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
383 * longer delays. We worked around that by reading back the
384 * compare register, but that required another workaround for
385 * ICH9,10 chips where the first readout after write can
386 * return the old stale value. We already had a minimum
387 * programming delta of 5us enforced, but a NMI or SMI hitting
388 * between the counter readout and the comparator write can
389 * move us behind that point easily. Now instead of reading
390 * the compare register back several times, we make the ETIME
391 * decision based on the following: Return ETIME if the
392 * counter value after the write is less than HPET_MIN_CYCLES
393 * away from the event or if the counter is already ahead of
394 * the event. The minimum programming delta for the generic
395 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
397 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
399 return res < HPET_MIN_CYCLES ? -ETIME : 0;
402 static int hpet_legacy_shutdown(struct clock_event_device *evt)
404 return hpet_shutdown(evt, 0);
407 static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
409 return hpet_set_oneshot(evt, 0);
412 static int hpet_legacy_set_periodic(struct clock_event_device *evt)
414 return hpet_set_periodic(evt, 0);
417 static int hpet_legacy_resume(struct clock_event_device *evt)
419 return hpet_resume(evt, 0);
422 static int hpet_legacy_next_event(unsigned long delta,
423 struct clock_event_device *evt)
425 return hpet_next_event(delta, evt, 0);
429 * The hpet clock event device
431 static struct clock_event_device hpet_clockevent = {
433 .features = CLOCK_EVT_FEAT_PERIODIC |
434 CLOCK_EVT_FEAT_ONESHOT,
435 .set_state_periodic = hpet_legacy_set_periodic,
436 .set_state_oneshot = hpet_legacy_set_oneshot,
437 .set_state_shutdown = hpet_legacy_shutdown,
438 .tick_resume = hpet_legacy_resume,
439 .set_next_event = hpet_legacy_next_event,
447 #ifdef CONFIG_PCI_MSI
449 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
450 static struct hpet_dev *hpet_devs;
451 static struct irq_domain *hpet_domain;
453 void hpet_msi_unmask(struct irq_data *data)
455 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
459 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
460 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
461 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
464 void hpet_msi_mask(struct irq_data *data)
466 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
470 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
471 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
472 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
475 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
477 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
478 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
481 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
483 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
484 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
488 static int hpet_msi_shutdown(struct clock_event_device *evt)
490 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
492 return hpet_shutdown(evt, hdev->num);
495 static int hpet_msi_set_oneshot(struct clock_event_device *evt)
497 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
499 return hpet_set_oneshot(evt, hdev->num);
502 static int hpet_msi_set_periodic(struct clock_event_device *evt)
504 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
506 return hpet_set_periodic(evt, hdev->num);
509 static int hpet_msi_resume(struct clock_event_device *evt)
511 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
513 return hpet_resume(evt, hdev->num);
516 static int hpet_msi_next_event(unsigned long delta,
517 struct clock_event_device *evt)
519 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
520 return hpet_next_event(delta, evt, hdev->num);
523 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
525 struct hpet_dev *dev = (struct hpet_dev *)data;
526 struct clock_event_device *hevt = &dev->evt;
528 if (!hevt->event_handler) {
529 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
534 hevt->event_handler(hevt);
538 static int hpet_setup_irq(struct hpet_dev *dev)
541 if (request_irq(dev->irq, hpet_interrupt_handler,
542 IRQF_TIMER | IRQF_NOBALANCING,
546 disable_irq(dev->irq);
547 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
548 enable_irq(dev->irq);
550 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
551 dev->name, dev->irq);
556 /* This should be called in specific @cpu */
557 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
559 struct clock_event_device *evt = &hdev->evt;
561 WARN_ON(cpu != smp_processor_id());
562 if (!(hdev->flags & HPET_DEV_VALID))
566 per_cpu(cpu_hpet_dev, cpu) = hdev;
567 evt->name = hdev->name;
568 hpet_setup_irq(hdev);
569 evt->irq = hdev->irq;
572 evt->features = CLOCK_EVT_FEAT_ONESHOT;
573 if (hdev->flags & HPET_DEV_PERI_CAP) {
574 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
575 evt->set_state_periodic = hpet_msi_set_periodic;
578 evt->set_state_shutdown = hpet_msi_shutdown;
579 evt->set_state_oneshot = hpet_msi_set_oneshot;
580 evt->tick_resume = hpet_msi_resume;
581 evt->set_next_event = hpet_msi_next_event;
582 evt->cpumask = cpumask_of(hdev->cpu);
584 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
589 /* Reserve at least one timer for userspace (/dev/hpet) */
590 #define RESERVE_TIMERS 1
592 #define RESERVE_TIMERS 0
595 static void hpet_msi_capability_lookup(unsigned int start_timer)
598 unsigned int num_timers;
599 unsigned int num_timers_used = 0;
602 if (hpet_msi_disable)
605 if (boot_cpu_has(X86_FEATURE_ARAT))
607 id = hpet_readl(HPET_ID);
609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
610 num_timers++; /* Value read out starts from 0 */
613 hpet_domain = hpet_create_irq_domain(hpet_blockid);
617 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
621 hpet_num_timers = num_timers;
623 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
624 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
625 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
627 /* Only consider HPET timer with MSI support */
628 if (!(cfg & HPET_TN_FSB_CAP))
632 if (cfg & HPET_TN_PERIODIC_CAP)
633 hdev->flags |= HPET_DEV_PERI_CAP;
634 sprintf(hdev->name, "hpet%d", i);
637 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
642 hdev->flags |= HPET_DEV_FSB_CAP;
643 hdev->flags |= HPET_DEV_VALID;
645 if (num_timers_used == num_possible_cpus())
649 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
650 num_timers, num_timers_used);
654 static void hpet_reserve_msi_timers(struct hpet_data *hd)
661 for (i = 0; i < hpet_num_timers; i++) {
662 struct hpet_dev *hdev = &hpet_devs[i];
664 if (!(hdev->flags & HPET_DEV_VALID))
667 hd->hd_irq[hdev->num] = hdev->irq;
668 hpet_reserve_timer(hd, hdev->num);
673 static struct hpet_dev *hpet_get_unused_timer(void)
680 for (i = 0; i < hpet_num_timers; i++) {
681 struct hpet_dev *hdev = &hpet_devs[i];
683 if (!(hdev->flags & HPET_DEV_VALID))
685 if (test_and_set_bit(HPET_DEV_USED_BIT,
686 (unsigned long *)&hdev->flags))
693 struct hpet_work_struct {
694 struct delayed_work work;
695 struct completion complete;
698 static void hpet_work(struct work_struct *w)
700 struct hpet_dev *hdev;
701 int cpu = smp_processor_id();
702 struct hpet_work_struct *hpet_work;
704 hpet_work = container_of(w, struct hpet_work_struct, work.work);
706 hdev = hpet_get_unused_timer();
708 init_one_hpet_msi_clockevent(hdev, cpu);
710 complete(&hpet_work->complete);
713 static int hpet_cpuhp_online(unsigned int cpu)
715 struct hpet_work_struct work;
717 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
718 init_completion(&work.complete);
719 /* FIXME: add schedule_work_on() */
720 schedule_delayed_work_on(cpu, &work.work, 0);
721 wait_for_completion(&work.complete);
722 destroy_delayed_work_on_stack(&work.work);
726 static int hpet_cpuhp_dead(unsigned int cpu)
728 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
732 free_irq(hdev->irq, hdev);
733 hdev->flags &= ~HPET_DEV_USED;
734 per_cpu(cpu_hpet_dev, cpu) = NULL;
739 static void hpet_msi_capability_lookup(unsigned int start_timer)
745 static void hpet_reserve_msi_timers(struct hpet_data *hd)
751 #define hpet_cpuhp_online NULL
752 #define hpet_cpuhp_dead NULL
757 * Clock source related code
759 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
761 * Reading the HPET counter is a very slow operation. If a large number of
762 * CPUs are trying to access the HPET counter simultaneously, it can cause
763 * massive delay and slow down system performance dramatically. This may
764 * happen when HPET is the default clock source instead of TSC. For a
765 * really large system with hundreds of CPUs, the slowdown may be so
766 * severe that it may actually crash the system because of a NMI watchdog
767 * soft lockup, for example.
769 * If multiple CPUs are trying to access the HPET counter at the same time,
770 * we don't actually need to read the counter multiple times. Instead, the
771 * other CPUs can use the counter value read by the first CPU in the group.
773 * This special feature is only enabled on x86-64 systems. It is unlikely
774 * that 32-bit x86 systems will have enough CPUs to require this feature
775 * with its associated locking overhead. And we also need 64-bit atomic
778 * The lock and the hpet value are stored together and can be read in a
779 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
780 * is 32 bits in size.
784 arch_spinlock_t lock;
790 static union hpet_lock hpet __cacheline_aligned = {
791 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
794 static cycle_t read_hpet(struct clocksource *cs)
797 union hpet_lock old, new;
799 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
802 * Read HPET directly if in NMI.
805 return (cycle_t)hpet_readl(HPET_COUNTER);
808 * Read the current state of the lock and HPET value atomically.
810 old.lockval = READ_ONCE(hpet.lockval);
812 if (arch_spin_is_locked(&old.lock))
815 local_irq_save(flags);
816 if (arch_spin_trylock(&hpet.lock)) {
817 new.value = hpet_readl(HPET_COUNTER);
819 * Use WRITE_ONCE() to prevent store tearing.
821 WRITE_ONCE(hpet.value, new.value);
822 arch_spin_unlock(&hpet.lock);
823 local_irq_restore(flags);
824 return (cycle_t)new.value;
826 local_irq_restore(flags);
832 * Wait until the HPET value change or the lock is free to indicate
833 * its value is up-to-date.
835 * It is possible that old.value has already contained the latest
836 * HPET value while the lock holder was in the process of releasing
837 * the lock. Checking for lock state change will enable us to return
838 * the value immediately instead of waiting for the next HPET reader
843 new.lockval = READ_ONCE(hpet.lockval);
844 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
846 return (cycle_t)new.value;
852 static cycle_t read_hpet(struct clocksource *cs)
854 return (cycle_t)hpet_readl(HPET_COUNTER);
858 static struct clocksource clocksource_hpet = {
863 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
864 .resume = hpet_resume_counter,
867 static int hpet_clocksource_register(void)
872 /* Start the counter */
873 hpet_restart_counter();
875 /* Verify whether hpet counter works */
876 t1 = hpet_readl(HPET_COUNTER);
880 * We don't know the TSC frequency yet, but waiting for
881 * 200000 TSC cycles is safe:
888 } while ((now - start) < 200000UL);
890 if (t1 == hpet_readl(HPET_COUNTER)) {
892 "HPET counter not counting. HPET disabled\n");
896 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
900 static u32 *hpet_boot_cfg;
903 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
905 int __init hpet_enable(void)
907 u32 hpet_period, cfg, id;
909 unsigned int i, last;
911 if (!is_hpet_capable())
917 * Read the period and check for a sane value:
919 hpet_period = hpet_readl(HPET_PERIOD);
922 * AMD SB700 based systems with spread spectrum enabled use a
923 * SMM based HPET emulation to provide proper frequency
924 * setting. The SMM code is initialized with the first HPET
925 * register access and takes some time to complete. During
926 * this time the config register reads 0xffffffff. We check
927 * for max. 1000 loops whether the config register reads a non
928 * 0xffffffff value to make sure that HPET is up and running
929 * before we go further. A counting loop is safe, as the HPET
930 * access takes thousands of CPU cycles. On non SB700 based
931 * machines this check is only done once and has no side
934 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
937 "HPET config register value = 0xFFFFFFFF. "
943 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
947 * The period is a femto seconds value. Convert it to a
951 do_div(freq, hpet_period);
955 * Read the HPET ID register to retrieve the IRQ routing
956 * information and the number of channels
958 id = hpet_readl(HPET_ID);
961 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
963 #ifdef CONFIG_HPET_EMULATE_RTC
965 * The legacy routing mode needs at least two channels, tick timer
966 * and the rtc emulation channel.
972 cfg = hpet_readl(HPET_CFG);
973 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
976 *hpet_boot_cfg = cfg;
978 pr_warn("HPET initial state will not be saved\n");
979 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
980 hpet_writel(cfg, HPET_CFG);
982 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
985 for (i = 0; i <= last; ++i) {
986 cfg = hpet_readl(HPET_Tn_CFG(i));
988 hpet_boot_cfg[i + 1] = cfg;
989 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
990 hpet_writel(cfg, HPET_Tn_CFG(i));
991 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
992 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
993 | HPET_TN_FSB | HPET_TN_FSB_CAP);
995 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
1000 if (hpet_clocksource_register())
1003 if (id & HPET_ID_LEGSUP) {
1004 hpet_legacy_clockevent_register();
1010 hpet_clear_mapping();
1016 * Needs to be late, as the reserve_timer code calls kalloc !
1018 * Not a problem on i386 as hpet_enable is called from late_time_init,
1019 * but on x86_64 it is necessary !
1021 static __init int hpet_late_init(void)
1025 if (boot_hpet_disable)
1028 if (!hpet_address) {
1029 if (!force_hpet_address)
1032 hpet_address = force_hpet_address;
1036 if (!hpet_virt_address)
1039 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
1040 hpet_msi_capability_lookup(2);
1042 hpet_msi_capability_lookup(0);
1044 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
1045 hpet_print_config();
1047 if (hpet_msi_disable)
1050 if (boot_cpu_has(X86_FEATURE_ARAT))
1053 /* This notifier should be called after workqueue is ready */
1054 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "AP_X86_HPET_ONLINE",
1055 hpet_cpuhp_online, NULL);
1058 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "X86_HPET_DEAD", NULL,
1065 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1068 fs_initcall(hpet_late_init);
1070 void hpet_disable(void)
1072 if (is_hpet_capable() && hpet_virt_address) {
1073 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
1076 cfg = *hpet_boot_cfg;
1077 else if (hpet_legacy_int_enabled) {
1078 cfg &= ~HPET_CFG_LEGACY;
1079 hpet_legacy_int_enabled = false;
1081 cfg &= ~HPET_CFG_ENABLE;
1082 hpet_writel(cfg, HPET_CFG);
1087 id = hpet_readl(HPET_ID);
1088 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
1090 for (id = 0; id <= last; ++id)
1091 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1093 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1094 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1098 #ifdef CONFIG_HPET_EMULATE_RTC
1100 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1101 * is enabled, we support RTC interrupt functionality in software.
1102 * RTC has 3 kinds of interrupts:
1103 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1105 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1106 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1107 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1108 * (1) and (2) above are implemented using polling at a frequency of
1109 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1110 * overhead. (DEFAULT_RTC_INT_FREQ)
1111 * For (3), we use interrupts at 64Hz or user specified periodic
1112 * frequency, whichever is higher.
1114 #include <linux/mc146818rtc.h>
1115 #include <linux/rtc.h>
1117 #define DEFAULT_RTC_INT_FREQ 64
1118 #define DEFAULT_RTC_SHIFT 6
1119 #define RTC_NUM_INTS 1
1121 static unsigned long hpet_rtc_flags;
1122 static int hpet_prev_update_sec;
1123 static struct rtc_time hpet_alarm_time;
1124 static unsigned long hpet_pie_count;
1125 static u32 hpet_t1_cmp;
1126 static u32 hpet_default_delta;
1127 static u32 hpet_pie_delta;
1128 static unsigned long hpet_pie_limit;
1130 static rtc_irq_handler irq_handler;
1133 * Check that the hpet counter c1 is ahead of the c2
1135 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1137 return (s32)(c2 - c1) < 0;
1141 * Registers a IRQ handler.
1143 int hpet_register_irq_handler(rtc_irq_handler handler)
1145 if (!is_hpet_enabled())
1150 irq_handler = handler;
1154 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1157 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1160 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1162 if (!is_hpet_enabled())
1168 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1171 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1172 * is not supported by all HPET implementations for timer 1.
1174 * hpet_rtc_timer_init() is called when the rtc is initialized.
1176 int hpet_rtc_timer_init(void)
1178 unsigned int cfg, cnt, delta;
1179 unsigned long flags;
1181 if (!is_hpet_enabled())
1184 if (!hpet_default_delta) {
1187 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1188 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1189 hpet_default_delta = clc;
1192 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1193 delta = hpet_default_delta;
1195 delta = hpet_pie_delta;
1197 local_irq_save(flags);
1199 cnt = delta + hpet_readl(HPET_COUNTER);
1200 hpet_writel(cnt, HPET_T1_CMP);
1203 cfg = hpet_readl(HPET_T1_CFG);
1204 cfg &= ~HPET_TN_PERIODIC;
1205 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1206 hpet_writel(cfg, HPET_T1_CFG);
1208 local_irq_restore(flags);
1212 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1214 static void hpet_disable_rtc_channel(void)
1216 u32 cfg = hpet_readl(HPET_T1_CFG);
1217 cfg &= ~HPET_TN_ENABLE;
1218 hpet_writel(cfg, HPET_T1_CFG);
1222 * The functions below are called from rtc driver.
1223 * Return 0 if HPET is not being used.
1224 * Otherwise do the necessary changes and return 1.
1226 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1228 if (!is_hpet_enabled())
1231 hpet_rtc_flags &= ~bit_mask;
1232 if (unlikely(!hpet_rtc_flags))
1233 hpet_disable_rtc_channel();
1237 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1239 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1241 unsigned long oldbits = hpet_rtc_flags;
1243 if (!is_hpet_enabled())
1246 hpet_rtc_flags |= bit_mask;
1248 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1249 hpet_prev_update_sec = -1;
1252 hpet_rtc_timer_init();
1256 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1258 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1261 if (!is_hpet_enabled())
1264 hpet_alarm_time.tm_hour = hrs;
1265 hpet_alarm_time.tm_min = min;
1266 hpet_alarm_time.tm_sec = sec;
1270 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1272 int hpet_set_periodic_freq(unsigned long freq)
1276 if (!is_hpet_enabled())
1279 if (freq <= DEFAULT_RTC_INT_FREQ)
1280 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1282 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1284 clc >>= hpet_clockevent.shift;
1285 hpet_pie_delta = clc;
1290 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1292 int hpet_rtc_dropped_irq(void)
1294 return is_hpet_enabled();
1296 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1298 static void hpet_rtc_timer_reinit(void)
1303 if (unlikely(!hpet_rtc_flags))
1304 hpet_disable_rtc_channel();
1306 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1307 delta = hpet_default_delta;
1309 delta = hpet_pie_delta;
1312 * Increment the comparator value until we are ahead of the
1316 hpet_t1_cmp += delta;
1317 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1319 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1322 if (hpet_rtc_flags & RTC_PIE)
1323 hpet_pie_count += lost_ints;
1324 if (printk_ratelimit())
1325 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1330 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1332 struct rtc_time curr_time;
1333 unsigned long rtc_int_flag = 0;
1335 hpet_rtc_timer_reinit();
1336 memset(&curr_time, 0, sizeof(struct rtc_time));
1338 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1339 mc146818_get_time(&curr_time);
1341 if (hpet_rtc_flags & RTC_UIE &&
1342 curr_time.tm_sec != hpet_prev_update_sec) {
1343 if (hpet_prev_update_sec >= 0)
1344 rtc_int_flag = RTC_UF;
1345 hpet_prev_update_sec = curr_time.tm_sec;
1348 if (hpet_rtc_flags & RTC_PIE &&
1349 ++hpet_pie_count >= hpet_pie_limit) {
1350 rtc_int_flag |= RTC_PF;
1354 if (hpet_rtc_flags & RTC_AIE &&
1355 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1356 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1357 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1358 rtc_int_flag |= RTC_AF;
1361 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1363 irq_handler(rtc_int_flag, dev_id);
1367 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);