1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/hpet.h>
8 #include <linux/init.h>
13 #include <asm/fixmap.h>
14 #include <asm/i8253.h>
17 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
35 unsigned long hpet_address;
36 u8 hpet_blockid; /* OS timer block num */
40 static unsigned long hpet_num_timers;
42 static void __iomem *hpet_virt_address;
45 struct clock_event_device evt;
53 inline unsigned int hpet_readl(unsigned int a)
55 return readl(hpet_virt_address + a);
58 static inline void hpet_writel(unsigned int d, unsigned int a)
60 writel(d, hpet_virt_address + a);
64 #include <asm/pgtable.h>
67 static inline void hpet_set_mapping(void)
69 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
71 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
75 static inline void hpet_clear_mapping(void)
77 iounmap(hpet_virt_address);
78 hpet_virt_address = NULL;
82 * HPET command line enable / disable
84 static int boot_hpet_disable;
86 static int hpet_verbose;
88 static int __init hpet_setup(char *str)
91 if (!strncmp("disable", str, 7))
92 boot_hpet_disable = 1;
93 if (!strncmp("force", str, 5))
95 if (!strncmp("verbose", str, 7))
100 __setup("hpet=", hpet_setup);
102 static int __init disable_hpet(char *str)
104 boot_hpet_disable = 1;
107 __setup("nohpet", disable_hpet);
109 static inline int is_hpet_capable(void)
111 return !boot_hpet_disable && hpet_address;
115 * HPET timer interrupt enable / disable
117 static int hpet_legacy_int_enabled;
120 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
122 int is_hpet_enabled(void)
124 return is_hpet_capable() && hpet_legacy_int_enabled;
126 EXPORT_SYMBOL_GPL(is_hpet_enabled);
128 static void _hpet_print_config(const char *function, int line)
131 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
132 l = hpet_readl(HPET_ID);
133 h = hpet_readl(HPET_PERIOD);
134 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
135 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
136 l = hpet_readl(HPET_CFG);
137 h = hpet_readl(HPET_STATUS);
138 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
139 l = hpet_readl(HPET_COUNTER);
140 h = hpet_readl(HPET_COUNTER+4);
141 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
143 for (i = 0; i < timers; i++) {
144 l = hpet_readl(HPET_Tn_CFG(i));
145 h = hpet_readl(HPET_Tn_CFG(i)+4);
146 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
148 l = hpet_readl(HPET_Tn_CMP(i));
149 h = hpet_readl(HPET_Tn_CMP(i)+4);
150 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
152 l = hpet_readl(HPET_Tn_ROUTE(i));
153 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
154 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
159 #define hpet_print_config() \
162 _hpet_print_config(__FUNCTION__, __LINE__); \
166 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
167 * timer 0 and timer 1 in case of RTC emulation.
171 static void hpet_reserve_msi_timers(struct hpet_data *hd);
173 static void hpet_reserve_platform_timers(unsigned int id)
175 struct hpet __iomem *hpet = hpet_virt_address;
176 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
177 unsigned int nrtimers, i;
180 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
182 memset(&hd, 0, sizeof(hd));
183 hd.hd_phys_address = hpet_address;
184 hd.hd_address = hpet;
185 hd.hd_nirqs = nrtimers;
186 hpet_reserve_timer(&hd, 0);
188 #ifdef CONFIG_HPET_EMULATE_RTC
189 hpet_reserve_timer(&hd, 1);
193 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
194 * is wrong for i8259!) not the output IRQ. Many BIOS writers
195 * don't bother configuring *any* comparator interrupts.
197 hd.hd_irq[0] = HPET_LEGACY_8254;
198 hd.hd_irq[1] = HPET_LEGACY_RTC;
200 for (i = 2; i < nrtimers; timer++, i++) {
201 hd.hd_irq[i] = (readl(&timer->hpet_config) &
202 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
205 hpet_reserve_msi_timers(&hd);
211 static void hpet_reserve_platform_timers(unsigned int id) { }
217 static unsigned long hpet_period;
219 static void hpet_legacy_set_mode(enum clock_event_mode mode,
220 struct clock_event_device *evt);
221 static int hpet_legacy_next_event(unsigned long delta,
222 struct clock_event_device *evt);
225 * The hpet clock event device
227 static struct clock_event_device hpet_clockevent = {
229 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
230 .set_mode = hpet_legacy_set_mode,
231 .set_next_event = hpet_legacy_next_event,
237 static void hpet_stop_counter(void)
239 unsigned long cfg = hpet_readl(HPET_CFG);
240 cfg &= ~HPET_CFG_ENABLE;
241 hpet_writel(cfg, HPET_CFG);
244 static void hpet_reset_counter(void)
246 hpet_writel(0, HPET_COUNTER);
247 hpet_writel(0, HPET_COUNTER + 4);
250 static void hpet_start_counter(void)
252 unsigned int cfg = hpet_readl(HPET_CFG);
253 cfg |= HPET_CFG_ENABLE;
254 hpet_writel(cfg, HPET_CFG);
257 static void hpet_restart_counter(void)
260 hpet_reset_counter();
261 hpet_start_counter();
264 static void hpet_resume_device(void)
269 static void hpet_resume_counter(void)
271 hpet_resume_device();
272 hpet_restart_counter();
275 static void hpet_enable_legacy_int(void)
277 unsigned int cfg = hpet_readl(HPET_CFG);
279 cfg |= HPET_CFG_LEGACY;
280 hpet_writel(cfg, HPET_CFG);
281 hpet_legacy_int_enabled = 1;
284 static void hpet_legacy_clockevent_register(void)
286 /* Start HPET legacy interrupts */
287 hpet_enable_legacy_int();
290 * The mult factor is defined as (include/linux/clockchips.h)
291 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
292 * hpet_period is in units of femtoseconds (per cycle), so
293 * mult/2^shift = cyc/ns = 10^6/hpet_period
294 * mult = (10^6 * 2^shift)/hpet_period
295 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
297 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
298 hpet_period, hpet_clockevent.shift);
299 /* Calculate the min / max delta */
300 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
302 /* 5 usec minimum reprogramming delta. */
303 hpet_clockevent.min_delta_ns = 5000;
306 * Start hpet with the boot cpu mask and make it
307 * global after the IO_APIC has been initialized.
309 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
310 clockevents_register_device(&hpet_clockevent);
311 global_clock_event = &hpet_clockevent;
312 printk(KERN_DEBUG "hpet clockevent registered\n");
315 static int hpet_setup_msi_irq(unsigned int irq);
317 static void hpet_set_mode(enum clock_event_mode mode,
318 struct clock_event_device *evt, int timer)
320 unsigned int cfg, cmp, now;
324 case CLOCK_EVT_MODE_PERIODIC:
326 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
327 delta >>= evt->shift;
328 now = hpet_readl(HPET_COUNTER);
329 cmp = now + (unsigned int) delta;
330 cfg = hpet_readl(HPET_Tn_CFG(timer));
331 /* Make sure we use edge triggered interrupts */
332 cfg &= ~HPET_TN_LEVEL;
333 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
334 HPET_TN_SETVAL | HPET_TN_32BIT;
335 hpet_writel(cfg, HPET_Tn_CFG(timer));
336 hpet_writel(cmp, HPET_Tn_CMP(timer));
339 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
340 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
341 * bit is automatically cleared after the first write.
342 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
343 * Publication # 24674)
345 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
346 hpet_start_counter();
350 case CLOCK_EVT_MODE_ONESHOT:
351 cfg = hpet_readl(HPET_Tn_CFG(timer));
352 cfg &= ~HPET_TN_PERIODIC;
353 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
354 hpet_writel(cfg, HPET_Tn_CFG(timer));
357 case CLOCK_EVT_MODE_UNUSED:
358 case CLOCK_EVT_MODE_SHUTDOWN:
359 cfg = hpet_readl(HPET_Tn_CFG(timer));
360 cfg &= ~HPET_TN_ENABLE;
361 hpet_writel(cfg, HPET_Tn_CFG(timer));
364 case CLOCK_EVT_MODE_RESUME:
366 hpet_enable_legacy_int();
368 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
369 hpet_setup_msi_irq(hdev->irq);
370 disable_irq(hdev->irq);
371 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
372 enable_irq(hdev->irq);
379 static int hpet_next_event(unsigned long delta,
380 struct clock_event_device *evt, int timer)
384 cnt = hpet_readl(HPET_COUNTER);
386 hpet_writel(cnt, HPET_Tn_CMP(timer));
389 * We need to read back the CMP register on certain HPET
390 * implementations (ATI chipsets) which seem to delay the
391 * transfer of the compare register into the internal compare
392 * logic. With small deltas this might actually be too late as
393 * the counter could already be higher than the compare value
394 * at that point and we would wait for the next hpet interrupt
395 * forever. We found out that reading the CMP register back
396 * forces the transfer so we can rely on the comparison with
397 * the counter register below. If the read back from the
398 * compare register does not match the value we programmed
399 * then we might have a real hardware problem. We can not do
400 * much about it here, but at least alert the user/admin with
401 * a prominent warning.
402 * An erratum on some chipsets (ICH9,..), results in comparator read
403 * immediately following a write returning old value. Workaround
404 * for this is to read this value second time, when first
405 * read returns old value.
407 if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
408 WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,
409 KERN_WARNING "hpet: compare register read back failed.\n");
412 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
415 static void hpet_legacy_set_mode(enum clock_event_mode mode,
416 struct clock_event_device *evt)
418 hpet_set_mode(mode, evt, 0);
421 static int hpet_legacy_next_event(unsigned long delta,
422 struct clock_event_device *evt)
424 return hpet_next_event(delta, evt, 0);
430 #ifdef CONFIG_PCI_MSI
432 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
433 static struct hpet_dev *hpet_devs;
435 void hpet_msi_unmask(unsigned int irq)
437 struct hpet_dev *hdev = get_irq_data(irq);
441 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
443 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
446 void hpet_msi_mask(unsigned int irq)
449 struct hpet_dev *hdev = get_irq_data(irq);
452 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
454 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
457 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
459 struct hpet_dev *hdev = get_irq_data(irq);
461 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
462 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
465 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
467 struct hpet_dev *hdev = get_irq_data(irq);
469 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
470 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
474 static void hpet_msi_set_mode(enum clock_event_mode mode,
475 struct clock_event_device *evt)
477 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
478 hpet_set_mode(mode, evt, hdev->num);
481 static int hpet_msi_next_event(unsigned long delta,
482 struct clock_event_device *evt)
484 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
485 return hpet_next_event(delta, evt, hdev->num);
488 static int hpet_setup_msi_irq(unsigned int irq)
490 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
497 static int hpet_assign_irq(struct hpet_dev *dev)
505 set_irq_data(irq, dev);
507 if (hpet_setup_msi_irq(irq))
514 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
516 struct hpet_dev *dev = (struct hpet_dev *)data;
517 struct clock_event_device *hevt = &dev->evt;
519 if (!hevt->event_handler) {
520 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
525 hevt->event_handler(hevt);
529 static int hpet_setup_irq(struct hpet_dev *dev)
532 if (request_irq(dev->irq, hpet_interrupt_handler,
533 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
537 disable_irq(dev->irq);
538 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
539 enable_irq(dev->irq);
541 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
542 dev->name, dev->irq);
547 /* This should be called in specific @cpu */
548 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
550 struct clock_event_device *evt = &hdev->evt;
553 WARN_ON(cpu != smp_processor_id());
554 if (!(hdev->flags & HPET_DEV_VALID))
557 if (hpet_setup_msi_irq(hdev->irq))
561 per_cpu(cpu_hpet_dev, cpu) = hdev;
562 evt->name = hdev->name;
563 hpet_setup_irq(hdev);
564 evt->irq = hdev->irq;
567 evt->features = CLOCK_EVT_FEAT_ONESHOT;
568 if (hdev->flags & HPET_DEV_PERI_CAP)
569 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
571 evt->set_mode = hpet_msi_set_mode;
572 evt->set_next_event = hpet_msi_next_event;
576 * The period is a femto seconds value. We need to calculate the
577 * scaled math multiplication factor for nanosecond to hpet tick
580 hpet_freq = 1000000000000000ULL;
581 do_div(hpet_freq, hpet_period);
582 evt->mult = div_sc((unsigned long) hpet_freq,
583 NSEC_PER_SEC, evt->shift);
584 /* Calculate the max delta */
585 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
586 /* 5 usec minimum reprogramming delta. */
587 evt->min_delta_ns = 5000;
589 evt->cpumask = cpumask_of(hdev->cpu);
590 clockevents_register_device(evt);
594 /* Reserve at least one timer for userspace (/dev/hpet) */
595 #define RESERVE_TIMERS 1
597 #define RESERVE_TIMERS 0
600 static void hpet_msi_capability_lookup(unsigned int start_timer)
603 unsigned int num_timers;
604 unsigned int num_timers_used = 0;
607 if (hpet_msi_disable)
610 if (boot_cpu_has(X86_FEATURE_ARAT))
612 id = hpet_readl(HPET_ID);
614 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
615 num_timers++; /* Value read out starts from 0 */
618 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
622 hpet_num_timers = num_timers;
624 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
625 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
626 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
628 /* Only consider HPET timer with MSI support */
629 if (!(cfg & HPET_TN_FSB_CAP))
633 if (cfg & HPET_TN_PERIODIC_CAP)
634 hdev->flags |= HPET_DEV_PERI_CAP;
637 sprintf(hdev->name, "hpet%d", i);
638 if (hpet_assign_irq(hdev))
641 hdev->flags |= HPET_DEV_FSB_CAP;
642 hdev->flags |= HPET_DEV_VALID;
644 if (num_timers_used == num_possible_cpus())
648 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
649 num_timers, num_timers_used);
653 static void hpet_reserve_msi_timers(struct hpet_data *hd)
660 for (i = 0; i < hpet_num_timers; i++) {
661 struct hpet_dev *hdev = &hpet_devs[i];
663 if (!(hdev->flags & HPET_DEV_VALID))
666 hd->hd_irq[hdev->num] = hdev->irq;
667 hpet_reserve_timer(hd, hdev->num);
672 static struct hpet_dev *hpet_get_unused_timer(void)
679 for (i = 0; i < hpet_num_timers; i++) {
680 struct hpet_dev *hdev = &hpet_devs[i];
682 if (!(hdev->flags & HPET_DEV_VALID))
684 if (test_and_set_bit(HPET_DEV_USED_BIT,
685 (unsigned long *)&hdev->flags))
692 struct hpet_work_struct {
693 struct delayed_work work;
694 struct completion complete;
697 static void hpet_work(struct work_struct *w)
699 struct hpet_dev *hdev;
700 int cpu = smp_processor_id();
701 struct hpet_work_struct *hpet_work;
703 hpet_work = container_of(w, struct hpet_work_struct, work.work);
705 hdev = hpet_get_unused_timer();
707 init_one_hpet_msi_clockevent(hdev, cpu);
709 complete(&hpet_work->complete);
712 static int hpet_cpuhp_notify(struct notifier_block *n,
713 unsigned long action, void *hcpu)
715 unsigned long cpu = (unsigned long)hcpu;
716 struct hpet_work_struct work;
717 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
719 switch (action & 0xf) {
721 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
722 init_completion(&work.complete);
723 /* FIXME: add schedule_work_on() */
724 schedule_delayed_work_on(cpu, &work.work, 0);
725 wait_for_completion(&work.complete);
726 destroy_timer_on_stack(&work.work.timer);
730 free_irq(hdev->irq, hdev);
731 hdev->flags &= ~HPET_DEV_USED;
732 per_cpu(cpu_hpet_dev, cpu) = NULL;
740 static int hpet_setup_msi_irq(unsigned int irq)
744 static void hpet_msi_capability_lookup(unsigned int start_timer)
750 static void hpet_reserve_msi_timers(struct hpet_data *hd)
756 static int hpet_cpuhp_notify(struct notifier_block *n,
757 unsigned long action, void *hcpu)
765 * Clock source related code
767 static cycle_t read_hpet(struct clocksource *cs)
769 return (cycle_t)hpet_readl(HPET_COUNTER);
773 static cycle_t __vsyscall_fn vread_hpet(void)
775 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
779 static struct clocksource clocksource_hpet = {
785 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
786 .resume = hpet_resume_counter,
792 static int hpet_clocksource_register(void)
797 /* Start the counter */
798 hpet_restart_counter();
800 /* Verify whether hpet counter works */
801 t1 = hpet_readl(HPET_COUNTER);
805 * We don't know the TSC frequency yet, but waiting for
806 * 200000 TSC cycles is safe:
813 } while ((now - start) < 200000UL);
815 if (t1 == hpet_readl(HPET_COUNTER)) {
817 "HPET counter not counting. HPET disabled\n");
822 * The definition of mult is (include/linux/clocksource.h)
823 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
824 * so we first need to convert hpet_period to ns/cyc units:
825 * mult/2^shift = ns/cyc = hpet_period/10^6
826 * mult = (hpet_period * 2^shift)/10^6
827 * mult = (hpet_period << shift)/FSEC_PER_NSEC
829 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
831 clocksource_register(&clocksource_hpet);
837 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
839 int __init hpet_enable(void)
844 if (!is_hpet_capable())
850 * Read the period and check for a sane value:
852 hpet_period = hpet_readl(HPET_PERIOD);
855 * AMD SB700 based systems with spread spectrum enabled use a
856 * SMM based HPET emulation to provide proper frequency
857 * setting. The SMM code is initialized with the first HPET
858 * register access and takes some time to complete. During
859 * this time the config register reads 0xffffffff. We check
860 * for max. 1000 loops whether the config register reads a non
861 * 0xffffffff value to make sure that HPET is up and running
862 * before we go further. A counting loop is safe, as the HPET
863 * access takes thousands of CPU cycles. On non SB700 based
864 * machines this check is only done once and has no side
867 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
870 "HPET config register value = 0xFFFFFFFF. "
876 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
880 * Read the HPET ID register to retrieve the IRQ routing
881 * information and the number of channels
883 id = hpet_readl(HPET_ID);
886 #ifdef CONFIG_HPET_EMULATE_RTC
888 * The legacy routing mode needs at least two channels, tick timer
889 * and the rtc emulation channel.
891 if (!(id & HPET_ID_NUMBER))
895 if (hpet_clocksource_register())
898 if (id & HPET_ID_LEGSUP) {
899 hpet_legacy_clockevent_register();
905 hpet_clear_mapping();
911 * Needs to be late, as the reserve_timer code calls kalloc !
913 * Not a problem on i386 as hpet_enable is called from late_time_init,
914 * but on x86_64 it is necessary !
916 static __init int hpet_late_init(void)
920 if (boot_hpet_disable)
924 if (!force_hpet_address)
927 hpet_address = force_hpet_address;
931 if (!hpet_virt_address)
934 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
935 hpet_msi_capability_lookup(2);
937 hpet_msi_capability_lookup(0);
939 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
942 if (hpet_msi_disable)
945 if (boot_cpu_has(X86_FEATURE_ARAT))
948 for_each_online_cpu(cpu) {
949 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
952 /* This notifier should be called after workqueue is ready */
953 hotcpu_notifier(hpet_cpuhp_notify, -20);
957 fs_initcall(hpet_late_init);
959 void hpet_disable(void)
961 if (is_hpet_capable()) {
962 unsigned int cfg = hpet_readl(HPET_CFG);
964 if (hpet_legacy_int_enabled) {
965 cfg &= ~HPET_CFG_LEGACY;
966 hpet_legacy_int_enabled = 0;
968 cfg &= ~HPET_CFG_ENABLE;
969 hpet_writel(cfg, HPET_CFG);
973 #ifdef CONFIG_HPET_EMULATE_RTC
975 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
976 * is enabled, we support RTC interrupt functionality in software.
977 * RTC has 3 kinds of interrupts:
978 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
980 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
981 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
982 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
983 * (1) and (2) above are implemented using polling at a frequency of
984 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
985 * overhead. (DEFAULT_RTC_INT_FREQ)
986 * For (3), we use interrupts at 64Hz or user specified periodic
987 * frequency, whichever is higher.
989 #include <linux/mc146818rtc.h>
990 #include <linux/rtc.h>
993 #define DEFAULT_RTC_INT_FREQ 64
994 #define DEFAULT_RTC_SHIFT 6
995 #define RTC_NUM_INTS 1
997 static unsigned long hpet_rtc_flags;
998 static int hpet_prev_update_sec;
999 static struct rtc_time hpet_alarm_time;
1000 static unsigned long hpet_pie_count;
1001 static u32 hpet_t1_cmp;
1002 static u32 hpet_default_delta;
1003 static u32 hpet_pie_delta;
1004 static unsigned long hpet_pie_limit;
1006 static rtc_irq_handler irq_handler;
1009 * Check that the hpet counter c1 is ahead of the c2
1011 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1013 return (s32)(c2 - c1) < 0;
1017 * Registers a IRQ handler.
1019 int hpet_register_irq_handler(rtc_irq_handler handler)
1021 if (!is_hpet_enabled())
1026 irq_handler = handler;
1030 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1033 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1036 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1038 if (!is_hpet_enabled())
1044 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1047 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1048 * is not supported by all HPET implementations for timer 1.
1050 * hpet_rtc_timer_init() is called when the rtc is initialized.
1052 int hpet_rtc_timer_init(void)
1054 unsigned int cfg, cnt, delta;
1055 unsigned long flags;
1057 if (!is_hpet_enabled())
1060 if (!hpet_default_delta) {
1063 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1064 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1065 hpet_default_delta = clc;
1068 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1069 delta = hpet_default_delta;
1071 delta = hpet_pie_delta;
1073 local_irq_save(flags);
1075 cnt = delta + hpet_readl(HPET_COUNTER);
1076 hpet_writel(cnt, HPET_T1_CMP);
1079 cfg = hpet_readl(HPET_T1_CFG);
1080 cfg &= ~HPET_TN_PERIODIC;
1081 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1082 hpet_writel(cfg, HPET_T1_CFG);
1084 local_irq_restore(flags);
1088 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1091 * The functions below are called from rtc driver.
1092 * Return 0 if HPET is not being used.
1093 * Otherwise do the necessary changes and return 1.
1095 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1097 if (!is_hpet_enabled())
1100 hpet_rtc_flags &= ~bit_mask;
1103 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1105 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1107 unsigned long oldbits = hpet_rtc_flags;
1109 if (!is_hpet_enabled())
1112 hpet_rtc_flags |= bit_mask;
1114 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1115 hpet_prev_update_sec = -1;
1118 hpet_rtc_timer_init();
1122 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1124 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1127 if (!is_hpet_enabled())
1130 hpet_alarm_time.tm_hour = hrs;
1131 hpet_alarm_time.tm_min = min;
1132 hpet_alarm_time.tm_sec = sec;
1136 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1138 int hpet_set_periodic_freq(unsigned long freq)
1142 if (!is_hpet_enabled())
1145 if (freq <= DEFAULT_RTC_INT_FREQ)
1146 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1148 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1150 clc >>= hpet_clockevent.shift;
1151 hpet_pie_delta = clc;
1155 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1157 int hpet_rtc_dropped_irq(void)
1159 return is_hpet_enabled();
1161 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1163 static void hpet_rtc_timer_reinit(void)
1165 unsigned int cfg, delta;
1168 if (unlikely(!hpet_rtc_flags)) {
1169 cfg = hpet_readl(HPET_T1_CFG);
1170 cfg &= ~HPET_TN_ENABLE;
1171 hpet_writel(cfg, HPET_T1_CFG);
1175 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1176 delta = hpet_default_delta;
1178 delta = hpet_pie_delta;
1181 * Increment the comparator value until we are ahead of the
1185 hpet_t1_cmp += delta;
1186 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1188 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1191 if (hpet_rtc_flags & RTC_PIE)
1192 hpet_pie_count += lost_ints;
1193 if (printk_ratelimit())
1194 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1199 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1201 struct rtc_time curr_time;
1202 unsigned long rtc_int_flag = 0;
1204 hpet_rtc_timer_reinit();
1205 memset(&curr_time, 0, sizeof(struct rtc_time));
1207 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1208 get_rtc_time(&curr_time);
1210 if (hpet_rtc_flags & RTC_UIE &&
1211 curr_time.tm_sec != hpet_prev_update_sec) {
1212 if (hpet_prev_update_sec >= 0)
1213 rtc_int_flag = RTC_UF;
1214 hpet_prev_update_sec = curr_time.tm_sec;
1217 if (hpet_rtc_flags & RTC_PIE &&
1218 ++hpet_pie_count >= hpet_pie_limit) {
1219 rtc_int_flag |= RTC_PF;
1223 if (hpet_rtc_flags & RTC_AIE &&
1224 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1225 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1226 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1227 rtc_int_flag |= RTC_AF;
1230 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1232 irq_handler(rtc_int_flag, dev_id);
1236 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);