1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/slab.h>
8 #include <linux/hpet.h>
9 #include <linux/init.h>
10 #include <linux/cpu.h>
14 #include <asm/fixmap.h>
15 #include <asm/i8253.h>
18 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
35 unsigned long hpet_address;
36 u8 hpet_blockid; /* OS timer block num */
40 static unsigned long hpet_num_timers;
42 static void __iomem *hpet_virt_address;
45 struct clock_event_device evt;
53 inline unsigned int hpet_readl(unsigned int a)
55 return readl(hpet_virt_address + a);
58 static inline void hpet_writel(unsigned int d, unsigned int a)
60 writel(d, hpet_virt_address + a);
64 #include <asm/pgtable.h>
67 static inline void hpet_set_mapping(void)
69 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
71 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
75 static inline void hpet_clear_mapping(void)
77 iounmap(hpet_virt_address);
78 hpet_virt_address = NULL;
82 * HPET command line enable / disable
84 static int boot_hpet_disable;
86 static int hpet_verbose;
88 static int __init hpet_setup(char *str)
91 if (!strncmp("disable", str, 7))
92 boot_hpet_disable = 1;
93 if (!strncmp("force", str, 5))
95 if (!strncmp("verbose", str, 7))
100 __setup("hpet=", hpet_setup);
102 static int __init disable_hpet(char *str)
104 boot_hpet_disable = 1;
107 __setup("nohpet", disable_hpet);
109 static inline int is_hpet_capable(void)
111 return !boot_hpet_disable && hpet_address;
115 * HPET timer interrupt enable / disable
117 static int hpet_legacy_int_enabled;
120 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
122 int is_hpet_enabled(void)
124 return is_hpet_capable() && hpet_legacy_int_enabled;
126 EXPORT_SYMBOL_GPL(is_hpet_enabled);
128 static void _hpet_print_config(const char *function, int line)
131 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
132 l = hpet_readl(HPET_ID);
133 h = hpet_readl(HPET_PERIOD);
134 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
135 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
136 l = hpet_readl(HPET_CFG);
137 h = hpet_readl(HPET_STATUS);
138 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
139 l = hpet_readl(HPET_COUNTER);
140 h = hpet_readl(HPET_COUNTER+4);
141 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
143 for (i = 0; i < timers; i++) {
144 l = hpet_readl(HPET_Tn_CFG(i));
145 h = hpet_readl(HPET_Tn_CFG(i)+4);
146 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
148 l = hpet_readl(HPET_Tn_CMP(i));
149 h = hpet_readl(HPET_Tn_CMP(i)+4);
150 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
152 l = hpet_readl(HPET_Tn_ROUTE(i));
153 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
154 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
159 #define hpet_print_config() \
162 _hpet_print_config(__FUNCTION__, __LINE__); \
166 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
167 * timer 0 and timer 1 in case of RTC emulation.
171 static void hpet_reserve_msi_timers(struct hpet_data *hd);
173 static void hpet_reserve_platform_timers(unsigned int id)
175 struct hpet __iomem *hpet = hpet_virt_address;
176 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
177 unsigned int nrtimers, i;
180 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
182 memset(&hd, 0, sizeof(hd));
183 hd.hd_phys_address = hpet_address;
184 hd.hd_address = hpet;
185 hd.hd_nirqs = nrtimers;
186 hpet_reserve_timer(&hd, 0);
188 #ifdef CONFIG_HPET_EMULATE_RTC
189 hpet_reserve_timer(&hd, 1);
193 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
194 * is wrong for i8259!) not the output IRQ. Many BIOS writers
195 * don't bother configuring *any* comparator interrupts.
197 hd.hd_irq[0] = HPET_LEGACY_8254;
198 hd.hd_irq[1] = HPET_LEGACY_RTC;
200 for (i = 2; i < nrtimers; timer++, i++) {
201 hd.hd_irq[i] = (readl(&timer->hpet_config) &
202 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
205 hpet_reserve_msi_timers(&hd);
211 static void hpet_reserve_platform_timers(unsigned int id) { }
217 static unsigned long hpet_period;
219 static void hpet_legacy_set_mode(enum clock_event_mode mode,
220 struct clock_event_device *evt);
221 static int hpet_legacy_next_event(unsigned long delta,
222 struct clock_event_device *evt);
225 * The hpet clock event device
227 static struct clock_event_device hpet_clockevent = {
229 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
230 .set_mode = hpet_legacy_set_mode,
231 .set_next_event = hpet_legacy_next_event,
237 static void hpet_stop_counter(void)
239 unsigned long cfg = hpet_readl(HPET_CFG);
240 cfg &= ~HPET_CFG_ENABLE;
241 hpet_writel(cfg, HPET_CFG);
244 static void hpet_reset_counter(void)
246 hpet_writel(0, HPET_COUNTER);
247 hpet_writel(0, HPET_COUNTER + 4);
250 static void hpet_start_counter(void)
252 unsigned int cfg = hpet_readl(HPET_CFG);
253 cfg |= HPET_CFG_ENABLE;
254 hpet_writel(cfg, HPET_CFG);
257 static void hpet_restart_counter(void)
260 hpet_reset_counter();
261 hpet_start_counter();
264 static void hpet_resume_device(void)
269 static void hpet_resume_counter(struct clocksource *cs)
271 hpet_resume_device();
272 hpet_restart_counter();
275 static void hpet_enable_legacy_int(void)
277 unsigned int cfg = hpet_readl(HPET_CFG);
279 cfg |= HPET_CFG_LEGACY;
280 hpet_writel(cfg, HPET_CFG);
281 hpet_legacy_int_enabled = 1;
284 static void hpet_legacy_clockevent_register(void)
286 /* Start HPET legacy interrupts */
287 hpet_enable_legacy_int();
290 * The mult factor is defined as (include/linux/clockchips.h)
291 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
292 * hpet_period is in units of femtoseconds (per cycle), so
293 * mult/2^shift = cyc/ns = 10^6/hpet_period
294 * mult = (10^6 * 2^shift)/hpet_period
295 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
297 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
298 hpet_period, hpet_clockevent.shift);
299 /* Calculate the min / max delta */
300 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
302 /* 5 usec minimum reprogramming delta. */
303 hpet_clockevent.min_delta_ns = 5000;
306 * Start hpet with the boot cpu mask and make it
307 * global after the IO_APIC has been initialized.
309 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
310 clockevents_register_device(&hpet_clockevent);
311 global_clock_event = &hpet_clockevent;
312 printk(KERN_DEBUG "hpet clockevent registered\n");
315 static int hpet_setup_msi_irq(unsigned int irq);
317 static void hpet_set_mode(enum clock_event_mode mode,
318 struct clock_event_device *evt, int timer)
320 unsigned int cfg, cmp, now;
324 case CLOCK_EVT_MODE_PERIODIC:
326 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
327 delta >>= evt->shift;
328 now = hpet_readl(HPET_COUNTER);
329 cmp = now + (unsigned int) delta;
330 cfg = hpet_readl(HPET_Tn_CFG(timer));
331 /* Make sure we use edge triggered interrupts */
332 cfg &= ~HPET_TN_LEVEL;
333 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
334 HPET_TN_SETVAL | HPET_TN_32BIT;
335 hpet_writel(cfg, HPET_Tn_CFG(timer));
336 hpet_writel(cmp, HPET_Tn_CMP(timer));
339 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
340 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
341 * bit is automatically cleared after the first write.
342 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
343 * Publication # 24674)
345 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
346 hpet_start_counter();
350 case CLOCK_EVT_MODE_ONESHOT:
351 cfg = hpet_readl(HPET_Tn_CFG(timer));
352 cfg &= ~HPET_TN_PERIODIC;
353 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
354 hpet_writel(cfg, HPET_Tn_CFG(timer));
357 case CLOCK_EVT_MODE_UNUSED:
358 case CLOCK_EVT_MODE_SHUTDOWN:
359 cfg = hpet_readl(HPET_Tn_CFG(timer));
360 cfg &= ~HPET_TN_ENABLE;
361 hpet_writel(cfg, HPET_Tn_CFG(timer));
364 case CLOCK_EVT_MODE_RESUME:
366 hpet_enable_legacy_int();
368 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
369 hpet_setup_msi_irq(hdev->irq);
370 disable_irq(hdev->irq);
371 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
372 enable_irq(hdev->irq);
379 static int hpet_next_event(unsigned long delta,
380 struct clock_event_device *evt, int timer)
385 cnt = hpet_readl(HPET_COUNTER);
387 hpet_writel(cnt, HPET_Tn_CMP(timer));
390 * HPETs are a complete disaster. The compare register is
391 * based on a equal comparison and neither provides a less
392 * than or equal functionality (which would require to take
393 * the wraparound into account) nor a simple count down event
394 * mode. Further the write to the comparator register is
395 * delayed internally up to two HPET clock cycles in certain
396 * chipsets (ATI, ICH9,10). We worked around that by reading
397 * back the compare register, but that required another
398 * workaround for ICH9,10 chips where the first readout after
399 * write can return the old stale value. We already have a
400 * minimum delta of 5us enforced, but a NMI or SMI hitting
401 * between the counter readout and the comparator write can
402 * move us behind that point easily. Now instead of reading
403 * the compare register back several times, we make the ETIME
404 * decision based on the following: Return ETIME if the
405 * counter value after the write is less than 8 HPET cycles
406 * away from the event or if the counter is already ahead of
409 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
411 return res < 8 ? -ETIME : 0;
414 static void hpet_legacy_set_mode(enum clock_event_mode mode,
415 struct clock_event_device *evt)
417 hpet_set_mode(mode, evt, 0);
420 static int hpet_legacy_next_event(unsigned long delta,
421 struct clock_event_device *evt)
423 return hpet_next_event(delta, evt, 0);
429 #ifdef CONFIG_PCI_MSI
431 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
432 static struct hpet_dev *hpet_devs;
434 void hpet_msi_unmask(struct irq_data *data)
436 struct hpet_dev *hdev = data->handler_data;
440 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
442 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
445 void hpet_msi_mask(struct irq_data *data)
447 struct hpet_dev *hdev = data->handler_data;
451 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
453 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
456 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
458 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
459 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
462 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
464 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
465 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
469 static void hpet_msi_set_mode(enum clock_event_mode mode,
470 struct clock_event_device *evt)
472 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
473 hpet_set_mode(mode, evt, hdev->num);
476 static int hpet_msi_next_event(unsigned long delta,
477 struct clock_event_device *evt)
479 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
480 return hpet_next_event(delta, evt, hdev->num);
483 static int hpet_setup_msi_irq(unsigned int irq)
485 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
492 static int hpet_assign_irq(struct hpet_dev *dev)
496 irq = create_irq_nr(0, -1);
500 set_irq_data(irq, dev);
502 if (hpet_setup_msi_irq(irq))
509 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
511 struct hpet_dev *dev = (struct hpet_dev *)data;
512 struct clock_event_device *hevt = &dev->evt;
514 if (!hevt->event_handler) {
515 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
520 hevt->event_handler(hevt);
524 static int hpet_setup_irq(struct hpet_dev *dev)
527 if (request_irq(dev->irq, hpet_interrupt_handler,
528 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
532 disable_irq(dev->irq);
533 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
534 enable_irq(dev->irq);
536 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
537 dev->name, dev->irq);
542 /* This should be called in specific @cpu */
543 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
545 struct clock_event_device *evt = &hdev->evt;
548 WARN_ON(cpu != smp_processor_id());
549 if (!(hdev->flags & HPET_DEV_VALID))
552 if (hpet_setup_msi_irq(hdev->irq))
556 per_cpu(cpu_hpet_dev, cpu) = hdev;
557 evt->name = hdev->name;
558 hpet_setup_irq(hdev);
559 evt->irq = hdev->irq;
562 evt->features = CLOCK_EVT_FEAT_ONESHOT;
563 if (hdev->flags & HPET_DEV_PERI_CAP)
564 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
566 evt->set_mode = hpet_msi_set_mode;
567 evt->set_next_event = hpet_msi_next_event;
571 * The period is a femto seconds value. We need to calculate the
572 * scaled math multiplication factor for nanosecond to hpet tick
575 hpet_freq = FSEC_PER_SEC;
576 do_div(hpet_freq, hpet_period);
577 evt->mult = div_sc((unsigned long) hpet_freq,
578 NSEC_PER_SEC, evt->shift);
579 /* Calculate the max delta */
580 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
581 /* 5 usec minimum reprogramming delta. */
582 evt->min_delta_ns = 5000;
584 evt->cpumask = cpumask_of(hdev->cpu);
585 clockevents_register_device(evt);
589 /* Reserve at least one timer for userspace (/dev/hpet) */
590 #define RESERVE_TIMERS 1
592 #define RESERVE_TIMERS 0
595 static void hpet_msi_capability_lookup(unsigned int start_timer)
598 unsigned int num_timers;
599 unsigned int num_timers_used = 0;
602 if (hpet_msi_disable)
605 if (boot_cpu_has(X86_FEATURE_ARAT))
607 id = hpet_readl(HPET_ID);
609 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
610 num_timers++; /* Value read out starts from 0 */
613 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
617 hpet_num_timers = num_timers;
619 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
620 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
621 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
623 /* Only consider HPET timer with MSI support */
624 if (!(cfg & HPET_TN_FSB_CAP))
628 if (cfg & HPET_TN_PERIODIC_CAP)
629 hdev->flags |= HPET_DEV_PERI_CAP;
632 sprintf(hdev->name, "hpet%d", i);
633 if (hpet_assign_irq(hdev))
636 hdev->flags |= HPET_DEV_FSB_CAP;
637 hdev->flags |= HPET_DEV_VALID;
639 if (num_timers_used == num_possible_cpus())
643 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
644 num_timers, num_timers_used);
648 static void hpet_reserve_msi_timers(struct hpet_data *hd)
655 for (i = 0; i < hpet_num_timers; i++) {
656 struct hpet_dev *hdev = &hpet_devs[i];
658 if (!(hdev->flags & HPET_DEV_VALID))
661 hd->hd_irq[hdev->num] = hdev->irq;
662 hpet_reserve_timer(hd, hdev->num);
667 static struct hpet_dev *hpet_get_unused_timer(void)
674 for (i = 0; i < hpet_num_timers; i++) {
675 struct hpet_dev *hdev = &hpet_devs[i];
677 if (!(hdev->flags & HPET_DEV_VALID))
679 if (test_and_set_bit(HPET_DEV_USED_BIT,
680 (unsigned long *)&hdev->flags))
687 struct hpet_work_struct {
688 struct delayed_work work;
689 struct completion complete;
692 static void hpet_work(struct work_struct *w)
694 struct hpet_dev *hdev;
695 int cpu = smp_processor_id();
696 struct hpet_work_struct *hpet_work;
698 hpet_work = container_of(w, struct hpet_work_struct, work.work);
700 hdev = hpet_get_unused_timer();
702 init_one_hpet_msi_clockevent(hdev, cpu);
704 complete(&hpet_work->complete);
707 static int hpet_cpuhp_notify(struct notifier_block *n,
708 unsigned long action, void *hcpu)
710 unsigned long cpu = (unsigned long)hcpu;
711 struct hpet_work_struct work;
712 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
714 switch (action & 0xf) {
716 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
717 init_completion(&work.complete);
718 /* FIXME: add schedule_work_on() */
719 schedule_delayed_work_on(cpu, &work.work, 0);
720 wait_for_completion(&work.complete);
721 destroy_timer_on_stack(&work.work.timer);
725 free_irq(hdev->irq, hdev);
726 hdev->flags &= ~HPET_DEV_USED;
727 per_cpu(cpu_hpet_dev, cpu) = NULL;
735 static int hpet_setup_msi_irq(unsigned int irq)
739 static void hpet_msi_capability_lookup(unsigned int start_timer)
745 static void hpet_reserve_msi_timers(struct hpet_data *hd)
751 static int hpet_cpuhp_notify(struct notifier_block *n,
752 unsigned long action, void *hcpu)
760 * Clock source related code
762 static cycle_t read_hpet(struct clocksource *cs)
764 return (cycle_t)hpet_readl(HPET_COUNTER);
768 static cycle_t __vsyscall_fn vread_hpet(void)
770 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
774 static struct clocksource clocksource_hpet = {
779 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
780 .resume = hpet_resume_counter,
786 static int hpet_clocksource_register(void)
792 /* Start the counter */
793 hpet_restart_counter();
795 /* Verify whether hpet counter works */
796 t1 = hpet_readl(HPET_COUNTER);
800 * We don't know the TSC frequency yet, but waiting for
801 * 200000 TSC cycles is safe:
808 } while ((now - start) < 200000UL);
810 if (t1 == hpet_readl(HPET_COUNTER)) {
812 "HPET counter not counting. HPET disabled\n");
817 * The definition of mult is (include/linux/clocksource.h)
818 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
819 * so we first need to convert hpet_period to ns/cyc units:
820 * mult/2^shift = ns/cyc = hpet_period/10^6
821 * mult = (hpet_period * 2^shift)/10^6
822 * mult = (hpet_period << shift)/FSEC_PER_NSEC
825 /* Need to convert hpet_period (fsec/cyc) to cyc/sec:
827 * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc)
828 * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period
830 hpet_freq = FSEC_PER_SEC;
831 do_div(hpet_freq, hpet_period);
832 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
838 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
840 int __init hpet_enable(void)
845 if (!is_hpet_capable())
851 * Read the period and check for a sane value:
853 hpet_period = hpet_readl(HPET_PERIOD);
856 * AMD SB700 based systems with spread spectrum enabled use a
857 * SMM based HPET emulation to provide proper frequency
858 * setting. The SMM code is initialized with the first HPET
859 * register access and takes some time to complete. During
860 * this time the config register reads 0xffffffff. We check
861 * for max. 1000 loops whether the config register reads a non
862 * 0xffffffff value to make sure that HPET is up and running
863 * before we go further. A counting loop is safe, as the HPET
864 * access takes thousands of CPU cycles. On non SB700 based
865 * machines this check is only done once and has no side
868 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
871 "HPET config register value = 0xFFFFFFFF. "
877 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
881 * Read the HPET ID register to retrieve the IRQ routing
882 * information and the number of channels
884 id = hpet_readl(HPET_ID);
887 #ifdef CONFIG_HPET_EMULATE_RTC
889 * The legacy routing mode needs at least two channels, tick timer
890 * and the rtc emulation channel.
892 if (!(id & HPET_ID_NUMBER))
896 if (hpet_clocksource_register())
899 if (id & HPET_ID_LEGSUP) {
900 hpet_legacy_clockevent_register();
906 hpet_clear_mapping();
912 * Needs to be late, as the reserve_timer code calls kalloc !
914 * Not a problem on i386 as hpet_enable is called from late_time_init,
915 * but on x86_64 it is necessary !
917 static __init int hpet_late_init(void)
921 if (boot_hpet_disable)
925 if (!force_hpet_address)
928 hpet_address = force_hpet_address;
932 if (!hpet_virt_address)
935 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
936 hpet_msi_capability_lookup(2);
938 hpet_msi_capability_lookup(0);
940 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
943 if (hpet_msi_disable)
946 if (boot_cpu_has(X86_FEATURE_ARAT))
949 for_each_online_cpu(cpu) {
950 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
953 /* This notifier should be called after workqueue is ready */
954 hotcpu_notifier(hpet_cpuhp_notify, -20);
958 fs_initcall(hpet_late_init);
960 void hpet_disable(void)
962 if (is_hpet_capable() && hpet_virt_address) {
963 unsigned int cfg = hpet_readl(HPET_CFG);
965 if (hpet_legacy_int_enabled) {
966 cfg &= ~HPET_CFG_LEGACY;
967 hpet_legacy_int_enabled = 0;
969 cfg &= ~HPET_CFG_ENABLE;
970 hpet_writel(cfg, HPET_CFG);
974 #ifdef CONFIG_HPET_EMULATE_RTC
976 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
977 * is enabled, we support RTC interrupt functionality in software.
978 * RTC has 3 kinds of interrupts:
979 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
981 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
982 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
983 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
984 * (1) and (2) above are implemented using polling at a frequency of
985 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
986 * overhead. (DEFAULT_RTC_INT_FREQ)
987 * For (3), we use interrupts at 64Hz or user specified periodic
988 * frequency, whichever is higher.
990 #include <linux/mc146818rtc.h>
991 #include <linux/rtc.h>
994 #define DEFAULT_RTC_INT_FREQ 64
995 #define DEFAULT_RTC_SHIFT 6
996 #define RTC_NUM_INTS 1
998 static unsigned long hpet_rtc_flags;
999 static int hpet_prev_update_sec;
1000 static struct rtc_time hpet_alarm_time;
1001 static unsigned long hpet_pie_count;
1002 static u32 hpet_t1_cmp;
1003 static u32 hpet_default_delta;
1004 static u32 hpet_pie_delta;
1005 static unsigned long hpet_pie_limit;
1007 static rtc_irq_handler irq_handler;
1010 * Check that the hpet counter c1 is ahead of the c2
1012 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1014 return (s32)(c2 - c1) < 0;
1018 * Registers a IRQ handler.
1020 int hpet_register_irq_handler(rtc_irq_handler handler)
1022 if (!is_hpet_enabled())
1027 irq_handler = handler;
1031 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1034 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1037 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1039 if (!is_hpet_enabled())
1045 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1048 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1049 * is not supported by all HPET implementations for timer 1.
1051 * hpet_rtc_timer_init() is called when the rtc is initialized.
1053 int hpet_rtc_timer_init(void)
1055 unsigned int cfg, cnt, delta;
1056 unsigned long flags;
1058 if (!is_hpet_enabled())
1061 if (!hpet_default_delta) {
1064 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1065 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1066 hpet_default_delta = clc;
1069 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1070 delta = hpet_default_delta;
1072 delta = hpet_pie_delta;
1074 local_irq_save(flags);
1076 cnt = delta + hpet_readl(HPET_COUNTER);
1077 hpet_writel(cnt, HPET_T1_CMP);
1080 cfg = hpet_readl(HPET_T1_CFG);
1081 cfg &= ~HPET_TN_PERIODIC;
1082 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1083 hpet_writel(cfg, HPET_T1_CFG);
1085 local_irq_restore(flags);
1089 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1092 * The functions below are called from rtc driver.
1093 * Return 0 if HPET is not being used.
1094 * Otherwise do the necessary changes and return 1.
1096 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1098 if (!is_hpet_enabled())
1101 hpet_rtc_flags &= ~bit_mask;
1104 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1106 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1108 unsigned long oldbits = hpet_rtc_flags;
1110 if (!is_hpet_enabled())
1113 hpet_rtc_flags |= bit_mask;
1115 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1116 hpet_prev_update_sec = -1;
1119 hpet_rtc_timer_init();
1123 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1125 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1128 if (!is_hpet_enabled())
1131 hpet_alarm_time.tm_hour = hrs;
1132 hpet_alarm_time.tm_min = min;
1133 hpet_alarm_time.tm_sec = sec;
1137 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1139 int hpet_set_periodic_freq(unsigned long freq)
1143 if (!is_hpet_enabled())
1146 if (freq <= DEFAULT_RTC_INT_FREQ)
1147 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1149 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1151 clc >>= hpet_clockevent.shift;
1152 hpet_pie_delta = clc;
1157 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1159 int hpet_rtc_dropped_irq(void)
1161 return is_hpet_enabled();
1163 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1165 static void hpet_rtc_timer_reinit(void)
1167 unsigned int cfg, delta;
1170 if (unlikely(!hpet_rtc_flags)) {
1171 cfg = hpet_readl(HPET_T1_CFG);
1172 cfg &= ~HPET_TN_ENABLE;
1173 hpet_writel(cfg, HPET_T1_CFG);
1177 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1178 delta = hpet_default_delta;
1180 delta = hpet_pie_delta;
1183 * Increment the comparator value until we are ahead of the
1187 hpet_t1_cmp += delta;
1188 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1190 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1193 if (hpet_rtc_flags & RTC_PIE)
1194 hpet_pie_count += lost_ints;
1195 if (printk_ratelimit())
1196 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1201 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1203 struct rtc_time curr_time;
1204 unsigned long rtc_int_flag = 0;
1206 hpet_rtc_timer_reinit();
1207 memset(&curr_time, 0, sizeof(struct rtc_time));
1209 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1210 get_rtc_time(&curr_time);
1212 if (hpet_rtc_flags & RTC_UIE &&
1213 curr_time.tm_sec != hpet_prev_update_sec) {
1214 if (hpet_prev_update_sec >= 0)
1215 rtc_int_flag = RTC_UF;
1216 hpet_prev_update_sec = curr_time.tm_sec;
1219 if (hpet_rtc_flags & RTC_PIE &&
1220 ++hpet_pie_count >= hpet_pie_limit) {
1221 rtc_int_flag |= RTC_PF;
1225 if (hpet_rtc_flags & RTC_AIE &&
1226 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1227 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1228 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1229 rtc_int_flag |= RTC_AF;
1232 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1234 irq_handler(rtc_int_flag, dev_id);
1238 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);