1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/sysdev.h>
5 #include <linux/delay.h>
6 #include <linux/errno.h>
7 #include <linux/slab.h>
8 #include <linux/hpet.h>
9 #include <linux/init.h>
10 #include <linux/cpu.h>
14 #include <asm/fixmap.h>
15 #include <asm/i8253.h>
18 #define HPET_MASK CLOCKSOURCE_MASK(32)
22 #define FSEC_PER_NSEC 1000000L
24 #define HPET_DEV_USED_BIT 2
25 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26 #define HPET_DEV_VALID 0x8
27 #define HPET_DEV_FSB_CAP 0x1000
28 #define HPET_DEV_PERI_CAP 0x2000
30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
35 unsigned long hpet_address;
36 u8 hpet_blockid; /* OS timer block num */
41 static unsigned long hpet_num_timers;
43 static void __iomem *hpet_virt_address;
46 struct clock_event_device evt;
54 inline unsigned int hpet_readl(unsigned int a)
56 return readl(hpet_virt_address + a);
59 static inline void hpet_writel(unsigned int d, unsigned int a)
61 writel(d, hpet_virt_address + a);
65 #include <asm/pgtable.h>
68 static inline void hpet_set_mapping(void)
70 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
72 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
76 static inline void hpet_clear_mapping(void)
78 iounmap(hpet_virt_address);
79 hpet_virt_address = NULL;
83 * HPET command line enable / disable
85 static int boot_hpet_disable;
87 static int hpet_verbose;
89 static int __init hpet_setup(char *str)
92 if (!strncmp("disable", str, 7))
93 boot_hpet_disable = 1;
94 if (!strncmp("force", str, 5))
96 if (!strncmp("verbose", str, 7))
101 __setup("hpet=", hpet_setup);
103 static int __init disable_hpet(char *str)
105 boot_hpet_disable = 1;
108 __setup("nohpet", disable_hpet);
110 static inline int is_hpet_capable(void)
112 return !boot_hpet_disable && hpet_address;
116 * HPET timer interrupt enable / disable
118 static int hpet_legacy_int_enabled;
121 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
123 int is_hpet_enabled(void)
125 return is_hpet_capable() && hpet_legacy_int_enabled;
127 EXPORT_SYMBOL_GPL(is_hpet_enabled);
129 static void _hpet_print_config(const char *function, int line)
132 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
133 l = hpet_readl(HPET_ID);
134 h = hpet_readl(HPET_PERIOD);
135 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
136 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
137 l = hpet_readl(HPET_CFG);
138 h = hpet_readl(HPET_STATUS);
139 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
140 l = hpet_readl(HPET_COUNTER);
141 h = hpet_readl(HPET_COUNTER+4);
142 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
144 for (i = 0; i < timers; i++) {
145 l = hpet_readl(HPET_Tn_CFG(i));
146 h = hpet_readl(HPET_Tn_CFG(i)+4);
147 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
149 l = hpet_readl(HPET_Tn_CMP(i));
150 h = hpet_readl(HPET_Tn_CMP(i)+4);
151 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
153 l = hpet_readl(HPET_Tn_ROUTE(i));
154 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
155 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
160 #define hpet_print_config() \
163 _hpet_print_config(__FUNCTION__, __LINE__); \
167 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
168 * timer 0 and timer 1 in case of RTC emulation.
172 static void hpet_reserve_msi_timers(struct hpet_data *hd);
174 static void hpet_reserve_platform_timers(unsigned int id)
176 struct hpet __iomem *hpet = hpet_virt_address;
177 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
178 unsigned int nrtimers, i;
181 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
183 memset(&hd, 0, sizeof(hd));
184 hd.hd_phys_address = hpet_address;
185 hd.hd_address = hpet;
186 hd.hd_nirqs = nrtimers;
187 hpet_reserve_timer(&hd, 0);
189 #ifdef CONFIG_HPET_EMULATE_RTC
190 hpet_reserve_timer(&hd, 1);
194 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
195 * is wrong for i8259!) not the output IRQ. Many BIOS writers
196 * don't bother configuring *any* comparator interrupts.
198 hd.hd_irq[0] = HPET_LEGACY_8254;
199 hd.hd_irq[1] = HPET_LEGACY_RTC;
201 for (i = 2; i < nrtimers; timer++, i++) {
202 hd.hd_irq[i] = (readl(&timer->hpet_config) &
203 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
206 hpet_reserve_msi_timers(&hd);
212 static void hpet_reserve_platform_timers(unsigned int id) { }
218 static unsigned long hpet_period;
220 static void hpet_legacy_set_mode(enum clock_event_mode mode,
221 struct clock_event_device *evt);
222 static int hpet_legacy_next_event(unsigned long delta,
223 struct clock_event_device *evt);
226 * The hpet clock event device
228 static struct clock_event_device hpet_clockevent = {
230 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
231 .set_mode = hpet_legacy_set_mode,
232 .set_next_event = hpet_legacy_next_event,
238 static void hpet_stop_counter(void)
240 unsigned long cfg = hpet_readl(HPET_CFG);
241 cfg &= ~HPET_CFG_ENABLE;
242 hpet_writel(cfg, HPET_CFG);
245 static void hpet_reset_counter(void)
247 hpet_writel(0, HPET_COUNTER);
248 hpet_writel(0, HPET_COUNTER + 4);
251 static void hpet_start_counter(void)
253 unsigned int cfg = hpet_readl(HPET_CFG);
254 cfg |= HPET_CFG_ENABLE;
255 hpet_writel(cfg, HPET_CFG);
258 static void hpet_restart_counter(void)
261 hpet_reset_counter();
262 hpet_start_counter();
265 static void hpet_resume_device(void)
270 static void hpet_resume_counter(struct clocksource *cs)
272 hpet_resume_device();
273 hpet_restart_counter();
276 static void hpet_enable_legacy_int(void)
278 unsigned int cfg = hpet_readl(HPET_CFG);
280 cfg |= HPET_CFG_LEGACY;
281 hpet_writel(cfg, HPET_CFG);
282 hpet_legacy_int_enabled = 1;
285 static void hpet_legacy_clockevent_register(void)
287 /* Start HPET legacy interrupts */
288 hpet_enable_legacy_int();
291 * The mult factor is defined as (include/linux/clockchips.h)
292 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
293 * hpet_period is in units of femtoseconds (per cycle), so
294 * mult/2^shift = cyc/ns = 10^6/hpet_period
295 * mult = (10^6 * 2^shift)/hpet_period
296 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
298 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
299 hpet_period, hpet_clockevent.shift);
300 /* Calculate the min / max delta */
301 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
303 /* 5 usec minimum reprogramming delta. */
304 hpet_clockevent.min_delta_ns = 5000;
307 * Start hpet with the boot cpu mask and make it
308 * global after the IO_APIC has been initialized.
310 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
311 clockevents_register_device(&hpet_clockevent);
312 global_clock_event = &hpet_clockevent;
313 printk(KERN_DEBUG "hpet clockevent registered\n");
316 static int hpet_setup_msi_irq(unsigned int irq);
318 static void hpet_set_mode(enum clock_event_mode mode,
319 struct clock_event_device *evt, int timer)
321 unsigned int cfg, cmp, now;
325 case CLOCK_EVT_MODE_PERIODIC:
327 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
328 delta >>= evt->shift;
329 now = hpet_readl(HPET_COUNTER);
330 cmp = now + (unsigned int) delta;
331 cfg = hpet_readl(HPET_Tn_CFG(timer));
332 /* Make sure we use edge triggered interrupts */
333 cfg &= ~HPET_TN_LEVEL;
334 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
335 HPET_TN_SETVAL | HPET_TN_32BIT;
336 hpet_writel(cfg, HPET_Tn_CFG(timer));
337 hpet_writel(cmp, HPET_Tn_CMP(timer));
340 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
341 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
342 * bit is automatically cleared after the first write.
343 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
344 * Publication # 24674)
346 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
347 hpet_start_counter();
351 case CLOCK_EVT_MODE_ONESHOT:
352 cfg = hpet_readl(HPET_Tn_CFG(timer));
353 cfg &= ~HPET_TN_PERIODIC;
354 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
355 hpet_writel(cfg, HPET_Tn_CFG(timer));
358 case CLOCK_EVT_MODE_UNUSED:
359 case CLOCK_EVT_MODE_SHUTDOWN:
360 cfg = hpet_readl(HPET_Tn_CFG(timer));
361 cfg &= ~HPET_TN_ENABLE;
362 hpet_writel(cfg, HPET_Tn_CFG(timer));
365 case CLOCK_EVT_MODE_RESUME:
367 hpet_enable_legacy_int();
369 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
370 hpet_setup_msi_irq(hdev->irq);
371 disable_irq(hdev->irq);
372 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
373 enable_irq(hdev->irq);
380 static int hpet_next_event(unsigned long delta,
381 struct clock_event_device *evt, int timer)
385 cnt = hpet_readl(HPET_COUNTER);
387 hpet_writel(cnt, HPET_Tn_CMP(timer));
390 * We need to read back the CMP register on certain HPET
391 * implementations (ATI chipsets) which seem to delay the
392 * transfer of the compare register into the internal compare
393 * logic. With small deltas this might actually be too late as
394 * the counter could already be higher than the compare value
395 * at that point and we would wait for the next hpet interrupt
396 * forever. We found out that reading the CMP register back
397 * forces the transfer so we can rely on the comparison with
398 * the counter register below.
400 * That works fine on those ATI chipsets, but on newer Intel
401 * chipsets (ICH9...) this triggers due to an erratum: Reading
402 * the comparator immediately following a write is returning
405 * We restrict the read back to the affected ATI chipsets (set
406 * by quirks) and also run it with hpet=verbose for debugging
409 if (hpet_readback_cmp || hpet_verbose) {
410 u32 cmp = hpet_readl(HPET_Tn_CMP(timer));
413 printk_once(KERN_WARNING
414 "hpet: compare register read back failed.\n");
417 return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
420 static void hpet_legacy_set_mode(enum clock_event_mode mode,
421 struct clock_event_device *evt)
423 hpet_set_mode(mode, evt, 0);
426 static int hpet_legacy_next_event(unsigned long delta,
427 struct clock_event_device *evt)
429 return hpet_next_event(delta, evt, 0);
435 #ifdef CONFIG_PCI_MSI
437 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
438 static struct hpet_dev *hpet_devs;
440 void hpet_msi_unmask(unsigned int irq)
442 struct hpet_dev *hdev = get_irq_data(irq);
446 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
448 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
451 void hpet_msi_mask(unsigned int irq)
454 struct hpet_dev *hdev = get_irq_data(irq);
457 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
459 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
462 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
464 struct hpet_dev *hdev = get_irq_data(irq);
466 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
467 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
470 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
472 struct hpet_dev *hdev = get_irq_data(irq);
474 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
475 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
479 static void hpet_msi_set_mode(enum clock_event_mode mode,
480 struct clock_event_device *evt)
482 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
483 hpet_set_mode(mode, evt, hdev->num);
486 static int hpet_msi_next_event(unsigned long delta,
487 struct clock_event_device *evt)
489 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
490 return hpet_next_event(delta, evt, hdev->num);
493 static int hpet_setup_msi_irq(unsigned int irq)
495 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
502 static int hpet_assign_irq(struct hpet_dev *dev)
510 set_irq_data(irq, dev);
512 if (hpet_setup_msi_irq(irq))
519 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
521 struct hpet_dev *dev = (struct hpet_dev *)data;
522 struct clock_event_device *hevt = &dev->evt;
524 if (!hevt->event_handler) {
525 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
530 hevt->event_handler(hevt);
534 static int hpet_setup_irq(struct hpet_dev *dev)
537 if (request_irq(dev->irq, hpet_interrupt_handler,
538 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
542 disable_irq(dev->irq);
543 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
544 enable_irq(dev->irq);
546 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
547 dev->name, dev->irq);
552 /* This should be called in specific @cpu */
553 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
555 struct clock_event_device *evt = &hdev->evt;
558 WARN_ON(cpu != smp_processor_id());
559 if (!(hdev->flags & HPET_DEV_VALID))
562 if (hpet_setup_msi_irq(hdev->irq))
566 per_cpu(cpu_hpet_dev, cpu) = hdev;
567 evt->name = hdev->name;
568 hpet_setup_irq(hdev);
569 evt->irq = hdev->irq;
572 evt->features = CLOCK_EVT_FEAT_ONESHOT;
573 if (hdev->flags & HPET_DEV_PERI_CAP)
574 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
576 evt->set_mode = hpet_msi_set_mode;
577 evt->set_next_event = hpet_msi_next_event;
581 * The period is a femto seconds value. We need to calculate the
582 * scaled math multiplication factor for nanosecond to hpet tick
585 hpet_freq = FSEC_PER_SEC;
586 do_div(hpet_freq, hpet_period);
587 evt->mult = div_sc((unsigned long) hpet_freq,
588 NSEC_PER_SEC, evt->shift);
589 /* Calculate the max delta */
590 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
591 /* 5 usec minimum reprogramming delta. */
592 evt->min_delta_ns = 5000;
594 evt->cpumask = cpumask_of(hdev->cpu);
595 clockevents_register_device(evt);
599 /* Reserve at least one timer for userspace (/dev/hpet) */
600 #define RESERVE_TIMERS 1
602 #define RESERVE_TIMERS 0
605 static void hpet_msi_capability_lookup(unsigned int start_timer)
608 unsigned int num_timers;
609 unsigned int num_timers_used = 0;
612 if (hpet_msi_disable)
615 if (boot_cpu_has(X86_FEATURE_ARAT))
617 id = hpet_readl(HPET_ID);
619 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
620 num_timers++; /* Value read out starts from 0 */
623 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
627 hpet_num_timers = num_timers;
629 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
630 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
631 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
633 /* Only consider HPET timer with MSI support */
634 if (!(cfg & HPET_TN_FSB_CAP))
638 if (cfg & HPET_TN_PERIODIC_CAP)
639 hdev->flags |= HPET_DEV_PERI_CAP;
642 sprintf(hdev->name, "hpet%d", i);
643 if (hpet_assign_irq(hdev))
646 hdev->flags |= HPET_DEV_FSB_CAP;
647 hdev->flags |= HPET_DEV_VALID;
649 if (num_timers_used == num_possible_cpus())
653 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
654 num_timers, num_timers_used);
658 static void hpet_reserve_msi_timers(struct hpet_data *hd)
665 for (i = 0; i < hpet_num_timers; i++) {
666 struct hpet_dev *hdev = &hpet_devs[i];
668 if (!(hdev->flags & HPET_DEV_VALID))
671 hd->hd_irq[hdev->num] = hdev->irq;
672 hpet_reserve_timer(hd, hdev->num);
677 static struct hpet_dev *hpet_get_unused_timer(void)
684 for (i = 0; i < hpet_num_timers; i++) {
685 struct hpet_dev *hdev = &hpet_devs[i];
687 if (!(hdev->flags & HPET_DEV_VALID))
689 if (test_and_set_bit(HPET_DEV_USED_BIT,
690 (unsigned long *)&hdev->flags))
697 struct hpet_work_struct {
698 struct delayed_work work;
699 struct completion complete;
702 static void hpet_work(struct work_struct *w)
704 struct hpet_dev *hdev;
705 int cpu = smp_processor_id();
706 struct hpet_work_struct *hpet_work;
708 hpet_work = container_of(w, struct hpet_work_struct, work.work);
710 hdev = hpet_get_unused_timer();
712 init_one_hpet_msi_clockevent(hdev, cpu);
714 complete(&hpet_work->complete);
717 static int hpet_cpuhp_notify(struct notifier_block *n,
718 unsigned long action, void *hcpu)
720 unsigned long cpu = (unsigned long)hcpu;
721 struct hpet_work_struct work;
722 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
724 switch (action & 0xf) {
726 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
727 init_completion(&work.complete);
728 /* FIXME: add schedule_work_on() */
729 schedule_delayed_work_on(cpu, &work.work, 0);
730 wait_for_completion(&work.complete);
731 destroy_timer_on_stack(&work.work.timer);
735 free_irq(hdev->irq, hdev);
736 hdev->flags &= ~HPET_DEV_USED;
737 per_cpu(cpu_hpet_dev, cpu) = NULL;
745 static int hpet_setup_msi_irq(unsigned int irq)
749 static void hpet_msi_capability_lookup(unsigned int start_timer)
755 static void hpet_reserve_msi_timers(struct hpet_data *hd)
761 static int hpet_cpuhp_notify(struct notifier_block *n,
762 unsigned long action, void *hcpu)
770 * Clock source related code
772 static cycle_t read_hpet(struct clocksource *cs)
774 return (cycle_t)hpet_readl(HPET_COUNTER);
778 static cycle_t __vsyscall_fn vread_hpet(void)
780 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
784 static struct clocksource clocksource_hpet = {
789 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
790 .resume = hpet_resume_counter,
796 static int hpet_clocksource_register(void)
802 /* Start the counter */
803 hpet_restart_counter();
805 /* Verify whether hpet counter works */
806 t1 = hpet_readl(HPET_COUNTER);
810 * We don't know the TSC frequency yet, but waiting for
811 * 200000 TSC cycles is safe:
818 } while ((now - start) < 200000UL);
820 if (t1 == hpet_readl(HPET_COUNTER)) {
822 "HPET counter not counting. HPET disabled\n");
827 * The definition of mult is (include/linux/clocksource.h)
828 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
829 * so we first need to convert hpet_period to ns/cyc units:
830 * mult/2^shift = ns/cyc = hpet_period/10^6
831 * mult = (hpet_period * 2^shift)/10^6
832 * mult = (hpet_period << shift)/FSEC_PER_NSEC
835 /* Need to convert hpet_period (fsec/cyc) to cyc/sec:
837 * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc)
838 * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period
840 hpet_freq = FSEC_PER_SEC;
841 do_div(hpet_freq, hpet_period);
842 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
848 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
850 int __init hpet_enable(void)
855 if (!is_hpet_capable())
861 * Read the period and check for a sane value:
863 hpet_period = hpet_readl(HPET_PERIOD);
866 * AMD SB700 based systems with spread spectrum enabled use a
867 * SMM based HPET emulation to provide proper frequency
868 * setting. The SMM code is initialized with the first HPET
869 * register access and takes some time to complete. During
870 * this time the config register reads 0xffffffff. We check
871 * for max. 1000 loops whether the config register reads a non
872 * 0xffffffff value to make sure that HPET is up and running
873 * before we go further. A counting loop is safe, as the HPET
874 * access takes thousands of CPU cycles. On non SB700 based
875 * machines this check is only done once and has no side
878 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
881 "HPET config register value = 0xFFFFFFFF. "
887 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
891 * Read the HPET ID register to retrieve the IRQ routing
892 * information and the number of channels
894 id = hpet_readl(HPET_ID);
897 #ifdef CONFIG_HPET_EMULATE_RTC
899 * The legacy routing mode needs at least two channels, tick timer
900 * and the rtc emulation channel.
902 if (!(id & HPET_ID_NUMBER))
906 if (hpet_clocksource_register())
909 if (id & HPET_ID_LEGSUP) {
910 hpet_legacy_clockevent_register();
916 hpet_clear_mapping();
922 * Needs to be late, as the reserve_timer code calls kalloc !
924 * Not a problem on i386 as hpet_enable is called from late_time_init,
925 * but on x86_64 it is necessary !
927 static __init int hpet_late_init(void)
931 if (boot_hpet_disable)
935 if (!force_hpet_address)
938 hpet_address = force_hpet_address;
942 if (!hpet_virt_address)
945 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
946 hpet_msi_capability_lookup(2);
948 hpet_msi_capability_lookup(0);
950 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
953 if (hpet_msi_disable)
956 if (boot_cpu_has(X86_FEATURE_ARAT))
959 for_each_online_cpu(cpu) {
960 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
963 /* This notifier should be called after workqueue is ready */
964 hotcpu_notifier(hpet_cpuhp_notify, -20);
968 fs_initcall(hpet_late_init);
970 void hpet_disable(void)
972 if (is_hpet_capable() && hpet_virt_address) {
973 unsigned int cfg = hpet_readl(HPET_CFG);
975 if (hpet_legacy_int_enabled) {
976 cfg &= ~HPET_CFG_LEGACY;
977 hpet_legacy_int_enabled = 0;
979 cfg &= ~HPET_CFG_ENABLE;
980 hpet_writel(cfg, HPET_CFG);
984 #ifdef CONFIG_HPET_EMULATE_RTC
986 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
987 * is enabled, we support RTC interrupt functionality in software.
988 * RTC has 3 kinds of interrupts:
989 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
991 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
992 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
993 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
994 * (1) and (2) above are implemented using polling at a frequency of
995 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
996 * overhead. (DEFAULT_RTC_INT_FREQ)
997 * For (3), we use interrupts at 64Hz or user specified periodic
998 * frequency, whichever is higher.
1000 #include <linux/mc146818rtc.h>
1001 #include <linux/rtc.h>
1002 #include <asm/rtc.h>
1004 #define DEFAULT_RTC_INT_FREQ 64
1005 #define DEFAULT_RTC_SHIFT 6
1006 #define RTC_NUM_INTS 1
1008 static unsigned long hpet_rtc_flags;
1009 static int hpet_prev_update_sec;
1010 static struct rtc_time hpet_alarm_time;
1011 static unsigned long hpet_pie_count;
1012 static u32 hpet_t1_cmp;
1013 static u32 hpet_default_delta;
1014 static u32 hpet_pie_delta;
1015 static unsigned long hpet_pie_limit;
1017 static rtc_irq_handler irq_handler;
1020 * Check that the hpet counter c1 is ahead of the c2
1022 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1024 return (s32)(c2 - c1) < 0;
1028 * Registers a IRQ handler.
1030 int hpet_register_irq_handler(rtc_irq_handler handler)
1032 if (!is_hpet_enabled())
1037 irq_handler = handler;
1041 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1044 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1047 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1049 if (!is_hpet_enabled())
1055 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1058 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1059 * is not supported by all HPET implementations for timer 1.
1061 * hpet_rtc_timer_init() is called when the rtc is initialized.
1063 int hpet_rtc_timer_init(void)
1065 unsigned int cfg, cnt, delta;
1066 unsigned long flags;
1068 if (!is_hpet_enabled())
1071 if (!hpet_default_delta) {
1074 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1075 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1076 hpet_default_delta = clc;
1079 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1080 delta = hpet_default_delta;
1082 delta = hpet_pie_delta;
1084 local_irq_save(flags);
1086 cnt = delta + hpet_readl(HPET_COUNTER);
1087 hpet_writel(cnt, HPET_T1_CMP);
1090 cfg = hpet_readl(HPET_T1_CFG);
1091 cfg &= ~HPET_TN_PERIODIC;
1092 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1093 hpet_writel(cfg, HPET_T1_CFG);
1095 local_irq_restore(flags);
1099 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1102 * The functions below are called from rtc driver.
1103 * Return 0 if HPET is not being used.
1104 * Otherwise do the necessary changes and return 1.
1106 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1108 if (!is_hpet_enabled())
1111 hpet_rtc_flags &= ~bit_mask;
1114 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1116 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1118 unsigned long oldbits = hpet_rtc_flags;
1120 if (!is_hpet_enabled())
1123 hpet_rtc_flags |= bit_mask;
1125 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1126 hpet_prev_update_sec = -1;
1129 hpet_rtc_timer_init();
1133 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1135 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1138 if (!is_hpet_enabled())
1141 hpet_alarm_time.tm_hour = hrs;
1142 hpet_alarm_time.tm_min = min;
1143 hpet_alarm_time.tm_sec = sec;
1147 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1149 int hpet_set_periodic_freq(unsigned long freq)
1153 if (!is_hpet_enabled())
1156 if (freq <= DEFAULT_RTC_INT_FREQ)
1157 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1159 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1161 clc >>= hpet_clockevent.shift;
1162 hpet_pie_delta = clc;
1167 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1169 int hpet_rtc_dropped_irq(void)
1171 return is_hpet_enabled();
1173 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1175 static void hpet_rtc_timer_reinit(void)
1177 unsigned int cfg, delta;
1180 if (unlikely(!hpet_rtc_flags)) {
1181 cfg = hpet_readl(HPET_T1_CFG);
1182 cfg &= ~HPET_TN_ENABLE;
1183 hpet_writel(cfg, HPET_T1_CFG);
1187 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1188 delta = hpet_default_delta;
1190 delta = hpet_pie_delta;
1193 * Increment the comparator value until we are ahead of the
1197 hpet_t1_cmp += delta;
1198 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1200 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1203 if (hpet_rtc_flags & RTC_PIE)
1204 hpet_pie_count += lost_ints;
1205 if (printk_ratelimit())
1206 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1211 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1213 struct rtc_time curr_time;
1214 unsigned long rtc_int_flag = 0;
1216 hpet_rtc_timer_reinit();
1217 memset(&curr_time, 0, sizeof(struct rtc_time));
1219 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1220 get_rtc_time(&curr_time);
1222 if (hpet_rtc_flags & RTC_UIE &&
1223 curr_time.tm_sec != hpet_prev_update_sec) {
1224 if (hpet_prev_update_sec >= 0)
1225 rtc_int_flag = RTC_UF;
1226 hpet_prev_update_sec = curr_time.tm_sec;
1229 if (hpet_rtc_flags & RTC_PIE &&
1230 ++hpet_pie_count >= hpet_pie_limit) {
1231 rtc_int_flag |= RTC_PF;
1235 if (hpet_rtc_flags & RTC_AIE &&
1236 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1237 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1238 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1239 rtc_int_flag |= RTC_AF;
1242 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1244 irq_handler(rtc_int_flag, dev_id);
1248 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);