1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/interrupt.h>
4 #include <linux/export.h>
5 #include <linux/sysdev.h>
6 #include <linux/delay.h>
7 #include <linux/errno.h>
8 #include <linux/i8253.h>
9 #include <linux/slab.h>
10 #include <linux/hpet.h>
11 #include <linux/init.h>
12 #include <linux/cpu.h>
16 #include <asm/fixmap.h>
20 #define HPET_MASK CLOCKSOURCE_MASK(32)
24 #define FSEC_PER_NSEC 1000000L
26 #define HPET_DEV_USED_BIT 2
27 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
28 #define HPET_DEV_VALID 0x8
29 #define HPET_DEV_FSB_CAP 0x1000
30 #define HPET_DEV_PERI_CAP 0x2000
32 #define HPET_MIN_CYCLES 128
33 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
36 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 unsigned long hpet_address;
39 u8 hpet_blockid; /* OS timer block num */
43 static unsigned long hpet_num_timers;
45 static void __iomem *hpet_virt_address;
48 struct clock_event_device evt;
56 inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
58 return container_of(evtdev, struct hpet_dev, evt);
61 inline unsigned int hpet_readl(unsigned int a)
63 return readl(hpet_virt_address + a);
66 static inline void hpet_writel(unsigned int d, unsigned int a)
68 writel(d, hpet_virt_address + a);
72 #include <asm/pgtable.h>
75 static inline void hpet_set_mapping(void)
77 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
79 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
83 static inline void hpet_clear_mapping(void)
85 iounmap(hpet_virt_address);
86 hpet_virt_address = NULL;
90 * HPET command line enable / disable
92 static int boot_hpet_disable;
94 static int hpet_verbose;
96 static int __init hpet_setup(char *str)
99 if (!strncmp("disable", str, 7))
100 boot_hpet_disable = 1;
101 if (!strncmp("force", str, 5))
103 if (!strncmp("verbose", str, 7))
108 __setup("hpet=", hpet_setup);
110 static int __init disable_hpet(char *str)
112 boot_hpet_disable = 1;
115 __setup("nohpet", disable_hpet);
117 static inline int is_hpet_capable(void)
119 return !boot_hpet_disable && hpet_address;
123 * HPET timer interrupt enable / disable
125 static int hpet_legacy_int_enabled;
128 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
130 int is_hpet_enabled(void)
132 return is_hpet_capable() && hpet_legacy_int_enabled;
134 EXPORT_SYMBOL_GPL(is_hpet_enabled);
136 static void _hpet_print_config(const char *function, int line)
139 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
140 l = hpet_readl(HPET_ID);
141 h = hpet_readl(HPET_PERIOD);
142 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
143 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
144 l = hpet_readl(HPET_CFG);
145 h = hpet_readl(HPET_STATUS);
146 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
147 l = hpet_readl(HPET_COUNTER);
148 h = hpet_readl(HPET_COUNTER+4);
149 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
151 for (i = 0; i < timers; i++) {
152 l = hpet_readl(HPET_Tn_CFG(i));
153 h = hpet_readl(HPET_Tn_CFG(i)+4);
154 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
156 l = hpet_readl(HPET_Tn_CMP(i));
157 h = hpet_readl(HPET_Tn_CMP(i)+4);
158 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
160 l = hpet_readl(HPET_Tn_ROUTE(i));
161 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
162 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
167 #define hpet_print_config() \
170 _hpet_print_config(__FUNCTION__, __LINE__); \
174 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
175 * timer 0 and timer 1 in case of RTC emulation.
179 static void hpet_reserve_msi_timers(struct hpet_data *hd);
181 static void hpet_reserve_platform_timers(unsigned int id)
183 struct hpet __iomem *hpet = hpet_virt_address;
184 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
185 unsigned int nrtimers, i;
188 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
190 memset(&hd, 0, sizeof(hd));
191 hd.hd_phys_address = hpet_address;
192 hd.hd_address = hpet;
193 hd.hd_nirqs = nrtimers;
194 hpet_reserve_timer(&hd, 0);
196 #ifdef CONFIG_HPET_EMULATE_RTC
197 hpet_reserve_timer(&hd, 1);
201 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
202 * is wrong for i8259!) not the output IRQ. Many BIOS writers
203 * don't bother configuring *any* comparator interrupts.
205 hd.hd_irq[0] = HPET_LEGACY_8254;
206 hd.hd_irq[1] = HPET_LEGACY_RTC;
208 for (i = 2; i < nrtimers; timer++, i++) {
209 hd.hd_irq[i] = (readl(&timer->hpet_config) &
210 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
213 hpet_reserve_msi_timers(&hd);
219 static void hpet_reserve_platform_timers(unsigned int id) { }
225 static unsigned long hpet_freq;
227 static void hpet_legacy_set_mode(enum clock_event_mode mode,
228 struct clock_event_device *evt);
229 static int hpet_legacy_next_event(unsigned long delta,
230 struct clock_event_device *evt);
233 * The hpet clock event device
235 static struct clock_event_device hpet_clockevent = {
237 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
238 .set_mode = hpet_legacy_set_mode,
239 .set_next_event = hpet_legacy_next_event,
244 static void hpet_stop_counter(void)
246 unsigned long cfg = hpet_readl(HPET_CFG);
247 cfg &= ~HPET_CFG_ENABLE;
248 hpet_writel(cfg, HPET_CFG);
251 static void hpet_reset_counter(void)
253 hpet_writel(0, HPET_COUNTER);
254 hpet_writel(0, HPET_COUNTER + 4);
257 static void hpet_start_counter(void)
259 unsigned int cfg = hpet_readl(HPET_CFG);
260 cfg |= HPET_CFG_ENABLE;
261 hpet_writel(cfg, HPET_CFG);
264 static void hpet_restart_counter(void)
267 hpet_reset_counter();
268 hpet_start_counter();
271 static void hpet_resume_device(void)
276 static void hpet_resume_counter(struct clocksource *cs)
278 hpet_resume_device();
279 hpet_restart_counter();
282 static void hpet_enable_legacy_int(void)
284 unsigned int cfg = hpet_readl(HPET_CFG);
286 cfg |= HPET_CFG_LEGACY;
287 hpet_writel(cfg, HPET_CFG);
288 hpet_legacy_int_enabled = 1;
291 static void hpet_legacy_clockevent_register(void)
293 /* Start HPET legacy interrupts */
294 hpet_enable_legacy_int();
297 * Start hpet with the boot cpu mask and make it
298 * global after the IO_APIC has been initialized.
300 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
301 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
302 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
303 global_clock_event = &hpet_clockevent;
304 printk(KERN_DEBUG "hpet clockevent registered\n");
307 static int hpet_setup_msi_irq(unsigned int irq);
309 static void hpet_set_mode(enum clock_event_mode mode,
310 struct clock_event_device *evt, int timer)
312 unsigned int cfg, cmp, now;
316 case CLOCK_EVT_MODE_PERIODIC:
318 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
319 delta >>= evt->shift;
320 now = hpet_readl(HPET_COUNTER);
321 cmp = now + (unsigned int) delta;
322 cfg = hpet_readl(HPET_Tn_CFG(timer));
323 /* Make sure we use edge triggered interrupts */
324 cfg &= ~HPET_TN_LEVEL;
325 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
326 HPET_TN_SETVAL | HPET_TN_32BIT;
327 hpet_writel(cfg, HPET_Tn_CFG(timer));
328 hpet_writel(cmp, HPET_Tn_CMP(timer));
331 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
332 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
333 * bit is automatically cleared after the first write.
334 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
335 * Publication # 24674)
337 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
338 hpet_start_counter();
342 case CLOCK_EVT_MODE_ONESHOT:
343 cfg = hpet_readl(HPET_Tn_CFG(timer));
344 cfg &= ~HPET_TN_PERIODIC;
345 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
346 hpet_writel(cfg, HPET_Tn_CFG(timer));
349 case CLOCK_EVT_MODE_UNUSED:
350 case CLOCK_EVT_MODE_SHUTDOWN:
351 cfg = hpet_readl(HPET_Tn_CFG(timer));
352 cfg &= ~HPET_TN_ENABLE;
353 hpet_writel(cfg, HPET_Tn_CFG(timer));
356 case CLOCK_EVT_MODE_RESUME:
358 hpet_enable_legacy_int();
360 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
361 hpet_setup_msi_irq(hdev->irq);
362 disable_irq(hdev->irq);
363 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
364 enable_irq(hdev->irq);
371 static int hpet_next_event(unsigned long delta,
372 struct clock_event_device *evt, int timer)
377 cnt = hpet_readl(HPET_COUNTER);
379 hpet_writel(cnt, HPET_Tn_CMP(timer));
382 * HPETs are a complete disaster. The compare register is
383 * based on a equal comparison and neither provides a less
384 * than or equal functionality (which would require to take
385 * the wraparound into account) nor a simple count down event
386 * mode. Further the write to the comparator register is
387 * delayed internally up to two HPET clock cycles in certain
388 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
389 * longer delays. We worked around that by reading back the
390 * compare register, but that required another workaround for
391 * ICH9,10 chips where the first readout after write can
392 * return the old stale value. We already had a minimum
393 * programming delta of 5us enforced, but a NMI or SMI hitting
394 * between the counter readout and the comparator write can
395 * move us behind that point easily. Now instead of reading
396 * the compare register back several times, we make the ETIME
397 * decision based on the following: Return ETIME if the
398 * counter value after the write is less than HPET_MIN_CYCLES
399 * away from the event or if the counter is already ahead of
400 * the event. The minimum programming delta for the generic
401 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
403 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
405 return res < HPET_MIN_CYCLES ? -ETIME : 0;
408 static void hpet_legacy_set_mode(enum clock_event_mode mode,
409 struct clock_event_device *evt)
411 hpet_set_mode(mode, evt, 0);
414 static int hpet_legacy_next_event(unsigned long delta,
415 struct clock_event_device *evt)
417 return hpet_next_event(delta, evt, 0);
423 #ifdef CONFIG_PCI_MSI
425 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
426 static struct hpet_dev *hpet_devs;
428 void hpet_msi_unmask(struct irq_data *data)
430 struct hpet_dev *hdev = data->handler_data;
434 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
436 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
439 void hpet_msi_mask(struct irq_data *data)
441 struct hpet_dev *hdev = data->handler_data;
445 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
447 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
450 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
452 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
453 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
456 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
458 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
459 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
463 static void hpet_msi_set_mode(enum clock_event_mode mode,
464 struct clock_event_device *evt)
466 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
467 hpet_set_mode(mode, evt, hdev->num);
470 static int hpet_msi_next_event(unsigned long delta,
471 struct clock_event_device *evt)
473 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
474 return hpet_next_event(delta, evt, hdev->num);
477 static int hpet_setup_msi_irq(unsigned int irq)
479 if (arch_setup_hpet_msi(irq, hpet_blockid)) {
486 static int hpet_assign_irq(struct hpet_dev *dev)
490 irq = create_irq_nr(0, -1);
494 irq_set_handler_data(irq, dev);
496 if (hpet_setup_msi_irq(irq))
503 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
505 struct hpet_dev *dev = (struct hpet_dev *)data;
506 struct clock_event_device *hevt = &dev->evt;
508 if (!hevt->event_handler) {
509 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
514 hevt->event_handler(hevt);
518 static int hpet_setup_irq(struct hpet_dev *dev)
521 if (request_irq(dev->irq, hpet_interrupt_handler,
522 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
526 disable_irq(dev->irq);
527 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
528 enable_irq(dev->irq);
530 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
531 dev->name, dev->irq);
536 /* This should be called in specific @cpu */
537 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
539 struct clock_event_device *evt = &hdev->evt;
541 WARN_ON(cpu != smp_processor_id());
542 if (!(hdev->flags & HPET_DEV_VALID))
545 if (hpet_setup_msi_irq(hdev->irq))
549 per_cpu(cpu_hpet_dev, cpu) = hdev;
550 evt->name = hdev->name;
551 hpet_setup_irq(hdev);
552 evt->irq = hdev->irq;
555 evt->features = CLOCK_EVT_FEAT_ONESHOT;
556 if (hdev->flags & HPET_DEV_PERI_CAP)
557 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
559 evt->set_mode = hpet_msi_set_mode;
560 evt->set_next_event = hpet_msi_next_event;
561 evt->cpumask = cpumask_of(hdev->cpu);
563 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
568 /* Reserve at least one timer for userspace (/dev/hpet) */
569 #define RESERVE_TIMERS 1
571 #define RESERVE_TIMERS 0
574 static void hpet_msi_capability_lookup(unsigned int start_timer)
577 unsigned int num_timers;
578 unsigned int num_timers_used = 0;
581 if (hpet_msi_disable)
584 if (boot_cpu_has(X86_FEATURE_ARAT))
586 id = hpet_readl(HPET_ID);
588 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
589 num_timers++; /* Value read out starts from 0 */
592 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
596 hpet_num_timers = num_timers;
598 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
599 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
600 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
602 /* Only consider HPET timer with MSI support */
603 if (!(cfg & HPET_TN_FSB_CAP))
607 if (cfg & HPET_TN_PERIODIC_CAP)
608 hdev->flags |= HPET_DEV_PERI_CAP;
611 sprintf(hdev->name, "hpet%d", i);
612 if (hpet_assign_irq(hdev))
615 hdev->flags |= HPET_DEV_FSB_CAP;
616 hdev->flags |= HPET_DEV_VALID;
618 if (num_timers_used == num_possible_cpus())
622 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
623 num_timers, num_timers_used);
627 static void hpet_reserve_msi_timers(struct hpet_data *hd)
634 for (i = 0; i < hpet_num_timers; i++) {
635 struct hpet_dev *hdev = &hpet_devs[i];
637 if (!(hdev->flags & HPET_DEV_VALID))
640 hd->hd_irq[hdev->num] = hdev->irq;
641 hpet_reserve_timer(hd, hdev->num);
646 static struct hpet_dev *hpet_get_unused_timer(void)
653 for (i = 0; i < hpet_num_timers; i++) {
654 struct hpet_dev *hdev = &hpet_devs[i];
656 if (!(hdev->flags & HPET_DEV_VALID))
658 if (test_and_set_bit(HPET_DEV_USED_BIT,
659 (unsigned long *)&hdev->flags))
666 struct hpet_work_struct {
667 struct delayed_work work;
668 struct completion complete;
671 static void hpet_work(struct work_struct *w)
673 struct hpet_dev *hdev;
674 int cpu = smp_processor_id();
675 struct hpet_work_struct *hpet_work;
677 hpet_work = container_of(w, struct hpet_work_struct, work.work);
679 hdev = hpet_get_unused_timer();
681 init_one_hpet_msi_clockevent(hdev, cpu);
683 complete(&hpet_work->complete);
686 static int hpet_cpuhp_notify(struct notifier_block *n,
687 unsigned long action, void *hcpu)
689 unsigned long cpu = (unsigned long)hcpu;
690 struct hpet_work_struct work;
691 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
693 switch (action & 0xf) {
695 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
696 init_completion(&work.complete);
697 /* FIXME: add schedule_work_on() */
698 schedule_delayed_work_on(cpu, &work.work, 0);
699 wait_for_completion(&work.complete);
700 destroy_timer_on_stack(&work.work.timer);
704 free_irq(hdev->irq, hdev);
705 hdev->flags &= ~HPET_DEV_USED;
706 per_cpu(cpu_hpet_dev, cpu) = NULL;
714 static int hpet_setup_msi_irq(unsigned int irq)
718 static void hpet_msi_capability_lookup(unsigned int start_timer)
724 static void hpet_reserve_msi_timers(struct hpet_data *hd)
730 static int hpet_cpuhp_notify(struct notifier_block *n,
731 unsigned long action, void *hcpu)
739 * Clock source related code
741 static cycle_t read_hpet(struct clocksource *cs)
743 return (cycle_t)hpet_readl(HPET_COUNTER);
746 static struct clocksource clocksource_hpet = {
751 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
752 .resume = hpet_resume_counter,
754 .archdata = { .vclock_mode = VCLOCK_HPET },
758 static int hpet_clocksource_register(void)
763 /* Start the counter */
764 hpet_restart_counter();
766 /* Verify whether hpet counter works */
767 t1 = hpet_readl(HPET_COUNTER);
771 * We don't know the TSC frequency yet, but waiting for
772 * 200000 TSC cycles is safe:
779 } while ((now - start) < 200000UL);
781 if (t1 == hpet_readl(HPET_COUNTER)) {
783 "HPET counter not counting. HPET disabled\n");
787 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
792 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
794 int __init hpet_enable(void)
796 unsigned long hpet_period;
801 if (!is_hpet_capable())
807 * Read the period and check for a sane value:
809 hpet_period = hpet_readl(HPET_PERIOD);
812 * AMD SB700 based systems with spread spectrum enabled use a
813 * SMM based HPET emulation to provide proper frequency
814 * setting. The SMM code is initialized with the first HPET
815 * register access and takes some time to complete. During
816 * this time the config register reads 0xffffffff. We check
817 * for max. 1000 loops whether the config register reads a non
818 * 0xffffffff value to make sure that HPET is up and running
819 * before we go further. A counting loop is safe, as the HPET
820 * access takes thousands of CPU cycles. On non SB700 based
821 * machines this check is only done once and has no side
824 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
827 "HPET config register value = 0xFFFFFFFF. "
833 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
837 * The period is a femto seconds value. Convert it to a
841 do_div(freq, hpet_period);
845 * Read the HPET ID register to retrieve the IRQ routing
846 * information and the number of channels
848 id = hpet_readl(HPET_ID);
851 #ifdef CONFIG_HPET_EMULATE_RTC
853 * The legacy routing mode needs at least two channels, tick timer
854 * and the rtc emulation channel.
856 if (!(id & HPET_ID_NUMBER))
860 if (hpet_clocksource_register())
863 if (id & HPET_ID_LEGSUP) {
864 hpet_legacy_clockevent_register();
870 hpet_clear_mapping();
876 * Needs to be late, as the reserve_timer code calls kalloc !
878 * Not a problem on i386 as hpet_enable is called from late_time_init,
879 * but on x86_64 it is necessary !
881 static __init int hpet_late_init(void)
885 if (boot_hpet_disable)
889 if (!force_hpet_address)
892 hpet_address = force_hpet_address;
896 if (!hpet_virt_address)
899 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
900 hpet_msi_capability_lookup(2);
902 hpet_msi_capability_lookup(0);
904 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
907 if (hpet_msi_disable)
910 if (boot_cpu_has(X86_FEATURE_ARAT))
913 for_each_online_cpu(cpu) {
914 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
917 /* This notifier should be called after workqueue is ready */
918 hotcpu_notifier(hpet_cpuhp_notify, -20);
922 fs_initcall(hpet_late_init);
924 void hpet_disable(void)
926 if (is_hpet_capable() && hpet_virt_address) {
927 unsigned int cfg = hpet_readl(HPET_CFG);
929 if (hpet_legacy_int_enabled) {
930 cfg &= ~HPET_CFG_LEGACY;
931 hpet_legacy_int_enabled = 0;
933 cfg &= ~HPET_CFG_ENABLE;
934 hpet_writel(cfg, HPET_CFG);
938 #ifdef CONFIG_HPET_EMULATE_RTC
940 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
941 * is enabled, we support RTC interrupt functionality in software.
942 * RTC has 3 kinds of interrupts:
943 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
945 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
946 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
947 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
948 * (1) and (2) above are implemented using polling at a frequency of
949 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
950 * overhead. (DEFAULT_RTC_INT_FREQ)
951 * For (3), we use interrupts at 64Hz or user specified periodic
952 * frequency, whichever is higher.
954 #include <linux/mc146818rtc.h>
955 #include <linux/rtc.h>
958 #define DEFAULT_RTC_INT_FREQ 64
959 #define DEFAULT_RTC_SHIFT 6
960 #define RTC_NUM_INTS 1
962 static unsigned long hpet_rtc_flags;
963 static int hpet_prev_update_sec;
964 static struct rtc_time hpet_alarm_time;
965 static unsigned long hpet_pie_count;
966 static u32 hpet_t1_cmp;
967 static u32 hpet_default_delta;
968 static u32 hpet_pie_delta;
969 static unsigned long hpet_pie_limit;
971 static rtc_irq_handler irq_handler;
974 * Check that the hpet counter c1 is ahead of the c2
976 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
978 return (s32)(c2 - c1) < 0;
982 * Registers a IRQ handler.
984 int hpet_register_irq_handler(rtc_irq_handler handler)
986 if (!is_hpet_enabled())
991 irq_handler = handler;
995 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
998 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1001 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1003 if (!is_hpet_enabled())
1009 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1012 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1013 * is not supported by all HPET implementations for timer 1.
1015 * hpet_rtc_timer_init() is called when the rtc is initialized.
1017 int hpet_rtc_timer_init(void)
1019 unsigned int cfg, cnt, delta;
1020 unsigned long flags;
1022 if (!is_hpet_enabled())
1025 if (!hpet_default_delta) {
1028 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1029 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1030 hpet_default_delta = clc;
1033 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1034 delta = hpet_default_delta;
1036 delta = hpet_pie_delta;
1038 local_irq_save(flags);
1040 cnt = delta + hpet_readl(HPET_COUNTER);
1041 hpet_writel(cnt, HPET_T1_CMP);
1044 cfg = hpet_readl(HPET_T1_CFG);
1045 cfg &= ~HPET_TN_PERIODIC;
1046 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1047 hpet_writel(cfg, HPET_T1_CFG);
1049 local_irq_restore(flags);
1053 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1055 static void hpet_disable_rtc_channel(void)
1058 cfg = hpet_readl(HPET_T1_CFG);
1059 cfg &= ~HPET_TN_ENABLE;
1060 hpet_writel(cfg, HPET_T1_CFG);
1064 * The functions below are called from rtc driver.
1065 * Return 0 if HPET is not being used.
1066 * Otherwise do the necessary changes and return 1.
1068 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1070 if (!is_hpet_enabled())
1073 hpet_rtc_flags &= ~bit_mask;
1074 if (unlikely(!hpet_rtc_flags))
1075 hpet_disable_rtc_channel();
1079 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1081 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1083 unsigned long oldbits = hpet_rtc_flags;
1085 if (!is_hpet_enabled())
1088 hpet_rtc_flags |= bit_mask;
1090 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1091 hpet_prev_update_sec = -1;
1094 hpet_rtc_timer_init();
1098 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1100 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1103 if (!is_hpet_enabled())
1106 hpet_alarm_time.tm_hour = hrs;
1107 hpet_alarm_time.tm_min = min;
1108 hpet_alarm_time.tm_sec = sec;
1112 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1114 int hpet_set_periodic_freq(unsigned long freq)
1118 if (!is_hpet_enabled())
1121 if (freq <= DEFAULT_RTC_INT_FREQ)
1122 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1124 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1126 clc >>= hpet_clockevent.shift;
1127 hpet_pie_delta = clc;
1132 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1134 int hpet_rtc_dropped_irq(void)
1136 return is_hpet_enabled();
1138 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1140 static void hpet_rtc_timer_reinit(void)
1145 if (unlikely(!hpet_rtc_flags))
1146 hpet_disable_rtc_channel();
1148 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1149 delta = hpet_default_delta;
1151 delta = hpet_pie_delta;
1154 * Increment the comparator value until we are ahead of the
1158 hpet_t1_cmp += delta;
1159 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1161 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1164 if (hpet_rtc_flags & RTC_PIE)
1165 hpet_pie_count += lost_ints;
1166 if (printk_ratelimit())
1167 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1172 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1174 struct rtc_time curr_time;
1175 unsigned long rtc_int_flag = 0;
1177 hpet_rtc_timer_reinit();
1178 memset(&curr_time, 0, sizeof(struct rtc_time));
1180 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1181 get_rtc_time(&curr_time);
1183 if (hpet_rtc_flags & RTC_UIE &&
1184 curr_time.tm_sec != hpet_prev_update_sec) {
1185 if (hpet_prev_update_sec >= 0)
1186 rtc_int_flag = RTC_UF;
1187 hpet_prev_update_sec = curr_time.tm_sec;
1190 if (hpet_rtc_flags & RTC_PIE &&
1191 ++hpet_pie_count >= hpet_pie_limit) {
1192 rtc_int_flag |= RTC_PF;
1196 if (hpet_rtc_flags & RTC_AIE &&
1197 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1198 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1199 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1200 rtc_int_flag |= RTC_AF;
1203 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1205 irq_handler(rtc_int_flag, dev_id);
1209 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);