1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/slab.h>
9 #include <linux/random.h>
10 #include <linux/init.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/sysdev.h>
13 #include <linux/bitops.h>
16 #include <asm/atomic.h>
17 #include <asm/system.h>
19 #include <asm/hw_irq.h>
20 #include <asm/pgtable.h>
21 #include <asm/delay.h>
24 #include <asm/i8259.h>
27 * Common place to define all x86 IRQ vectors
29 * This builds up the IRQ handler stubs using some ugly macros in irq.h
31 * These macros create the low-level assembly IRQ routines that save
32 * register context and call do_IRQ(). do_IRQ() then does all the
33 * operations that are needed to keep the AT (or SMP IOAPIC)
34 * interrupt-controller happy.
37 #define IRQ_NAME2(nr) nr##_interrupt(void)
38 #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
41 * SMP has a few special interrupts for IPI messages
44 #define BUILD_IRQ(nr) \
45 asmlinkage void IRQ_NAME(nr); \
47 "IRQ" #nr "_interrupt:\n\t" \
48 "push $~(" #nr ") ; " \
49 "jmp common_interrupt");
54 #define BUILD_16_IRQS(x) \
55 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
56 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
57 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
58 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
61 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
62 * (these are usually mapped to vectors 0x30-0x3f)
66 * The IO-APIC gives us many more interrupt sources. Most of these
67 * are unused but an SMP system is supposed to have enough memory ...
68 * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
69 * across the spectrum, so we really want to be prepared to get all
70 * of these. Plus, more powerful systems might have more than 64
73 * (these are usually mapped into the 0x30-0xff vector range)
75 BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
76 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
77 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
78 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
87 #define IRQLIST_16(x) \
88 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
89 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
90 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
91 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
93 /* for the irq vectors */
94 static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
95 IRQLIST_16(0x2), IRQLIST_16(0x3),
96 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
97 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
98 IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
105 * This is the 'legacy' 8259A Programmable Interrupt Controller,
106 * present in the majority of PC/AT boxes.
107 * plus some generic x86 specific things if generic specifics makes
109 * this file should become arch/i386/kernel/irq.c when the old irq.c
110 * moves to arch independent land
113 static int i8259A_auto_eoi;
114 DEFINE_SPINLOCK(i8259A_lock);
115 static void mask_and_ack_8259A(unsigned int);
117 static struct irq_chip i8259A_chip = {
119 .mask = disable_8259A_irq,
120 .disable = disable_8259A_irq,
121 .unmask = enable_8259A_irq,
122 .mask_ack = mask_and_ack_8259A,
126 * 8259A PIC functions to handle ISA devices:
130 * This contains the irq mask for both 8259A irq controllers,
132 unsigned int cached_irq_mask = 0xffff;
135 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
136 * boards the timer interrupt is not really connected to any IO-APIC pin,
137 * it's fed to the master 8259A's IR0 line only.
139 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
140 * this 'mixed mode' IRQ handling costs nothing because it's only used
143 unsigned long io_apic_irqs;
145 void disable_8259A_irq(unsigned int irq)
147 unsigned int mask = 1 << irq;
150 spin_lock_irqsave(&i8259A_lock, flags);
151 cached_irq_mask |= mask;
153 outb(cached_slave_mask, PIC_SLAVE_IMR);
155 outb(cached_master_mask, PIC_MASTER_IMR);
156 spin_unlock_irqrestore(&i8259A_lock, flags);
159 void enable_8259A_irq(unsigned int irq)
161 unsigned int mask = ~(1 << irq);
164 spin_lock_irqsave(&i8259A_lock, flags);
165 cached_irq_mask &= mask;
167 outb(cached_slave_mask, PIC_SLAVE_IMR);
169 outb(cached_master_mask, PIC_MASTER_IMR);
170 spin_unlock_irqrestore(&i8259A_lock, flags);
173 int i8259A_irq_pending(unsigned int irq)
175 unsigned int mask = 1<<irq;
179 spin_lock_irqsave(&i8259A_lock, flags);
181 ret = inb(PIC_MASTER_CMD) & mask;
183 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
184 spin_unlock_irqrestore(&i8259A_lock, flags);
189 void make_8259A_irq(unsigned int irq)
191 disable_irq_nosync(irq);
192 io_apic_irqs &= ~(1<<irq);
193 set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
199 * This function assumes to be called rarely. Switching between
200 * 8259A registers is slow.
201 * This has to be protected by the irq controller spinlock
202 * before being called.
204 static inline int i8259A_irq_real(unsigned int irq)
207 int irqmask = 1<<irq;
210 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
211 value = inb(PIC_MASTER_CMD) & irqmask;
212 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
215 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
216 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
217 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
222 * Careful! The 8259A is a fragile beast, it pretty
223 * much _has_ to be done exactly like this (mask it
224 * first, _then_ send the EOI, and the order of EOI
225 * to the two 8259s is important!
227 static void mask_and_ack_8259A(unsigned int irq)
229 unsigned int irqmask = 1 << irq;
232 spin_lock_irqsave(&i8259A_lock, flags);
234 * Lightweight spurious IRQ detection. We do not want
235 * to overdo spurious IRQ handling - it's usually a sign
236 * of hardware problems, so we only do the checks we can
237 * do without slowing down good hardware unnecessarily.
239 * Note that IRQ7 and IRQ15 (the two spurious IRQs
240 * usually resulting from the 8259A-1|2 PICs) occur
241 * even if the IRQ is masked in the 8259A. Thus we
242 * can check spurious 8259A IRQs without doing the
243 * quite slow i8259A_irq_real() call for every IRQ.
244 * This does not cover 100% of spurious interrupts,
245 * but should be enough to warn the user that there
246 * is something bad going on ...
248 if (cached_irq_mask & irqmask)
249 goto spurious_8259A_irq;
250 cached_irq_mask |= irqmask;
254 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
255 outb(cached_slave_mask, PIC_SLAVE_IMR);
256 /* 'Specific EOI' to slave */
257 outb(0x60+(irq&7),PIC_SLAVE_CMD);
258 /* 'Specific EOI' to master-IRQ2 */
259 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD);
261 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
262 outb(cached_master_mask, PIC_MASTER_IMR);
263 /* 'Specific EOI' to master */
264 outb(0x60+irq,PIC_MASTER_CMD);
266 spin_unlock_irqrestore(&i8259A_lock, flags);
271 * this is the slow path - should happen rarely.
273 if (i8259A_irq_real(irq))
275 * oops, the IRQ _is_ in service according to the
276 * 8259A - not spurious, go handle it.
278 goto handle_real_irq;
281 static int spurious_irq_mask;
283 * At this point we can be sure the IRQ is spurious,
284 * lets ACK and report it. [once per IRQ]
286 if (!(spurious_irq_mask & irqmask)) {
288 "spurious 8259A interrupt: IRQ%d.\n", irq);
289 spurious_irq_mask |= irqmask;
291 atomic_inc(&irq_err_count);
293 * Theoretically we do not have to handle this IRQ,
294 * but in Linux this does not cause problems and is
297 goto handle_real_irq;
301 static char irq_trigger[2];
303 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
305 static void restore_ELCR(char *trigger)
307 outb(trigger[0], 0x4d0);
308 outb(trigger[1], 0x4d1);
311 static void save_ELCR(char *trigger)
313 /* IRQ 0,1,2,8,13 are marked as reserved */
314 trigger[0] = inb(0x4d0) & 0xF8;
315 trigger[1] = inb(0x4d1) & 0xDE;
318 static int i8259A_resume(struct sys_device *dev)
320 init_8259A(i8259A_auto_eoi);
321 restore_ELCR(irq_trigger);
325 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
327 save_ELCR(irq_trigger);
331 static int i8259A_shutdown(struct sys_device *dev)
333 /* Put the i8259A into a quiescent state that
334 * the kernel initialization code can get it
337 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
338 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
342 static struct sysdev_class i8259_sysdev_class = {
344 .suspend = i8259A_suspend,
345 .resume = i8259A_resume,
346 .shutdown = i8259A_shutdown,
349 static struct sys_device device_i8259A = {
351 .cls = &i8259_sysdev_class,
354 static int __init i8259A_init_sysfs(void)
356 int error = sysdev_class_register(&i8259_sysdev_class);
358 error = sysdev_register(&device_i8259A);
362 device_initcall(i8259A_init_sysfs);
364 void init_8259A(int auto_eoi)
368 i8259A_auto_eoi = auto_eoi;
370 spin_lock_irqsave(&i8259A_lock, flags);
372 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
373 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
376 * outb_pic - this has to work on a wide range of PC hardware.
378 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
379 /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
380 outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
381 /* 8259A-1 (the master) has a slave on IR2 */
382 outb_pic(0x04, PIC_MASTER_IMR);
383 if (auto_eoi) /* master does Auto EOI */
384 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
385 else /* master expects normal EOI */
386 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
388 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
389 /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
390 outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
391 /* 8259A-2 is a slave on master's IR2 */
392 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
393 /* (slave's support for AEOI in flat mode is to be investigated) */
394 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
398 * In AEOI mode we just have to mask the interrupt
401 i8259A_chip.mask_ack = disable_8259A_irq;
403 i8259A_chip.mask_ack = mask_and_ack_8259A;
405 udelay(100); /* wait for 8259A to initialize */
407 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
408 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
410 spin_unlock_irqrestore(&i8259A_lock, flags);
417 * IRQ2 is cascade interrupt to second interrupt controller
420 static struct irqaction irq2 = {
421 .handler = no_action,
422 .mask = CPU_MASK_NONE,
425 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
426 [0 ... IRQ0_VECTOR - 1] = -1,
443 [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
446 void __init init_ISA_irqs (void)
453 for (i = 0; i < NR_IRQS; i++) {
454 irq_desc[i].status = IRQ_DISABLED;
455 irq_desc[i].action = NULL;
456 irq_desc[i].depth = 1;
460 * 16 old-style INTA-cycle interrupts:
462 set_irq_chip_and_handler_name(i, &i8259A_chip,
463 handle_level_irq, "XT");
466 * 'high' PCI IRQs filled in on demand
468 irq_desc[i].chip = &no_irq_chip;
473 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
475 void __init native_init_IRQ(void)
481 * Cover the whole vector space, no vector can escape
482 * us. (some of these will be overridden and become
483 * 'special' SMP interrupts)
485 for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
486 int vector = FIRST_EXTERNAL_VECTOR + i;
487 if (vector != IA32_SYSCALL_VECTOR)
488 set_intr_gate(vector, interrupt[i]);
493 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
494 * IPI, driven by wakeup.
496 alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
498 /* IPIs for invalidation */
499 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
500 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
501 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
502 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
503 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
504 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
505 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
506 alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
508 /* IPI for generic function call */
509 alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
511 /* Low priority IPI to cleanup after moving an irq */
512 set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
514 alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
515 alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
517 /* self generated IPI for local APIC timer */
518 alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
520 /* IPI vectors for APIC spurious and error interrupts */
521 alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
522 alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);