2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 static int __init parse_noapic(char *str)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list {
121 struct irq_pin_list *next;
124 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
126 struct irq_pin_list *pin;
129 node = cpu_to_node(cpu);
131 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
132 printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node);
138 struct irq_pin_list *irq_2_pin;
140 cpumask_t old_domain;
141 unsigned move_cleanup_count;
143 u8 move_in_progress : 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending : 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
155 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
156 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
157 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
158 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
159 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
160 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
161 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
162 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
163 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
164 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
165 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
166 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
167 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
168 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
169 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
170 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
173 void __init arch_early_irq_init(void)
176 struct irq_desc *desc;
181 count = ARRAY_SIZE(irq_cfgx);
183 for (i = 0; i < count; i++) {
184 desc = irq_to_desc(i);
185 desc->chip_data = &cfg[i];
189 #ifdef CONFIG_SPARSE_IRQ
190 static struct irq_cfg *irq_cfg(unsigned int irq)
192 struct irq_cfg *cfg = NULL;
193 struct irq_desc *desc;
195 desc = irq_to_desc(irq);
197 cfg = desc->chip_data;
202 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
207 node = cpu_to_node(cpu);
209 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
210 printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
215 void arch_init_chip_data(struct irq_desc *desc, int cpu)
219 cfg = desc->chip_data;
221 desc->chip_data = get_one_free_irq_cfg(cpu);
222 if (!desc->chip_data) {
223 printk(KERN_ERR "can not alloc irq_cfg\n");
229 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
232 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
234 struct irq_pin_list *old_entry, *head, *tail, *entry;
236 cfg->irq_2_pin = NULL;
237 old_entry = old_cfg->irq_2_pin;
241 entry = get_one_free_irq_2_pin(cpu);
245 entry->apic = old_entry->apic;
246 entry->pin = old_entry->pin;
249 old_entry = old_entry->next;
251 entry = get_one_free_irq_2_pin(cpu);
259 /* still use the old one */
262 entry->apic = old_entry->apic;
263 entry->pin = old_entry->pin;
266 old_entry = old_entry->next;
270 cfg->irq_2_pin = head;
273 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
275 struct irq_pin_list *entry, *next;
277 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
280 entry = old_cfg->irq_2_pin;
287 old_cfg->irq_2_pin = NULL;
290 void arch_init_copy_chip_data(struct irq_desc *old_desc,
291 struct irq_desc *desc, int cpu)
294 struct irq_cfg *old_cfg;
296 cfg = get_one_free_irq_cfg(cpu);
301 desc->chip_data = cfg;
303 old_cfg = old_desc->chip_data;
305 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
307 init_copy_irq_2_pin(old_cfg, cfg, cpu);
310 static void free_irq_cfg(struct irq_cfg *old_cfg)
315 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
317 struct irq_cfg *old_cfg, *cfg;
319 old_cfg = old_desc->chip_data;
320 cfg = desc->chip_data;
326 free_irq_2_pin(old_cfg, cfg);
327 free_irq_cfg(old_cfg);
328 old_desc->chip_data = NULL;
332 static void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
334 struct irq_cfg *cfg = desc->chip_data;
336 if (!cfg->move_in_progress) {
337 /* it means that domain is not changed */
338 if (!cpus_intersects(desc->affinity, mask))
339 cfg->move_desc_pending = 1;
345 static struct irq_cfg *irq_cfg(unsigned int irq)
347 return irq < nr_irqs ? irq_cfgx + irq : NULL;
352 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
353 static inline void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask)
360 unsigned int unused[3];
364 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
366 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
367 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
370 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
372 struct io_apic __iomem *io_apic = io_apic_base(apic);
373 writel(reg, &io_apic->index);
374 return readl(&io_apic->data);
377 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
379 struct io_apic __iomem *io_apic = io_apic_base(apic);
380 writel(reg, &io_apic->index);
381 writel(value, &io_apic->data);
385 * Re-write a value: to be used for read-modify-write
386 * cycles where the read already set up the index register.
388 * Older SiS APIC requires we rewrite the index register
390 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
392 struct io_apic __iomem *io_apic = io_apic_base(apic);
395 writel(reg, &io_apic->index);
396 writel(value, &io_apic->data);
399 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
401 struct irq_pin_list *entry;
404 spin_lock_irqsave(&ioapic_lock, flags);
405 entry = cfg->irq_2_pin;
413 reg = io_apic_read(entry->apic, 0x10 + pin*2);
414 /* Is the remote IRR bit set? */
415 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
416 spin_unlock_irqrestore(&ioapic_lock, flags);
423 spin_unlock_irqrestore(&ioapic_lock, flags);
429 struct { u32 w1, w2; };
430 struct IO_APIC_route_entry entry;
433 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
435 union entry_union eu;
437 spin_lock_irqsave(&ioapic_lock, flags);
438 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
439 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
440 spin_unlock_irqrestore(&ioapic_lock, flags);
445 * When we write a new IO APIC routing entry, we need to write the high
446 * word first! If the mask bit in the low word is clear, we will enable
447 * the interrupt, and we need to make sure the entry is fully populated
448 * before that happens.
451 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
453 union entry_union eu;
455 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
456 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
459 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
462 spin_lock_irqsave(&ioapic_lock, flags);
463 __ioapic_write_entry(apic, pin, e);
464 spin_unlock_irqrestore(&ioapic_lock, flags);
468 * When we mask an IO APIC routing entry, we need to write the low
469 * word first, in order to set the mask bit before we change the
472 static void ioapic_mask_entry(int apic, int pin)
475 union entry_union eu = { .entry.mask = 1 };
477 spin_lock_irqsave(&ioapic_lock, flags);
478 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
479 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
480 spin_unlock_irqrestore(&ioapic_lock, flags);
484 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
487 struct irq_pin_list *entry;
488 u8 vector = cfg->vector;
490 entry = cfg->irq_2_pin;
499 #ifdef CONFIG_INTR_REMAP
501 * With interrupt-remapping, destination information comes
502 * from interrupt-remapping table entry.
504 if (!irq_remapped(irq))
505 io_apic_write(apic, 0x11 + pin*2, dest);
507 io_apic_write(apic, 0x11 + pin*2, dest);
509 reg = io_apic_read(apic, 0x10 + pin*2);
510 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
512 io_apic_modify(apic, 0x10 + pin*2, reg);
519 static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask);
521 static void set_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask)
529 cpus_and(tmp, mask, cpu_online_map);
534 cfg = desc->chip_data;
535 if (assign_irq_vector(irq, cfg, mask))
538 set_extra_move_desc(desc, mask);
540 cpus_and(tmp, cfg->domain, mask);
541 dest = cpu_mask_to_apicid(tmp);
543 * Only the high 8 bits are valid.
545 dest = SET_APIC_LOGICAL_ID(dest);
547 spin_lock_irqsave(&ioapic_lock, flags);
548 __target_IO_APIC_irq(irq, dest, cfg);
549 desc->affinity = mask;
550 spin_unlock_irqrestore(&ioapic_lock, flags);
553 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
555 struct irq_desc *desc;
557 desc = irq_to_desc(irq);
559 set_ioapic_affinity_irq_desc(desc, mask);
561 #endif /* CONFIG_SMP */
564 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
565 * shared ISA-space IRQs, so we have to support them. We are super
566 * fast in the common case, and fast for shared ISA-space IRQs.
568 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
570 struct irq_pin_list *entry;
572 entry = cfg->irq_2_pin;
574 entry = get_one_free_irq_2_pin(cpu);
576 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
580 cfg->irq_2_pin = entry;
586 while (entry->next) {
587 /* not again, please */
588 if (entry->apic == apic && entry->pin == pin)
594 entry->next = get_one_free_irq_2_pin(cpu);
601 * Reroute an IRQ to a different pin.
603 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
604 int oldapic, int oldpin,
605 int newapic, int newpin)
607 struct irq_pin_list *entry = cfg->irq_2_pin;
611 if (entry->apic == oldapic && entry->pin == oldpin) {
612 entry->apic = newapic;
615 /* every one is different, right? */
621 /* why? call replace before add? */
623 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
626 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
627 int mask_and, int mask_or,
628 void (*final)(struct irq_pin_list *entry))
631 struct irq_pin_list *entry;
633 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
636 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
639 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
645 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
647 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
651 void io_apic_sync(struct irq_pin_list *entry)
654 * Synchronize the IO-APIC and the CPU by doing
655 * a dummy read from the IO-APIC
657 struct io_apic __iomem *io_apic;
658 io_apic = io_apic_base(entry->apic);
659 readl(&io_apic->data);
662 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
664 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
666 #else /* CONFIG_X86_32 */
667 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
669 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
672 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
674 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
675 IO_APIC_REDIR_MASKED, NULL);
678 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
680 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
681 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
683 #endif /* CONFIG_X86_32 */
685 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
687 struct irq_cfg *cfg = desc->chip_data;
692 spin_lock_irqsave(&ioapic_lock, flags);
693 __mask_IO_APIC_irq(cfg);
694 spin_unlock_irqrestore(&ioapic_lock, flags);
697 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
699 struct irq_cfg *cfg = desc->chip_data;
702 spin_lock_irqsave(&ioapic_lock, flags);
703 __unmask_IO_APIC_irq(cfg);
704 spin_unlock_irqrestore(&ioapic_lock, flags);
707 static void mask_IO_APIC_irq(unsigned int irq)
709 struct irq_desc *desc = irq_to_desc(irq);
711 mask_IO_APIC_irq_desc(desc);
713 static void unmask_IO_APIC_irq(unsigned int irq)
715 struct irq_desc *desc = irq_to_desc(irq);
717 unmask_IO_APIC_irq_desc(desc);
720 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
722 struct IO_APIC_route_entry entry;
724 /* Check delivery_mode to be sure we're not clearing an SMI pin */
725 entry = ioapic_read_entry(apic, pin);
726 if (entry.delivery_mode == dest_SMI)
729 * Disable it in the IO-APIC irq-routing table:
731 ioapic_mask_entry(apic, pin);
734 static void clear_IO_APIC (void)
738 for (apic = 0; apic < nr_ioapics; apic++)
739 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
740 clear_IO_APIC_pin(apic, pin);
743 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
744 void send_IPI_self(int vector)
751 apic_wait_icr_idle();
752 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
754 * Send the IPI. The write to APIC_ICR fires this off.
756 apic_write(APIC_ICR, cfg);
758 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
762 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
763 * specific CPU-side IRQs.
767 static int pirq_entries [MAX_PIRQS];
768 static int pirqs_enabled;
770 static int __init ioapic_pirq_setup(char *str)
773 int ints[MAX_PIRQS+1];
775 get_options(str, ARRAY_SIZE(ints), ints);
777 for (i = 0; i < MAX_PIRQS; i++)
778 pirq_entries[i] = -1;
781 apic_printk(APIC_VERBOSE, KERN_INFO
782 "PIRQ redirection, working around broken MP-BIOS.\n");
784 if (ints[0] < MAX_PIRQS)
787 for (i = 0; i < max; i++) {
788 apic_printk(APIC_VERBOSE, KERN_DEBUG
789 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
791 * PIRQs are mapped upside down, usually.
793 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
798 __setup("pirq=", ioapic_pirq_setup);
799 #endif /* CONFIG_X86_32 */
801 #ifdef CONFIG_INTR_REMAP
802 /* I/O APIC RTE contents at the OS boot up */
803 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
806 * Saves and masks all the unmasked IO-APIC RTE's
808 int save_mask_IO_APIC_setup(void)
810 union IO_APIC_reg_01 reg_01;
815 * The number of IO-APIC IRQ registers (== #pins):
817 for (apic = 0; apic < nr_ioapics; apic++) {
818 spin_lock_irqsave(&ioapic_lock, flags);
819 reg_01.raw = io_apic_read(apic, 1);
820 spin_unlock_irqrestore(&ioapic_lock, flags);
821 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
824 for (apic = 0; apic < nr_ioapics; apic++) {
825 early_ioapic_entries[apic] =
826 kzalloc(sizeof(struct IO_APIC_route_entry) *
827 nr_ioapic_registers[apic], GFP_KERNEL);
828 if (!early_ioapic_entries[apic])
832 for (apic = 0; apic < nr_ioapics; apic++)
833 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
834 struct IO_APIC_route_entry entry;
836 entry = early_ioapic_entries[apic][pin] =
837 ioapic_read_entry(apic, pin);
840 ioapic_write_entry(apic, pin, entry);
848 kfree(early_ioapic_entries[apic--]);
849 memset(early_ioapic_entries, 0,
850 ARRAY_SIZE(early_ioapic_entries));
855 void restore_IO_APIC_setup(void)
859 for (apic = 0; apic < nr_ioapics; apic++) {
860 if (!early_ioapic_entries[apic])
862 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
863 ioapic_write_entry(apic, pin,
864 early_ioapic_entries[apic][pin]);
865 kfree(early_ioapic_entries[apic]);
866 early_ioapic_entries[apic] = NULL;
870 void reinit_intr_remapped_IO_APIC(int intr_remapping)
873 * for now plain restore of previous settings.
874 * TBD: In the case of OS enabling interrupt-remapping,
875 * IO-APIC RTE's need to be setup to point to interrupt-remapping
876 * table entries. for now, do a plain restore, and wait for
877 * the setup_IO_APIC_irqs() to do proper initialization.
879 restore_IO_APIC_setup();
884 * Find the IRQ entry number of a certain pin.
886 static int find_irq_entry(int apic, int pin, int type)
890 for (i = 0; i < mp_irq_entries; i++)
891 if (mp_irqs[i].mp_irqtype == type &&
892 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
893 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
894 mp_irqs[i].mp_dstirq == pin)
901 * Find the pin to which IRQ[irq] (ISA) is connected
903 static int __init find_isa_irq_pin(int irq, int type)
907 for (i = 0; i < mp_irq_entries; i++) {
908 int lbus = mp_irqs[i].mp_srcbus;
910 if (test_bit(lbus, mp_bus_not_pci) &&
911 (mp_irqs[i].mp_irqtype == type) &&
912 (mp_irqs[i].mp_srcbusirq == irq))
914 return mp_irqs[i].mp_dstirq;
919 static int __init find_isa_irq_apic(int irq, int type)
923 for (i = 0; i < mp_irq_entries; i++) {
924 int lbus = mp_irqs[i].mp_srcbus;
926 if (test_bit(lbus, mp_bus_not_pci) &&
927 (mp_irqs[i].mp_irqtype == type) &&
928 (mp_irqs[i].mp_srcbusirq == irq))
931 if (i < mp_irq_entries) {
933 for(apic = 0; apic < nr_ioapics; apic++) {
934 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
943 * Find a specific PCI IRQ entry.
944 * Not an __init, possibly needed by modules
946 static int pin_2_irq(int idx, int apic, int pin);
948 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
950 int apic, i, best_guess = -1;
952 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
954 if (test_bit(bus, mp_bus_not_pci)) {
955 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
958 for (i = 0; i < mp_irq_entries; i++) {
959 int lbus = mp_irqs[i].mp_srcbus;
961 for (apic = 0; apic < nr_ioapics; apic++)
962 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
963 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
966 if (!test_bit(lbus, mp_bus_not_pci) &&
967 !mp_irqs[i].mp_irqtype &&
969 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
970 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
972 if (!(apic || IO_APIC_IRQ(irq)))
975 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
978 * Use the first all-but-pin matching entry as a
979 * best-guess fuzzy result for broken mptables.
988 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
990 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
992 * EISA Edge/Level control register, ELCR
994 static int EISA_ELCR(unsigned int irq)
996 if (irq < NR_IRQS_LEGACY) {
997 unsigned int port = 0x4d0 + (irq >> 3);
998 return (inb(port) >> (irq & 7)) & 1;
1000 apic_printk(APIC_VERBOSE, KERN_INFO
1001 "Broken MPtable reports ISA irq %d\n", irq);
1007 /* ISA interrupts are always polarity zero edge triggered,
1008 * when listed as conforming in the MP table. */
1010 #define default_ISA_trigger(idx) (0)
1011 #define default_ISA_polarity(idx) (0)
1013 /* EISA interrupts are always polarity zero and can be edge or level
1014 * trigger depending on the ELCR value. If an interrupt is listed as
1015 * EISA conforming in the MP table, that means its trigger type must
1016 * be read in from the ELCR */
1018 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1019 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1021 /* PCI interrupts are always polarity one level triggered,
1022 * when listed as conforming in the MP table. */
1024 #define default_PCI_trigger(idx) (1)
1025 #define default_PCI_polarity(idx) (1)
1027 /* MCA interrupts are always polarity zero level triggered,
1028 * when listed as conforming in the MP table. */
1030 #define default_MCA_trigger(idx) (1)
1031 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1033 static int MPBIOS_polarity(int idx)
1035 int bus = mp_irqs[idx].mp_srcbus;
1039 * Determine IRQ line polarity (high active or low active):
1041 switch (mp_irqs[idx].mp_irqflag & 3)
1043 case 0: /* conforms, ie. bus-type dependent polarity */
1044 if (test_bit(bus, mp_bus_not_pci))
1045 polarity = default_ISA_polarity(idx);
1047 polarity = default_PCI_polarity(idx);
1049 case 1: /* high active */
1054 case 2: /* reserved */
1056 printk(KERN_WARNING "broken BIOS!!\n");
1060 case 3: /* low active */
1065 default: /* invalid */
1067 printk(KERN_WARNING "broken BIOS!!\n");
1075 static int MPBIOS_trigger(int idx)
1077 int bus = mp_irqs[idx].mp_srcbus;
1081 * Determine IRQ trigger mode (edge or level sensitive):
1083 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1085 case 0: /* conforms, ie. bus-type dependent */
1086 if (test_bit(bus, mp_bus_not_pci))
1087 trigger = default_ISA_trigger(idx);
1089 trigger = default_PCI_trigger(idx);
1090 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1091 switch (mp_bus_id_to_type[bus]) {
1092 case MP_BUS_ISA: /* ISA pin */
1094 /* set before the switch */
1097 case MP_BUS_EISA: /* EISA pin */
1099 trigger = default_EISA_trigger(idx);
1102 case MP_BUS_PCI: /* PCI pin */
1104 /* set before the switch */
1107 case MP_BUS_MCA: /* MCA pin */
1109 trigger = default_MCA_trigger(idx);
1114 printk(KERN_WARNING "broken BIOS!!\n");
1126 case 2: /* reserved */
1128 printk(KERN_WARNING "broken BIOS!!\n");
1137 default: /* invalid */
1139 printk(KERN_WARNING "broken BIOS!!\n");
1147 static inline int irq_polarity(int idx)
1149 return MPBIOS_polarity(idx);
1152 static inline int irq_trigger(int idx)
1154 return MPBIOS_trigger(idx);
1157 int (*ioapic_renumber_irq)(int ioapic, int irq);
1158 static int pin_2_irq(int idx, int apic, int pin)
1161 int bus = mp_irqs[idx].mp_srcbus;
1164 * Debugging check, we are in big trouble if this message pops up!
1166 if (mp_irqs[idx].mp_dstirq != pin)
1167 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1169 if (test_bit(bus, mp_bus_not_pci)) {
1170 irq = mp_irqs[idx].mp_srcbusirq;
1173 * PCI IRQs are mapped in order
1177 irq += nr_ioapic_registers[i++];
1180 * For MPS mode, so far only needed by ES7000 platform
1182 if (ioapic_renumber_irq)
1183 irq = ioapic_renumber_irq(apic, irq);
1186 #ifdef CONFIG_X86_32
1188 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1190 if ((pin >= 16) && (pin <= 23)) {
1191 if (pirq_entries[pin-16] != -1) {
1192 if (!pirq_entries[pin-16]) {
1193 apic_printk(APIC_VERBOSE, KERN_DEBUG
1194 "disabling PIRQ%d\n", pin-16);
1196 irq = pirq_entries[pin-16];
1197 apic_printk(APIC_VERBOSE, KERN_DEBUG
1198 "using PIRQ%d -> IRQ %d\n",
1208 void lock_vector_lock(void)
1210 /* Used to the online set of cpus does not change
1211 * during assign_irq_vector.
1213 spin_lock(&vector_lock);
1216 void unlock_vector_lock(void)
1218 spin_unlock(&vector_lock);
1221 static int __assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask)
1224 * NOTE! The local APIC isn't very good at handling
1225 * multiple interrupts at the same interrupt level.
1226 * As the interrupt level is determined by taking the
1227 * vector number and shifting that right by 4, we
1228 * want to spread these out a bit so that they don't
1229 * all fall in the same interrupt level.
1231 * Also, we've got to be careful not to trash gate
1232 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1234 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1235 unsigned int old_vector;
1238 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1241 /* Only try and allocate irqs on cpus that are present */
1242 cpus_and(mask, mask, cpu_online_map);
1244 old_vector = cfg->vector;
1247 cpus_and(tmp, cfg->domain, mask);
1248 if (!cpus_empty(tmp))
1252 for_each_cpu_mask_nr(cpu, mask) {
1253 cpumask_t domain, new_mask;
1257 domain = vector_allocation_domain(cpu);
1258 cpus_and(new_mask, domain, cpu_online_map);
1260 vector = current_vector;
1261 offset = current_offset;
1264 if (vector >= first_system_vector) {
1265 /* If we run out of vectors on large boxen, must share them. */
1266 offset = (offset + 1) % 8;
1267 vector = FIRST_DEVICE_VECTOR + offset;
1269 if (unlikely(current_vector == vector))
1271 #ifdef CONFIG_X86_64
1272 if (vector == IA32_SYSCALL_VECTOR)
1275 if (vector == SYSCALL_VECTOR)
1278 for_each_cpu_mask_nr(new_cpu, new_mask)
1279 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1282 current_vector = vector;
1283 current_offset = offset;
1285 cfg->move_in_progress = 1;
1286 cfg->old_domain = cfg->domain;
1288 for_each_cpu_mask_nr(new_cpu, new_mask)
1289 per_cpu(vector_irq, new_cpu)[vector] = irq;
1290 cfg->vector = vector;
1291 cfg->domain = domain;
1297 static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask)
1300 unsigned long flags;
1302 spin_lock_irqsave(&vector_lock, flags);
1303 err = __assign_irq_vector(irq, cfg, mask);
1304 spin_unlock_irqrestore(&vector_lock, flags);
1308 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1313 BUG_ON(!cfg->vector);
1315 vector = cfg->vector;
1316 cpus_and(mask, cfg->domain, cpu_online_map);
1317 for_each_cpu_mask_nr(cpu, mask)
1318 per_cpu(vector_irq, cpu)[vector] = -1;
1321 cpus_clear(cfg->domain);
1323 if (likely(!cfg->move_in_progress))
1325 cpus_and(mask, cfg->old_domain, cpu_online_map);
1326 for_each_cpu_mask_nr(cpu, mask) {
1327 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1329 if (per_cpu(vector_irq, cpu)[vector] != irq)
1331 per_cpu(vector_irq, cpu)[vector] = -1;
1335 cfg->move_in_progress = 0;
1338 void __setup_vector_irq(int cpu)
1340 /* Initialize vector_irq on a new cpu */
1341 /* This function must be called with vector_lock held */
1343 struct irq_cfg *cfg;
1344 struct irq_desc *desc;
1346 /* Mark the inuse vectors */
1347 for_each_irq_desc(irq, desc) {
1348 cfg = desc->chip_data;
1349 if (!cpu_isset(cpu, cfg->domain))
1351 vector = cfg->vector;
1352 per_cpu(vector_irq, cpu)[vector] = irq;
1354 /* Mark the free vectors */
1355 for (vector = 0; vector < NR_VECTORS; ++vector) {
1356 irq = per_cpu(vector_irq, cpu)[vector];
1361 if (!cpu_isset(cpu, cfg->domain))
1362 per_cpu(vector_irq, cpu)[vector] = -1;
1366 static struct irq_chip ioapic_chip;
1367 #ifdef CONFIG_INTR_REMAP
1368 static struct irq_chip ir_ioapic_chip;
1371 #define IOAPIC_AUTO -1
1372 #define IOAPIC_EDGE 0
1373 #define IOAPIC_LEVEL 1
1375 #ifdef CONFIG_X86_32
1376 static inline int IO_APIC_irq_trigger(int irq)
1380 for (apic = 0; apic < nr_ioapics; apic++) {
1381 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1382 idx = find_irq_entry(apic, pin, mp_INT);
1383 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1384 return irq_trigger(idx);
1388 * nonexistent IRQs are edge default
1393 static inline int IO_APIC_irq_trigger(int irq)
1399 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1402 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1403 trigger == IOAPIC_LEVEL)
1404 desc->status |= IRQ_LEVEL;
1406 desc->status &= ~IRQ_LEVEL;
1408 #ifdef CONFIG_INTR_REMAP
1409 if (irq_remapped(irq)) {
1410 desc->status |= IRQ_MOVE_PCNTXT;
1412 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1416 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1417 handle_edge_irq, "edge");
1421 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1422 trigger == IOAPIC_LEVEL)
1423 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1427 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1428 handle_edge_irq, "edge");
1431 static int setup_ioapic_entry(int apic, int irq,
1432 struct IO_APIC_route_entry *entry,
1433 unsigned int destination, int trigger,
1434 int polarity, int vector)
1437 * add it to the IO-APIC irq-routing table:
1439 memset(entry,0,sizeof(*entry));
1441 #ifdef CONFIG_INTR_REMAP
1442 if (intr_remapping_enabled) {
1443 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1445 struct IR_IO_APIC_route_entry *ir_entry =
1446 (struct IR_IO_APIC_route_entry *) entry;
1450 panic("No mapping iommu for ioapic %d\n", apic);
1452 index = alloc_irte(iommu, irq, 1);
1454 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1456 memset(&irte, 0, sizeof(irte));
1459 irte.dst_mode = INT_DEST_MODE;
1460 irte.trigger_mode = trigger;
1461 irte.dlvry_mode = INT_DELIVERY_MODE;
1462 irte.vector = vector;
1463 irte.dest_id = IRTE_DEST(destination);
1465 modify_irte(irq, &irte);
1467 ir_entry->index2 = (index >> 15) & 0x1;
1469 ir_entry->format = 1;
1470 ir_entry->index = (index & 0x7fff);
1474 entry->delivery_mode = INT_DELIVERY_MODE;
1475 entry->dest_mode = INT_DEST_MODE;
1476 entry->dest = destination;
1479 entry->mask = 0; /* enable IRQ */
1480 entry->trigger = trigger;
1481 entry->polarity = polarity;
1482 entry->vector = vector;
1484 /* Mask level triggered irqs.
1485 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1492 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc,
1493 int trigger, int polarity)
1495 struct irq_cfg *cfg;
1496 struct IO_APIC_route_entry entry;
1499 if (!IO_APIC_IRQ(irq))
1502 cfg = desc->chip_data;
1505 if (assign_irq_vector(irq, cfg, mask))
1508 cpus_and(mask, cfg->domain, mask);
1510 apic_printk(APIC_VERBOSE,KERN_DEBUG
1511 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1512 "IRQ %d Mode:%i Active:%i)\n",
1513 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1514 irq, trigger, polarity);
1517 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1518 cpu_mask_to_apicid(mask), trigger, polarity,
1520 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1521 mp_ioapics[apic].mp_apicid, pin);
1522 __clear_irq_vector(irq, cfg);
1526 ioapic_register_intr(irq, desc, trigger);
1527 if (irq < NR_IRQS_LEGACY)
1528 disable_8259A_irq(irq);
1530 ioapic_write_entry(apic, pin, entry);
1533 static void __init setup_IO_APIC_irqs(void)
1535 int apic, pin, idx, irq;
1537 struct irq_desc *desc;
1538 struct irq_cfg *cfg;
1539 int cpu = boot_cpu_id;
1541 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1543 for (apic = 0; apic < nr_ioapics; apic++) {
1544 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1546 idx = find_irq_entry(apic, pin, mp_INT);
1550 apic_printk(APIC_VERBOSE,
1551 KERN_DEBUG " %d-%d",
1552 mp_ioapics[apic].mp_apicid,
1555 apic_printk(APIC_VERBOSE, " %d-%d",
1556 mp_ioapics[apic].mp_apicid,
1561 apic_printk(APIC_VERBOSE,
1562 " (apicid-pin) not connected\n");
1566 irq = pin_2_irq(idx, apic, pin);
1567 #ifdef CONFIG_X86_32
1568 if (multi_timer_check(apic, irq))
1571 desc = irq_to_desc_alloc_cpu(irq, cpu);
1573 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1576 cfg = desc->chip_data;
1577 add_pin_to_irq_cpu(cfg, cpu, apic, pin);
1579 setup_IO_APIC_irq(apic, pin, irq, desc,
1580 irq_trigger(idx), irq_polarity(idx));
1585 apic_printk(APIC_VERBOSE,
1586 " (apicid-pin) not connected\n");
1590 * Set up the timer pin, possibly with the 8259A-master behind.
1592 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1595 struct IO_APIC_route_entry entry;
1597 #ifdef CONFIG_INTR_REMAP
1598 if (intr_remapping_enabled)
1602 memset(&entry, 0, sizeof(entry));
1605 * We use logical delivery to get the timer IRQ
1608 entry.dest_mode = INT_DEST_MODE;
1609 entry.mask = 1; /* mask IRQ now */
1610 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1611 entry.delivery_mode = INT_DELIVERY_MODE;
1614 entry.vector = vector;
1617 * The timer IRQ doesn't have to know that behind the
1618 * scene we may have a 8259A-master in AEOI mode ...
1620 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1623 * Add it to the IO-APIC irq-routing table:
1625 ioapic_write_entry(apic, pin, entry);
1629 __apicdebuginit(void) print_IO_APIC(void)
1632 union IO_APIC_reg_00 reg_00;
1633 union IO_APIC_reg_01 reg_01;
1634 union IO_APIC_reg_02 reg_02;
1635 union IO_APIC_reg_03 reg_03;
1636 unsigned long flags;
1637 struct irq_cfg *cfg;
1638 struct irq_desc *desc;
1641 if (apic_verbosity == APIC_QUIET)
1644 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1645 for (i = 0; i < nr_ioapics; i++)
1646 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1647 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1650 * We are a bit conservative about what we expect. We have to
1651 * know about every hardware change ASAP.
1653 printk(KERN_INFO "testing the IO APIC.......................\n");
1655 for (apic = 0; apic < nr_ioapics; apic++) {
1657 spin_lock_irqsave(&ioapic_lock, flags);
1658 reg_00.raw = io_apic_read(apic, 0);
1659 reg_01.raw = io_apic_read(apic, 1);
1660 if (reg_01.bits.version >= 0x10)
1661 reg_02.raw = io_apic_read(apic, 2);
1662 if (reg_01.bits.version >= 0x20)
1663 reg_03.raw = io_apic_read(apic, 3);
1664 spin_unlock_irqrestore(&ioapic_lock, flags);
1667 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1668 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1669 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1670 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1671 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1673 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1674 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1676 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1677 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1680 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1681 * but the value of reg_02 is read as the previous read register
1682 * value, so ignore it if reg_02 == reg_01.
1684 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1685 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1686 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1690 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1691 * or reg_03, but the value of reg_0[23] is read as the previous read
1692 * register value, so ignore it if reg_03 == reg_0[12].
1694 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1695 reg_03.raw != reg_01.raw) {
1696 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1697 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1700 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1702 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1703 " Stat Dmod Deli Vect: \n");
1705 for (i = 0; i <= reg_01.bits.entries; i++) {
1706 struct IO_APIC_route_entry entry;
1708 entry = ioapic_read_entry(apic, i);
1710 printk(KERN_DEBUG " %02x %03X ",
1715 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1720 entry.delivery_status,
1722 entry.delivery_mode,
1727 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1728 for_each_irq_desc(irq, desc) {
1729 struct irq_pin_list *entry;
1731 cfg = desc->chip_data;
1732 entry = cfg->irq_2_pin;
1735 printk(KERN_DEBUG "IRQ%d ", irq);
1737 printk("-> %d:%d", entry->apic, entry->pin);
1740 entry = entry->next;
1745 printk(KERN_INFO ".................................... done.\n");
1750 __apicdebuginit(void) print_APIC_bitfield(int base)
1755 if (apic_verbosity == APIC_QUIET)
1758 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1759 for (i = 0; i < 8; i++) {
1760 v = apic_read(base + i*0x10);
1761 for (j = 0; j < 32; j++) {
1771 __apicdebuginit(void) print_local_APIC(void *dummy)
1773 unsigned int v, ver, maxlvt;
1776 if (apic_verbosity == APIC_QUIET)
1779 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1780 smp_processor_id(), hard_smp_processor_id());
1781 v = apic_read(APIC_ID);
1782 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1783 v = apic_read(APIC_LVR);
1784 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1785 ver = GET_APIC_VERSION(v);
1786 maxlvt = lapic_get_maxlvt();
1788 v = apic_read(APIC_TASKPRI);
1789 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1791 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1792 if (!APIC_XAPIC(ver)) {
1793 v = apic_read(APIC_ARBPRI);
1794 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1795 v & APIC_ARBPRI_MASK);
1797 v = apic_read(APIC_PROCPRI);
1798 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1802 * Remote read supported only in the 82489DX and local APIC for
1803 * Pentium processors.
1805 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1806 v = apic_read(APIC_RRR);
1807 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1810 v = apic_read(APIC_LDR);
1811 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1812 if (!x2apic_enabled()) {
1813 v = apic_read(APIC_DFR);
1814 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1816 v = apic_read(APIC_SPIV);
1817 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1819 printk(KERN_DEBUG "... APIC ISR field:\n");
1820 print_APIC_bitfield(APIC_ISR);
1821 printk(KERN_DEBUG "... APIC TMR field:\n");
1822 print_APIC_bitfield(APIC_TMR);
1823 printk(KERN_DEBUG "... APIC IRR field:\n");
1824 print_APIC_bitfield(APIC_IRR);
1826 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1827 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1828 apic_write(APIC_ESR, 0);
1830 v = apic_read(APIC_ESR);
1831 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1834 icr = apic_icr_read();
1835 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1836 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1838 v = apic_read(APIC_LVTT);
1839 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1841 if (maxlvt > 3) { /* PC is LVT#4. */
1842 v = apic_read(APIC_LVTPC);
1843 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1845 v = apic_read(APIC_LVT0);
1846 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1847 v = apic_read(APIC_LVT1);
1848 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1850 if (maxlvt > 2) { /* ERR is LVT#3. */
1851 v = apic_read(APIC_LVTERR);
1852 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1855 v = apic_read(APIC_TMICT);
1856 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1857 v = apic_read(APIC_TMCCT);
1858 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1859 v = apic_read(APIC_TDCR);
1860 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1864 __apicdebuginit(void) print_all_local_APICs(void)
1869 for_each_online_cpu(cpu)
1870 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1874 __apicdebuginit(void) print_PIC(void)
1877 unsigned long flags;
1879 if (apic_verbosity == APIC_QUIET)
1882 printk(KERN_DEBUG "\nprinting PIC contents\n");
1884 spin_lock_irqsave(&i8259A_lock, flags);
1886 v = inb(0xa1) << 8 | inb(0x21);
1887 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1889 v = inb(0xa0) << 8 | inb(0x20);
1890 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1894 v = inb(0xa0) << 8 | inb(0x20);
1898 spin_unlock_irqrestore(&i8259A_lock, flags);
1900 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1902 v = inb(0x4d1) << 8 | inb(0x4d0);
1903 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1906 __apicdebuginit(int) print_all_ICs(void)
1909 print_all_local_APICs();
1915 fs_initcall(print_all_ICs);
1918 /* Where if anywhere is the i8259 connect in external int mode */
1919 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1921 void __init enable_IO_APIC(void)
1923 union IO_APIC_reg_01 reg_01;
1924 int i8259_apic, i8259_pin;
1926 unsigned long flags;
1928 #ifdef CONFIG_X86_32
1931 for (i = 0; i < MAX_PIRQS; i++)
1932 pirq_entries[i] = -1;
1936 * The number of IO-APIC IRQ registers (== #pins):
1938 for (apic = 0; apic < nr_ioapics; apic++) {
1939 spin_lock_irqsave(&ioapic_lock, flags);
1940 reg_01.raw = io_apic_read(apic, 1);
1941 spin_unlock_irqrestore(&ioapic_lock, flags);
1942 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1944 for(apic = 0; apic < nr_ioapics; apic++) {
1946 /* See if any of the pins is in ExtINT mode */
1947 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1948 struct IO_APIC_route_entry entry;
1949 entry = ioapic_read_entry(apic, pin);
1951 /* If the interrupt line is enabled and in ExtInt mode
1952 * I have found the pin where the i8259 is connected.
1954 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1955 ioapic_i8259.apic = apic;
1956 ioapic_i8259.pin = pin;
1962 /* Look to see what if the MP table has reported the ExtINT */
1963 /* If we could not find the appropriate pin by looking at the ioapic
1964 * the i8259 probably is not connected the ioapic but give the
1965 * mptable a chance anyway.
1967 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1968 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1969 /* Trust the MP table if nothing is setup in the hardware */
1970 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1971 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1972 ioapic_i8259.pin = i8259_pin;
1973 ioapic_i8259.apic = i8259_apic;
1975 /* Complain if the MP table and the hardware disagree */
1976 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1977 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1979 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1983 * Do not trust the IO-APIC being empty at bootup
1989 * Not an __init, needed by the reboot code
1991 void disable_IO_APIC(void)
1994 * Clear the IO-APIC before rebooting:
1999 * If the i8259 is routed through an IOAPIC
2000 * Put that IOAPIC in virtual wire mode
2001 * so legacy interrupts can be delivered.
2003 if (ioapic_i8259.pin != -1) {
2004 struct IO_APIC_route_entry entry;
2006 memset(&entry, 0, sizeof(entry));
2007 entry.mask = 0; /* Enabled */
2008 entry.trigger = 0; /* Edge */
2010 entry.polarity = 0; /* High */
2011 entry.delivery_status = 0;
2012 entry.dest_mode = 0; /* Physical */
2013 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2015 entry.dest = read_apic_id();
2018 * Add it to the IO-APIC irq-routing table:
2020 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2023 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2026 #ifdef CONFIG_X86_32
2028 * function to set the IO-APIC physical IDs based on the
2029 * values stored in the MPC table.
2031 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2034 static void __init setup_ioapic_ids_from_mpc(void)
2036 union IO_APIC_reg_00 reg_00;
2037 physid_mask_t phys_id_present_map;
2040 unsigned char old_id;
2041 unsigned long flags;
2043 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2047 * Don't check I/O APIC IDs for xAPIC systems. They have
2048 * no meaning without the serial APIC bus.
2050 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2051 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2054 * This is broken; anything with a real cpu count has to
2055 * circumvent this idiocy regardless.
2057 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
2060 * Set the IOAPIC ID to the value stored in the MPC table.
2062 for (apic = 0; apic < nr_ioapics; apic++) {
2064 /* Read the register 0 value */
2065 spin_lock_irqsave(&ioapic_lock, flags);
2066 reg_00.raw = io_apic_read(apic, 0);
2067 spin_unlock_irqrestore(&ioapic_lock, flags);
2069 old_id = mp_ioapics[apic].mp_apicid;
2071 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
2072 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2073 apic, mp_ioapics[apic].mp_apicid);
2074 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2076 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
2080 * Sanity check, is the ID really free? Every APIC in a
2081 * system must have a unique ID or we get lots of nice
2082 * 'stuck on smp_invalidate_needed IPI wait' messages.
2084 if (check_apicid_used(phys_id_present_map,
2085 mp_ioapics[apic].mp_apicid)) {
2086 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2087 apic, mp_ioapics[apic].mp_apicid);
2088 for (i = 0; i < get_physical_broadcast(); i++)
2089 if (!physid_isset(i, phys_id_present_map))
2091 if (i >= get_physical_broadcast())
2092 panic("Max APIC ID exceeded!\n");
2093 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2095 physid_set(i, phys_id_present_map);
2096 mp_ioapics[apic].mp_apicid = i;
2099 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
2100 apic_printk(APIC_VERBOSE, "Setting %d in the "
2101 "phys_id_present_map\n",
2102 mp_ioapics[apic].mp_apicid);
2103 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2108 * We need to adjust the IRQ routing table
2109 * if the ID changed.
2111 if (old_id != mp_ioapics[apic].mp_apicid)
2112 for (i = 0; i < mp_irq_entries; i++)
2113 if (mp_irqs[i].mp_dstapic == old_id)
2114 mp_irqs[i].mp_dstapic
2115 = mp_ioapics[apic].mp_apicid;
2118 * Read the right value from the MPC table and
2119 * write it into the ID register.
2121 apic_printk(APIC_VERBOSE, KERN_INFO
2122 "...changing IO-APIC physical APIC ID to %d ...",
2123 mp_ioapics[apic].mp_apicid);
2125 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
2126 spin_lock_irqsave(&ioapic_lock, flags);
2127 io_apic_write(apic, 0, reg_00.raw);
2128 spin_unlock_irqrestore(&ioapic_lock, flags);
2133 spin_lock_irqsave(&ioapic_lock, flags);
2134 reg_00.raw = io_apic_read(apic, 0);
2135 spin_unlock_irqrestore(&ioapic_lock, flags);
2136 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
2137 printk("could not set ID!\n");
2139 apic_printk(APIC_VERBOSE, " ok.\n");
2144 int no_timer_check __initdata;
2146 static int __init notimercheck(char *s)
2151 __setup("no_timer_check", notimercheck);
2154 * There is a nasty bug in some older SMP boards, their mptable lies
2155 * about the timer IRQ. We do the following to work around the situation:
2157 * - timer IRQ defaults to IO-APIC IRQ
2158 * - if this function detects that timer IRQs are defunct, then we fall
2159 * back to ISA timer IRQs
2161 static int __init timer_irq_works(void)
2163 unsigned long t1 = jiffies;
2164 unsigned long flags;
2169 local_save_flags(flags);
2171 /* Let ten ticks pass... */
2172 mdelay((10 * 1000) / HZ);
2173 local_irq_restore(flags);
2176 * Expect a few ticks at least, to be sure some possible
2177 * glue logic does not lock up after one or two first
2178 * ticks in a non-ExtINT mode. Also the local APIC
2179 * might have cached one ExtINT interrupt. Finally, at
2180 * least one tick may be lost due to delays.
2184 if (time_after(jiffies, t1 + 4))
2190 * In the SMP+IOAPIC case it might happen that there are an unspecified
2191 * number of pending IRQ events unhandled. These cases are very rare,
2192 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2193 * better to do it this way as thus we do not have to be aware of
2194 * 'pending' interrupts in the IRQ path, except at this point.
2197 * Edge triggered needs to resend any interrupt
2198 * that was delayed but this is now handled in the device
2203 * Starting up a edge-triggered IO-APIC interrupt is
2204 * nasty - we need to make sure that we get the edge.
2205 * If it is already asserted for some reason, we need
2206 * return 1 to indicate that is was pending.
2208 * This is not complete - we should be able to fake
2209 * an edge even if it isn't on the 8259A...
2212 static unsigned int startup_ioapic_irq(unsigned int irq)
2214 int was_pending = 0;
2215 unsigned long flags;
2216 struct irq_cfg *cfg;
2218 spin_lock_irqsave(&ioapic_lock, flags);
2219 if (irq < NR_IRQS_LEGACY) {
2220 disable_8259A_irq(irq);
2221 if (i8259A_irq_pending(irq))
2225 __unmask_IO_APIC_irq(cfg);
2226 spin_unlock_irqrestore(&ioapic_lock, flags);
2231 #ifdef CONFIG_X86_64
2232 static int ioapic_retrigger_irq(unsigned int irq)
2235 struct irq_cfg *cfg = irq_cfg(irq);
2236 unsigned long flags;
2238 spin_lock_irqsave(&vector_lock, flags);
2239 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2240 spin_unlock_irqrestore(&vector_lock, flags);
2245 static int ioapic_retrigger_irq(unsigned int irq)
2247 send_IPI_self(irq_cfg(irq)->vector);
2254 * Level and edge triggered IO-APIC interrupts need different handling,
2255 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2256 * handled with the level-triggered descriptor, but that one has slightly
2257 * more overhead. Level-triggered interrupts cannot be handled with the
2258 * edge-triggered handler, without risking IRQ storms and other ugly
2264 #ifdef CONFIG_INTR_REMAP
2265 static void ir_irq_migration(struct work_struct *work);
2267 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2270 * Migrate the IO-APIC irq in the presence of intr-remapping.
2272 * For edge triggered, irq migration is a simple atomic update(of vector
2273 * and cpu destination) of IRTE and flush the hardware cache.
2275 * For level triggered, we need to modify the io-apic RTE aswell with the update
2276 * vector information, along with modifying IRTE with vector and destination.
2277 * So irq migration for level triggered is little bit more complex compared to
2278 * edge triggered migration. But the good news is, we use the same algorithm
2279 * for level triggered migration as we have today, only difference being,
2280 * we now initiate the irq migration from process context instead of the
2281 * interrupt context.
2283 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2284 * suppression) to the IO-APIC, level triggered irq migration will also be
2285 * as simple as edge triggered migration and we can do the irq migration
2286 * with a simple atomic update to IO-APIC RTE.
2288 static void migrate_ioapic_irq_desc(struct irq_desc *desc, cpumask_t mask)
2290 struct irq_cfg *cfg;
2291 cpumask_t tmp, cleanup_mask;
2293 int modify_ioapic_rte;
2295 unsigned long flags;
2298 cpus_and(tmp, mask, cpu_online_map);
2299 if (cpus_empty(tmp))
2303 if (get_irte(irq, &irte))
2306 cfg = desc->chip_data;
2307 if (assign_irq_vector(irq, cfg, mask))
2310 set_extra_move_desc(desc, mask);
2312 cpus_and(tmp, cfg->domain, mask);
2313 dest = cpu_mask_to_apicid(tmp);
2315 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2316 if (modify_ioapic_rte) {
2317 spin_lock_irqsave(&ioapic_lock, flags);
2318 __target_IO_APIC_irq(irq, dest, cfg);
2319 spin_unlock_irqrestore(&ioapic_lock, flags);
2322 irte.vector = cfg->vector;
2323 irte.dest_id = IRTE_DEST(dest);
2326 * Modified the IRTE and flushes the Interrupt entry cache.
2328 modify_irte(irq, &irte);
2330 if (cfg->move_in_progress) {
2331 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2332 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2333 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2334 cfg->move_in_progress = 0;
2337 desc->affinity = mask;
2340 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2343 struct irq_cfg *cfg = desc->chip_data;
2345 mask_IO_APIC_irq_desc(desc);
2347 if (io_apic_level_ack_pending(cfg)) {
2349 * Interrupt in progress. Migrating irq now will change the
2350 * vector information in the IO-APIC RTE and that will confuse
2351 * the EOI broadcast performed by cpu.
2352 * So, delay the irq migration to the next instance.
2354 schedule_delayed_work(&ir_migration_work, 1);
2358 /* everthing is clear. we have right of way */
2359 migrate_ioapic_irq_desc(desc, desc->pending_mask);
2362 desc->status &= ~IRQ_MOVE_PENDING;
2363 cpus_clear(desc->pending_mask);
2366 unmask_IO_APIC_irq_desc(desc);
2371 static void ir_irq_migration(struct work_struct *work)
2374 struct irq_desc *desc;
2376 for_each_irq_desc(irq, desc) {
2377 if (desc->status & IRQ_MOVE_PENDING) {
2378 unsigned long flags;
2380 spin_lock_irqsave(&desc->lock, flags);
2381 if (!desc->chip->set_affinity ||
2382 !(desc->status & IRQ_MOVE_PENDING)) {
2383 desc->status &= ~IRQ_MOVE_PENDING;
2384 spin_unlock_irqrestore(&desc->lock, flags);
2388 desc->chip->set_affinity(irq, desc->pending_mask);
2389 spin_unlock_irqrestore(&desc->lock, flags);
2395 * Migrates the IRQ destination in the process context.
2397 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask)
2399 if (desc->status & IRQ_LEVEL) {
2400 desc->status |= IRQ_MOVE_PENDING;
2401 desc->pending_mask = mask;
2402 migrate_irq_remapped_level_desc(desc);
2406 migrate_ioapic_irq_desc(desc, mask);
2408 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2410 struct irq_desc *desc = irq_to_desc(irq);
2412 set_ir_ioapic_affinity_irq_desc(desc, mask);
2416 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2418 unsigned vector, me;
2420 #ifdef CONFIG_X86_64
2425 me = smp_processor_id();
2426 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2428 struct irq_desc *desc;
2429 struct irq_cfg *cfg;
2430 irq = __get_cpu_var(vector_irq)[vector];
2435 desc = irq_to_desc(irq);
2440 spin_lock(&desc->lock);
2441 if (!cfg->move_cleanup_count)
2444 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2447 __get_cpu_var(vector_irq)[vector] = -1;
2448 cfg->move_cleanup_count--;
2450 spin_unlock(&desc->lock);
2456 static void irq_complete_move(struct irq_desc **descp)
2458 struct irq_desc *desc = *descp;
2459 struct irq_cfg *cfg = desc->chip_data;
2460 unsigned vector, me;
2462 if (likely(!cfg->move_in_progress)) {
2463 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2464 if (likely(!cfg->move_desc_pending))
2467 /* domain has not changed, but affinity did */
2468 me = smp_processor_id();
2469 if (cpu_isset(me, desc->affinity)) {
2470 *descp = desc = move_irq_desc(desc, me);
2471 /* get the new one */
2472 cfg = desc->chip_data;
2473 cfg->move_desc_pending = 0;
2479 vector = ~get_irq_regs()->orig_ax;
2480 me = smp_processor_id();
2481 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2482 cpumask_t cleanup_mask;
2484 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2485 *descp = desc = move_irq_desc(desc, me);
2486 /* get the new one */
2487 cfg = desc->chip_data;
2490 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2491 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2492 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2493 cfg->move_in_progress = 0;
2497 static inline void irq_complete_move(struct irq_desc **descp) {}
2500 #ifdef CONFIG_INTR_REMAP
2501 static void ack_x2apic_level(unsigned int irq)
2506 static void ack_x2apic_edge(unsigned int irq)
2513 static void ack_apic_edge(unsigned int irq)
2515 struct irq_desc *desc = irq_to_desc(irq);
2517 irq_complete_move(&desc);
2518 move_native_irq(irq);
2522 atomic_t irq_mis_count;
2524 static void ack_apic_level(unsigned int irq)
2526 struct irq_desc *desc = irq_to_desc(irq);
2528 #ifdef CONFIG_X86_32
2532 struct irq_cfg *cfg;
2533 int do_unmask_irq = 0;
2535 irq_complete_move(&desc);
2536 #ifdef CONFIG_GENERIC_PENDING_IRQ
2537 /* If we are moving the irq we need to mask it */
2538 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2540 mask_IO_APIC_irq_desc(desc);
2544 #ifdef CONFIG_X86_32
2546 * It appears there is an erratum which affects at least version 0x11
2547 * of I/O APIC (that's the 82093AA and cores integrated into various
2548 * chipsets). Under certain conditions a level-triggered interrupt is
2549 * erroneously delivered as edge-triggered one but the respective IRR
2550 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2551 * message but it will never arrive and further interrupts are blocked
2552 * from the source. The exact reason is so far unknown, but the
2553 * phenomenon was observed when two consecutive interrupt requests
2554 * from a given source get delivered to the same CPU and the source is
2555 * temporarily disabled in between.
2557 * A workaround is to simulate an EOI message manually. We achieve it
2558 * by setting the trigger mode to edge and then to level when the edge
2559 * trigger mode gets detected in the TMR of a local APIC for a
2560 * level-triggered interrupt. We mask the source for the time of the
2561 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2562 * The idea is from Manfred Spraul. --macro
2564 cfg = desc->chip_data;
2567 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2571 * We must acknowledge the irq before we move it or the acknowledge will
2572 * not propagate properly.
2576 /* Now we can move and renable the irq */
2577 if (unlikely(do_unmask_irq)) {
2578 /* Only migrate the irq if the ack has been received.
2580 * On rare occasions the broadcast level triggered ack gets
2581 * delayed going to ioapics, and if we reprogram the
2582 * vector while Remote IRR is still set the irq will never
2585 * To prevent this scenario we read the Remote IRR bit
2586 * of the ioapic. This has two effects.
2587 * - On any sane system the read of the ioapic will
2588 * flush writes (and acks) going to the ioapic from
2590 * - We get to see if the ACK has actually been delivered.
2592 * Based on failed experiments of reprogramming the
2593 * ioapic entry from outside of irq context starting
2594 * with masking the ioapic entry and then polling until
2595 * Remote IRR was clear before reprogramming the
2596 * ioapic I don't trust the Remote IRR bit to be
2597 * completey accurate.
2599 * However there appears to be no other way to plug
2600 * this race, so if the Remote IRR bit is not
2601 * accurate and is causing problems then it is a hardware bug
2602 * and you can go talk to the chipset vendor about it.
2604 cfg = desc->chip_data;
2605 if (!io_apic_level_ack_pending(cfg))
2606 move_masked_irq(irq);
2607 unmask_IO_APIC_irq_desc(desc);
2610 #ifdef CONFIG_X86_32
2611 if (!(v & (1 << (i & 0x1f)))) {
2612 atomic_inc(&irq_mis_count);
2613 spin_lock(&ioapic_lock);
2614 __mask_and_edge_IO_APIC_irq(cfg);
2615 __unmask_and_level_IO_APIC_irq(cfg);
2616 spin_unlock(&ioapic_lock);
2621 static struct irq_chip ioapic_chip __read_mostly = {
2623 .startup = startup_ioapic_irq,
2624 .mask = mask_IO_APIC_irq,
2625 .unmask = unmask_IO_APIC_irq,
2626 .ack = ack_apic_edge,
2627 .eoi = ack_apic_level,
2629 .set_affinity = set_ioapic_affinity_irq,
2631 .retrigger = ioapic_retrigger_irq,
2634 #ifdef CONFIG_INTR_REMAP
2635 static struct irq_chip ir_ioapic_chip __read_mostly = {
2636 .name = "IR-IO-APIC",
2637 .startup = startup_ioapic_irq,
2638 .mask = mask_IO_APIC_irq,
2639 .unmask = unmask_IO_APIC_irq,
2640 .ack = ack_x2apic_edge,
2641 .eoi = ack_x2apic_level,
2643 .set_affinity = set_ir_ioapic_affinity_irq,
2645 .retrigger = ioapic_retrigger_irq,
2649 static inline void init_IO_APIC_traps(void)
2652 struct irq_desc *desc;
2653 struct irq_cfg *cfg;
2656 * NOTE! The local APIC isn't very good at handling
2657 * multiple interrupts at the same interrupt level.
2658 * As the interrupt level is determined by taking the
2659 * vector number and shifting that right by 4, we
2660 * want to spread these out a bit so that they don't
2661 * all fall in the same interrupt level.
2663 * Also, we've got to be careful not to trash gate
2664 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2666 for_each_irq_desc(irq, desc) {
2667 cfg = desc->chip_data;
2668 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2670 * Hmm.. We don't have an entry for this,
2671 * so default to an old-fashioned 8259
2672 * interrupt if we can..
2674 if (irq < NR_IRQS_LEGACY)
2675 make_8259A_irq(irq);
2677 /* Strange. Oh, well.. */
2678 desc->chip = &no_irq_chip;
2684 * The local APIC irq-chip implementation:
2687 static void mask_lapic_irq(unsigned int irq)
2691 v = apic_read(APIC_LVT0);
2692 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2695 static void unmask_lapic_irq(unsigned int irq)
2699 v = apic_read(APIC_LVT0);
2700 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2703 static void ack_lapic_irq(unsigned int irq)
2708 static struct irq_chip lapic_chip __read_mostly = {
2709 .name = "local-APIC",
2710 .mask = mask_lapic_irq,
2711 .unmask = unmask_lapic_irq,
2712 .ack = ack_lapic_irq,
2715 static void lapic_register_intr(int irq, struct irq_desc *desc)
2717 desc->status &= ~IRQ_LEVEL;
2718 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2722 static void __init setup_nmi(void)
2725 * Dirty trick to enable the NMI watchdog ...
2726 * We put the 8259A master into AEOI mode and
2727 * unmask on all local APICs LVT0 as NMI.
2729 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2730 * is from Maciej W. Rozycki - so we do not have to EOI from
2731 * the NMI handler or the timer interrupt.
2733 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2735 enable_NMI_through_LVT0();
2737 apic_printk(APIC_VERBOSE, " done.\n");
2741 * This looks a bit hackish but it's about the only one way of sending
2742 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2743 * not support the ExtINT mode, unfortunately. We need to send these
2744 * cycles as some i82489DX-based boards have glue logic that keeps the
2745 * 8259A interrupt line asserted until INTA. --macro
2747 static inline void __init unlock_ExtINT_logic(void)
2750 struct IO_APIC_route_entry entry0, entry1;
2751 unsigned char save_control, save_freq_select;
2753 pin = find_isa_irq_pin(8, mp_INT);
2758 apic = find_isa_irq_apic(8, mp_INT);
2764 entry0 = ioapic_read_entry(apic, pin);
2765 clear_IO_APIC_pin(apic, pin);
2767 memset(&entry1, 0, sizeof(entry1));
2769 entry1.dest_mode = 0; /* physical delivery */
2770 entry1.mask = 0; /* unmask IRQ now */
2771 entry1.dest = hard_smp_processor_id();
2772 entry1.delivery_mode = dest_ExtINT;
2773 entry1.polarity = entry0.polarity;
2777 ioapic_write_entry(apic, pin, entry1);
2779 save_control = CMOS_READ(RTC_CONTROL);
2780 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2781 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2783 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2788 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2792 CMOS_WRITE(save_control, RTC_CONTROL);
2793 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2794 clear_IO_APIC_pin(apic, pin);
2796 ioapic_write_entry(apic, pin, entry0);
2799 static int disable_timer_pin_1 __initdata;
2800 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2801 static int __init disable_timer_pin_setup(char *arg)
2803 disable_timer_pin_1 = 1;
2806 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2808 int timer_through_8259 __initdata;
2811 * This code may look a bit paranoid, but it's supposed to cooperate with
2812 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2813 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2814 * fanatically on his truly buggy board.
2816 * FIXME: really need to revamp this for all platforms.
2818 static inline void __init check_timer(void)
2820 struct irq_desc *desc = irq_to_desc(0);
2821 struct irq_cfg *cfg = desc->chip_data;
2822 int cpu = boot_cpu_id;
2823 int apic1, pin1, apic2, pin2;
2824 unsigned long flags;
2828 local_irq_save(flags);
2830 ver = apic_read(APIC_LVR);
2831 ver = GET_APIC_VERSION(ver);
2834 * get/set the timer IRQ vector:
2836 disable_8259A_irq(0);
2837 assign_irq_vector(0, cfg, TARGET_CPUS);
2840 * As IRQ0 is to be enabled in the 8259A, the virtual
2841 * wire has to be disabled in the local APIC. Also
2842 * timer interrupts need to be acknowledged manually in
2843 * the 8259A for the i82489DX when using the NMI
2844 * watchdog as that APIC treats NMIs as level-triggered.
2845 * The AEOI mode will finish them in the 8259A
2848 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2850 #ifdef CONFIG_X86_32
2851 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2854 pin1 = find_isa_irq_pin(0, mp_INT);
2855 apic1 = find_isa_irq_apic(0, mp_INT);
2856 pin2 = ioapic_i8259.pin;
2857 apic2 = ioapic_i8259.apic;
2859 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2860 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2861 cfg->vector, apic1, pin1, apic2, pin2);
2864 * Some BIOS writers are clueless and report the ExtINTA
2865 * I/O APIC input from the cascaded 8259A as the timer
2866 * interrupt input. So just in case, if only one pin
2867 * was found above, try it both directly and through the
2871 #ifdef CONFIG_INTR_REMAP
2872 if (intr_remapping_enabled)
2873 panic("BIOS bug: timer not connected to IO-APIC");
2878 } else if (pin2 == -1) {
2885 * Ok, does IRQ0 through the IOAPIC work?
2888 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2889 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2891 unmask_IO_APIC_irq_desc(desc);
2892 if (timer_irq_works()) {
2893 if (nmi_watchdog == NMI_IO_APIC) {
2895 enable_8259A_irq(0);
2897 if (disable_timer_pin_1 > 0)
2898 clear_IO_APIC_pin(0, pin1);
2901 #ifdef CONFIG_INTR_REMAP
2902 if (intr_remapping_enabled)
2903 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2905 clear_IO_APIC_pin(apic1, pin1);
2907 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2908 "8254 timer not connected to IO-APIC\n");
2910 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2911 "(IRQ0) through the 8259A ...\n");
2912 apic_printk(APIC_QUIET, KERN_INFO
2913 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2915 * legacy devices should be connected to IO APIC #0
2917 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2918 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2919 unmask_IO_APIC_irq_desc(desc);
2920 enable_8259A_irq(0);
2921 if (timer_irq_works()) {
2922 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2923 timer_through_8259 = 1;
2924 if (nmi_watchdog == NMI_IO_APIC) {
2925 disable_8259A_irq(0);
2927 enable_8259A_irq(0);
2932 * Cleanup, just in case ...
2934 disable_8259A_irq(0);
2935 clear_IO_APIC_pin(apic2, pin2);
2936 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2939 if (nmi_watchdog == NMI_IO_APIC) {
2940 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2941 "through the IO-APIC - disabling NMI Watchdog!\n");
2942 nmi_watchdog = NMI_NONE;
2944 #ifdef CONFIG_X86_32
2948 apic_printk(APIC_QUIET, KERN_INFO
2949 "...trying to set up timer as Virtual Wire IRQ...\n");
2951 lapic_register_intr(0, desc);
2952 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2953 enable_8259A_irq(0);
2955 if (timer_irq_works()) {
2956 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2959 disable_8259A_irq(0);
2960 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2961 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2963 apic_printk(APIC_QUIET, KERN_INFO
2964 "...trying to set up timer as ExtINT IRQ...\n");
2968 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2970 unlock_ExtINT_logic();
2972 if (timer_irq_works()) {
2973 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2976 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2977 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2978 "report. Then try booting with the 'noapic' option.\n");
2980 local_irq_restore(flags);
2984 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2985 * to devices. However there may be an I/O APIC pin available for
2986 * this interrupt regardless. The pin may be left unconnected, but
2987 * typically it will be reused as an ExtINT cascade interrupt for
2988 * the master 8259A. In the MPS case such a pin will normally be
2989 * reported as an ExtINT interrupt in the MP table. With ACPI
2990 * there is no provision for ExtINT interrupts, and in the absence
2991 * of an override it would be treated as an ordinary ISA I/O APIC
2992 * interrupt, that is edge-triggered and unmasked by default. We
2993 * used to do this, but it caused problems on some systems because
2994 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2995 * the same ExtINT cascade interrupt to drive the local APIC of the
2996 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2997 * the I/O APIC in all cases now. No actual device should request
2998 * it anyway. --macro
3000 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3002 void __init setup_IO_APIC(void)
3005 #ifdef CONFIG_X86_32
3009 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3013 io_apic_irqs = ~PIC_IRQS;
3015 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3017 * Set up IO-APIC IRQ routing.
3019 #ifdef CONFIG_X86_32
3021 setup_ioapic_ids_from_mpc();
3024 setup_IO_APIC_irqs();
3025 init_IO_APIC_traps();
3030 * Called after all the initialization is done. If we didnt find any
3031 * APIC bugs then we can allow the modify fast path
3034 static int __init io_apic_bug_finalize(void)
3036 if (sis_apic_bug == -1)
3041 late_initcall(io_apic_bug_finalize);
3043 struct sysfs_ioapic_data {
3044 struct sys_device dev;
3045 struct IO_APIC_route_entry entry[0];
3047 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3049 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3051 struct IO_APIC_route_entry *entry;
3052 struct sysfs_ioapic_data *data;
3055 data = container_of(dev, struct sysfs_ioapic_data, dev);
3056 entry = data->entry;
3057 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3058 *entry = ioapic_read_entry(dev->id, i);
3063 static int ioapic_resume(struct sys_device *dev)
3065 struct IO_APIC_route_entry *entry;
3066 struct sysfs_ioapic_data *data;
3067 unsigned long flags;
3068 union IO_APIC_reg_00 reg_00;
3071 data = container_of(dev, struct sysfs_ioapic_data, dev);
3072 entry = data->entry;
3074 spin_lock_irqsave(&ioapic_lock, flags);
3075 reg_00.raw = io_apic_read(dev->id, 0);
3076 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
3077 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
3078 io_apic_write(dev->id, 0, reg_00.raw);
3080 spin_unlock_irqrestore(&ioapic_lock, flags);
3081 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3082 ioapic_write_entry(dev->id, i, entry[i]);
3087 static struct sysdev_class ioapic_sysdev_class = {
3089 .suspend = ioapic_suspend,
3090 .resume = ioapic_resume,
3093 static int __init ioapic_init_sysfs(void)
3095 struct sys_device * dev;
3098 error = sysdev_class_register(&ioapic_sysdev_class);
3102 for (i = 0; i < nr_ioapics; i++ ) {
3103 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3104 * sizeof(struct IO_APIC_route_entry);
3105 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3106 if (!mp_ioapic_data[i]) {
3107 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3110 dev = &mp_ioapic_data[i]->dev;
3112 dev->cls = &ioapic_sysdev_class;
3113 error = sysdev_register(dev);
3115 kfree(mp_ioapic_data[i]);
3116 mp_ioapic_data[i] = NULL;
3117 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3125 device_initcall(ioapic_init_sysfs);
3128 * Dynamic irq allocate and deallocation
3130 unsigned int create_irq_nr(unsigned int irq_want)
3132 /* Allocate an unused irq */
3135 unsigned long flags;
3136 struct irq_cfg *cfg_new = NULL;
3137 int cpu = boot_cpu_id;
3138 struct irq_desc *desc_new = NULL;
3141 spin_lock_irqsave(&vector_lock, flags);
3142 for (new = irq_want; new < NR_IRQS; new++) {
3143 if (platform_legacy_irq(new))
3146 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3148 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3151 cfg_new = desc_new->chip_data;
3153 if (cfg_new->vector != 0)
3155 if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0)
3159 spin_unlock_irqrestore(&vector_lock, flags);
3162 dynamic_irq_init(irq);
3163 /* restore it, in case dynamic_irq_init clear it */
3165 desc_new->chip_data = cfg_new;
3170 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3171 int create_irq(void)
3173 unsigned int irq_want;
3176 irq_want = nr_irqs_gsi;
3177 irq = create_irq_nr(irq_want);
3185 void destroy_irq(unsigned int irq)
3187 unsigned long flags;
3188 struct irq_cfg *cfg;
3189 struct irq_desc *desc;
3191 /* store it, in case dynamic_irq_cleanup clear it */
3192 desc = irq_to_desc(irq);
3193 cfg = desc->chip_data;
3194 dynamic_irq_cleanup(irq);
3195 /* connect back irq_cfg */
3197 desc->chip_data = cfg;
3199 #ifdef CONFIG_INTR_REMAP
3202 spin_lock_irqsave(&vector_lock, flags);
3203 __clear_irq_vector(irq, cfg);
3204 spin_unlock_irqrestore(&vector_lock, flags);
3208 * MSI message composition
3210 #ifdef CONFIG_PCI_MSI
3211 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3213 struct irq_cfg *cfg;
3220 err = assign_irq_vector(irq, cfg, tmp);
3224 cpus_and(tmp, cfg->domain, tmp);
3225 dest = cpu_mask_to_apicid(tmp);
3227 #ifdef CONFIG_INTR_REMAP
3228 if (irq_remapped(irq)) {
3233 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3234 BUG_ON(ir_index == -1);
3236 memset (&irte, 0, sizeof(irte));
3239 irte.dst_mode = INT_DEST_MODE;
3240 irte.trigger_mode = 0; /* edge */
3241 irte.dlvry_mode = INT_DELIVERY_MODE;
3242 irte.vector = cfg->vector;
3243 irte.dest_id = IRTE_DEST(dest);
3245 modify_irte(irq, &irte);
3247 msg->address_hi = MSI_ADDR_BASE_HI;
3248 msg->data = sub_handle;
3249 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3251 MSI_ADDR_IR_INDEX1(ir_index) |
3252 MSI_ADDR_IR_INDEX2(ir_index);
3256 msg->address_hi = MSI_ADDR_BASE_HI;
3259 ((INT_DEST_MODE == 0) ?
3260 MSI_ADDR_DEST_MODE_PHYSICAL:
3261 MSI_ADDR_DEST_MODE_LOGICAL) |
3262 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3263 MSI_ADDR_REDIRECTION_CPU:
3264 MSI_ADDR_REDIRECTION_LOWPRI) |
3265 MSI_ADDR_DEST_ID(dest);
3268 MSI_DATA_TRIGGER_EDGE |
3269 MSI_DATA_LEVEL_ASSERT |
3270 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3271 MSI_DATA_DELIVERY_FIXED:
3272 MSI_DATA_DELIVERY_LOWPRI) |
3273 MSI_DATA_VECTOR(cfg->vector);
3279 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3281 struct irq_desc *desc = irq_to_desc(irq);
3282 struct irq_cfg *cfg;
3287 cpus_and(tmp, mask, cpu_online_map);
3288 if (cpus_empty(tmp))
3291 cfg = desc->chip_data;
3292 if (assign_irq_vector(irq, cfg, mask))
3295 set_extra_move_desc(desc, mask);
3297 cpus_and(tmp, cfg->domain, mask);
3298 dest = cpu_mask_to_apicid(tmp);
3300 read_msi_msg_desc(desc, &msg);
3302 msg.data &= ~MSI_DATA_VECTOR_MASK;
3303 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3304 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3305 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3307 write_msi_msg_desc(desc, &msg);
3308 desc->affinity = mask;
3310 #ifdef CONFIG_INTR_REMAP
3312 * Migrate the MSI irq to another cpumask. This migration is
3313 * done in the process context using interrupt-remapping hardware.
3315 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3317 struct irq_desc *desc = irq_to_desc(irq);
3318 struct irq_cfg *cfg;
3320 cpumask_t tmp, cleanup_mask;
3323 cpus_and(tmp, mask, cpu_online_map);
3324 if (cpus_empty(tmp))
3327 if (get_irte(irq, &irte))
3330 cfg = desc->chip_data;
3331 if (assign_irq_vector(irq, cfg, mask))
3334 set_extra_move_desc(desc, mask);
3336 cpus_and(tmp, cfg->domain, mask);
3337 dest = cpu_mask_to_apicid(tmp);
3339 irte.vector = cfg->vector;
3340 irte.dest_id = IRTE_DEST(dest);
3343 * atomically update the IRTE with the new destination and vector.
3345 modify_irte(irq, &irte);
3348 * After this point, all the interrupts will start arriving
3349 * at the new destination. So, time to cleanup the previous
3350 * vector allocation.
3352 if (cfg->move_in_progress) {
3353 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3354 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3355 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3356 cfg->move_in_progress = 0;
3359 desc->affinity = mask;
3363 #endif /* CONFIG_SMP */
3366 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3367 * which implement the MSI or MSI-X Capability Structure.
3369 static struct irq_chip msi_chip = {
3371 .unmask = unmask_msi_irq,
3372 .mask = mask_msi_irq,
3373 .ack = ack_apic_edge,
3375 .set_affinity = set_msi_irq_affinity,
3377 .retrigger = ioapic_retrigger_irq,
3380 #ifdef CONFIG_INTR_REMAP
3381 static struct irq_chip msi_ir_chip = {
3382 .name = "IR-PCI-MSI",
3383 .unmask = unmask_msi_irq,
3384 .mask = mask_msi_irq,
3385 .ack = ack_x2apic_edge,
3387 .set_affinity = ir_set_msi_irq_affinity,
3389 .retrigger = ioapic_retrigger_irq,
3393 * Map the PCI dev to the corresponding remapping hardware unit
3394 * and allocate 'nvec' consecutive interrupt-remapping table entries
3397 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3399 struct intel_iommu *iommu;
3402 iommu = map_dev_to_ir(dev);
3405 "Unable to map PCI %s to iommu\n", pci_name(dev));
3409 index = alloc_irte(iommu, irq, nvec);
3412 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3420 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3425 ret = msi_compose_msg(dev, irq, &msg);
3429 set_irq_msi(irq, msidesc);
3430 write_msi_msg(irq, &msg);
3432 #ifdef CONFIG_INTR_REMAP
3433 if (irq_remapped(irq)) {
3434 struct irq_desc *desc = irq_to_desc(irq);
3436 * irq migration in process context
3438 desc->status |= IRQ_MOVE_PCNTXT;
3439 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3442 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3444 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3449 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc)
3453 unsigned int irq_want;
3455 irq_want = nr_irqs_gsi;
3456 irq = create_irq_nr(irq_want);
3460 #ifdef CONFIG_INTR_REMAP
3461 if (!intr_remapping_enabled)
3464 ret = msi_alloc_irte(dev, irq, 1);
3469 ret = setup_msi_irq(dev, msidesc, irq);
3476 #ifdef CONFIG_INTR_REMAP
3483 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3486 int ret, sub_handle;
3487 struct msi_desc *msidesc;
3488 unsigned int irq_want;
3490 #ifdef CONFIG_INTR_REMAP
3491 struct intel_iommu *iommu = 0;
3495 irq_want = nr_irqs_gsi;
3497 list_for_each_entry(msidesc, &dev->msi_list, list) {
3498 irq = create_irq_nr(irq_want);
3502 #ifdef CONFIG_INTR_REMAP
3503 if (!intr_remapping_enabled)
3508 * allocate the consecutive block of IRTE's
3511 index = msi_alloc_irte(dev, irq, nvec);
3517 iommu = map_dev_to_ir(dev);
3523 * setup the mapping between the irq and the IRTE
3524 * base index, the sub_handle pointing to the
3525 * appropriate interrupt remap table entry.
3527 set_irte_irq(irq, iommu, index, sub_handle);
3531 ret = setup_msi_irq(dev, msidesc, irq);
3543 void arch_teardown_msi_irq(unsigned int irq)
3550 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3552 struct irq_desc *desc = irq_to_desc(irq);
3553 struct irq_cfg *cfg;
3558 cpus_and(tmp, mask, cpu_online_map);
3559 if (cpus_empty(tmp))
3562 cfg = desc->chip_data;
3563 if (assign_irq_vector(irq, cfg, mask))
3566 set_extra_move_desc(desc, mask);
3568 cpus_and(tmp, cfg->domain, mask);
3569 dest = cpu_mask_to_apicid(tmp);
3571 dmar_msi_read(irq, &msg);
3573 msg.data &= ~MSI_DATA_VECTOR_MASK;
3574 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3575 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3576 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3578 dmar_msi_write(irq, &msg);
3579 desc->affinity = mask;
3582 #endif /* CONFIG_SMP */
3584 struct irq_chip dmar_msi_type = {
3586 .unmask = dmar_msi_unmask,
3587 .mask = dmar_msi_mask,
3588 .ack = ack_apic_edge,
3590 .set_affinity = dmar_msi_set_affinity,
3592 .retrigger = ioapic_retrigger_irq,
3595 int arch_setup_dmar_msi(unsigned int irq)
3600 ret = msi_compose_msg(NULL, irq, &msg);
3603 dmar_msi_write(irq, &msg);
3604 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3610 #ifdef CONFIG_HPET_TIMER
3613 static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask)
3615 struct irq_desc *desc = irq_to_desc(irq);
3616 struct irq_cfg *cfg;
3621 cpus_and(tmp, mask, cpu_online_map);
3622 if (cpus_empty(tmp))
3625 cfg = desc->chip_data;
3626 if (assign_irq_vector(irq, cfg, mask))
3629 set_extra_move_desc(desc, mask);
3631 cpus_and(tmp, cfg->domain, mask);
3632 dest = cpu_mask_to_apicid(tmp);
3634 hpet_msi_read(irq, &msg);
3636 msg.data &= ~MSI_DATA_VECTOR_MASK;
3637 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3638 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3639 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3641 hpet_msi_write(irq, &msg);
3642 desc->affinity = mask;
3645 #endif /* CONFIG_SMP */
3647 struct irq_chip hpet_msi_type = {
3649 .unmask = hpet_msi_unmask,
3650 .mask = hpet_msi_mask,
3651 .ack = ack_apic_edge,
3653 .set_affinity = hpet_msi_set_affinity,
3655 .retrigger = ioapic_retrigger_irq,
3658 int arch_setup_hpet_msi(unsigned int irq)
3663 ret = msi_compose_msg(NULL, irq, &msg);
3667 hpet_msi_write(irq, &msg);
3668 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3675 #endif /* CONFIG_PCI_MSI */
3677 * Hypertransport interrupt support
3679 #ifdef CONFIG_HT_IRQ
3683 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3685 struct ht_irq_msg msg;
3686 fetch_ht_irq_msg(irq, &msg);
3688 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3689 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3691 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3692 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3694 write_ht_irq_msg(irq, &msg);
3697 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3699 struct irq_desc *desc = irq_to_desc(irq);
3700 struct irq_cfg *cfg;
3704 cpus_and(tmp, mask, cpu_online_map);
3705 if (cpus_empty(tmp))
3708 cfg = desc->chip_data;
3709 if (assign_irq_vector(irq, cfg, mask))
3712 set_extra_move_desc(desc, mask);
3714 cpus_and(tmp, cfg->domain, mask);
3715 dest = cpu_mask_to_apicid(tmp);
3717 target_ht_irq(irq, dest, cfg->vector);
3718 desc->affinity = mask;
3723 static struct irq_chip ht_irq_chip = {
3725 .mask = mask_ht_irq,
3726 .unmask = unmask_ht_irq,
3727 .ack = ack_apic_edge,
3729 .set_affinity = set_ht_irq_affinity,
3731 .retrigger = ioapic_retrigger_irq,
3734 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3736 struct irq_cfg *cfg;
3742 err = assign_irq_vector(irq, cfg, tmp);
3744 struct ht_irq_msg msg;
3747 cpus_and(tmp, cfg->domain, tmp);
3748 dest = cpu_mask_to_apicid(tmp);
3750 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3754 HT_IRQ_LOW_DEST_ID(dest) |
3755 HT_IRQ_LOW_VECTOR(cfg->vector) |
3756 ((INT_DEST_MODE == 0) ?
3757 HT_IRQ_LOW_DM_PHYSICAL :
3758 HT_IRQ_LOW_DM_LOGICAL) |
3759 HT_IRQ_LOW_RQEOI_EDGE |
3760 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3761 HT_IRQ_LOW_MT_FIXED :
3762 HT_IRQ_LOW_MT_ARBITRATED) |
3763 HT_IRQ_LOW_IRQ_MASKED;
3765 write_ht_irq_msg(irq, &msg);
3767 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3768 handle_edge_irq, "edge");
3770 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3774 #endif /* CONFIG_HT_IRQ */
3776 #ifdef CONFIG_X86_64
3778 * Re-target the irq to the specified CPU and enable the specified MMR located
3779 * on the specified blade to allow the sending of MSIs to the specified CPU.
3781 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3782 unsigned long mmr_offset)
3784 const cpumask_t *eligible_cpu = get_cpu_mask(cpu);
3785 struct irq_cfg *cfg;
3787 unsigned long mmr_value;
3788 struct uv_IO_APIC_route_entry *entry;
3789 unsigned long flags;
3794 err = assign_irq_vector(irq, cfg, *eligible_cpu);
3798 spin_lock_irqsave(&vector_lock, flags);
3799 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3801 spin_unlock_irqrestore(&vector_lock, flags);
3804 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3805 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3807 entry->vector = cfg->vector;
3808 entry->delivery_mode = INT_DELIVERY_MODE;
3809 entry->dest_mode = INT_DEST_MODE;
3810 entry->polarity = 0;
3813 entry->dest = cpu_mask_to_apicid(*eligible_cpu);
3815 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3816 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3822 * Disable the specified MMR located on the specified blade so that MSIs are
3823 * longer allowed to be sent.
3825 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3827 unsigned long mmr_value;
3828 struct uv_IO_APIC_route_entry *entry;
3832 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3833 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3837 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3838 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3840 #endif /* CONFIG_X86_64 */
3842 int __init io_apic_get_redir_entries (int ioapic)
3844 union IO_APIC_reg_01 reg_01;
3845 unsigned long flags;
3847 spin_lock_irqsave(&ioapic_lock, flags);
3848 reg_01.raw = io_apic_read(ioapic, 1);
3849 spin_unlock_irqrestore(&ioapic_lock, flags);
3851 return reg_01.bits.entries;
3854 void __init probe_nr_irqs_gsi(void)
3859 for (idx = 0; idx < nr_ioapics; idx++)
3860 nr += io_apic_get_redir_entries(idx) + 1;
3862 if (nr > nr_irqs_gsi)
3866 /* --------------------------------------------------------------------------
3867 ACPI-based IOAPIC Configuration
3868 -------------------------------------------------------------------------- */
3872 #ifdef CONFIG_X86_32
3873 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3875 union IO_APIC_reg_00 reg_00;
3876 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3878 unsigned long flags;
3882 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3883 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3884 * supports up to 16 on one shared APIC bus.
3886 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3887 * advantage of new APIC bus architecture.
3890 if (physids_empty(apic_id_map))
3891 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3893 spin_lock_irqsave(&ioapic_lock, flags);
3894 reg_00.raw = io_apic_read(ioapic, 0);
3895 spin_unlock_irqrestore(&ioapic_lock, flags);
3897 if (apic_id >= get_physical_broadcast()) {
3898 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3899 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3900 apic_id = reg_00.bits.ID;
3904 * Every APIC in a system must have a unique ID or we get lots of nice
3905 * 'stuck on smp_invalidate_needed IPI wait' messages.
3907 if (check_apicid_used(apic_id_map, apic_id)) {
3909 for (i = 0; i < get_physical_broadcast(); i++) {
3910 if (!check_apicid_used(apic_id_map, i))
3914 if (i == get_physical_broadcast())
3915 panic("Max apic_id exceeded!\n");
3917 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3918 "trying %d\n", ioapic, apic_id, i);
3923 tmp = apicid_to_cpu_present(apic_id);
3924 physids_or(apic_id_map, apic_id_map, tmp);
3926 if (reg_00.bits.ID != apic_id) {
3927 reg_00.bits.ID = apic_id;
3929 spin_lock_irqsave(&ioapic_lock, flags);
3930 io_apic_write(ioapic, 0, reg_00.raw);
3931 reg_00.raw = io_apic_read(ioapic, 0);
3932 spin_unlock_irqrestore(&ioapic_lock, flags);
3935 if (reg_00.bits.ID != apic_id) {
3936 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3941 apic_printk(APIC_VERBOSE, KERN_INFO
3942 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3947 int __init io_apic_get_version(int ioapic)
3949 union IO_APIC_reg_01 reg_01;
3950 unsigned long flags;
3952 spin_lock_irqsave(&ioapic_lock, flags);
3953 reg_01.raw = io_apic_read(ioapic, 1);
3954 spin_unlock_irqrestore(&ioapic_lock, flags);
3956 return reg_01.bits.version;
3960 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3962 struct irq_desc *desc;
3963 struct irq_cfg *cfg;
3964 int cpu = boot_cpu_id;
3966 if (!IO_APIC_IRQ(irq)) {
3967 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3972 desc = irq_to_desc_alloc_cpu(irq, cpu);
3974 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3979 * IRQs < 16 are already in the irq_2_pin[] map
3981 if (irq >= NR_IRQS_LEGACY) {
3982 cfg = desc->chip_data;
3983 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3986 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3992 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3996 if (skip_ioapic_setup)
3999 for (i = 0; i < mp_irq_entries; i++)
4000 if (mp_irqs[i].mp_irqtype == mp_INT &&
4001 mp_irqs[i].mp_srcbusirq == bus_irq)
4003 if (i >= mp_irq_entries)
4006 *trigger = irq_trigger(i);
4007 *polarity = irq_polarity(i);
4011 #endif /* CONFIG_ACPI */
4014 * This function currently is only a helper for the i386 smp boot process where
4015 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4016 * so mask in all cases should simply be TARGET_CPUS
4019 void __init setup_ioapic_dest(void)
4021 int pin, ioapic, irq, irq_entry;
4022 struct irq_desc *desc;
4023 struct irq_cfg *cfg;
4026 if (skip_ioapic_setup == 1)
4029 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4030 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4031 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4032 if (irq_entry == -1)
4034 irq = pin_2_irq(irq_entry, ioapic, pin);
4036 /* setup_IO_APIC_irqs could fail to get vector for some device
4037 * when you have too many devices, because at that time only boot
4040 desc = irq_to_desc(irq);
4041 cfg = desc->chip_data;
4043 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4044 irq_trigger(irq_entry),
4045 irq_polarity(irq_entry));
4051 * Honour affinities which have been set in early boot
4054 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4055 mask = desc->affinity;
4059 #ifdef CONFIG_INTR_REMAP
4060 if (intr_remapping_enabled)
4061 set_ir_ioapic_affinity_irq_desc(desc, mask);
4064 set_ioapic_affinity_irq_desc(desc, mask);
4071 #define IOAPIC_RESOURCE_NAME_SIZE 11
4073 static struct resource *ioapic_resources;
4075 static struct resource * __init ioapic_setup_resources(void)
4078 struct resource *res;
4082 if (nr_ioapics <= 0)
4085 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4088 mem = alloc_bootmem(n);
4092 mem += sizeof(struct resource) * nr_ioapics;
4094 for (i = 0; i < nr_ioapics; i++) {
4096 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4097 sprintf(mem, "IOAPIC %u", i);
4098 mem += IOAPIC_RESOURCE_NAME_SIZE;
4102 ioapic_resources = res;
4107 void __init ioapic_init_mappings(void)
4109 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4110 struct resource *ioapic_res;
4113 ioapic_res = ioapic_setup_resources();
4114 for (i = 0; i < nr_ioapics; i++) {
4115 if (smp_found_config) {
4116 ioapic_phys = mp_ioapics[i].mp_apicaddr;
4117 #ifdef CONFIG_X86_32
4120 "WARNING: bogus zero IO-APIC "
4121 "address found in MPTABLE, "
4122 "disabling IO/APIC support!\n");
4123 smp_found_config = 0;
4124 skip_ioapic_setup = 1;
4125 goto fake_ioapic_page;
4129 #ifdef CONFIG_X86_32
4132 ioapic_phys = (unsigned long)
4133 alloc_bootmem_pages(PAGE_SIZE);
4134 ioapic_phys = __pa(ioapic_phys);
4136 set_fixmap_nocache(idx, ioapic_phys);
4137 apic_printk(APIC_VERBOSE,
4138 "mapped IOAPIC to %08lx (%08lx)\n",
4139 __fix_to_virt(idx), ioapic_phys);
4142 if (ioapic_res != NULL) {
4143 ioapic_res->start = ioapic_phys;
4144 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4150 static int __init ioapic_insert_resources(void)
4153 struct resource *r = ioapic_resources;
4157 "IO APIC resources could be not be allocated.\n");
4161 for (i = 0; i < nr_ioapics; i++) {
4162 insert_resource(&iomem_resource, r);
4169 /* Insert the IO APIC resources after PCI initialization has occured to handle
4170 * IO APICS that are mapped in on a BAR in PCI space. */
4171 late_initcall(ioapic_insert_resources);