2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
61 int timer_over_8254 __initdata = 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug = -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers[MAX_IO_APICS];
74 static int disable_timer_pin_1 __initdata;
77 * Rough estimation of how many shared IRQs there are, can
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84 * This is performance-critical, we want to do it O(1)
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
90 static struct irq_pin_list {
92 } irq_2_pin[PIN_MAP_SIZE];
96 unsigned int unused[3];
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
102 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
108 struct io_apic __iomem *io_apic = io_apic_base(apic);
109 writel(reg, &io_apic->index);
110 return readl(&io_apic->data);
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
115 struct io_apic __iomem *io_apic = io_apic_base(apic);
116 writel(reg, &io_apic->index);
117 writel(value, &io_apic->data);
121 * Re-write a value: to be used for read-modify-write
122 * cycles where the read already set up the index register.
124 * Older SiS APIC requires we rewrite the index register
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
128 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
130 writel(reg, &io_apic->index);
131 writel(value, &io_apic->data);
135 struct { u32 w1, w2; };
136 struct IO_APIC_route_entry entry;
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
141 union entry_union eu;
143 spin_lock_irqsave(&ioapic_lock, flags);
144 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146 spin_unlock_irqrestore(&ioapic_lock, flags);
151 * When we write a new IO APIC routing entry, we need to write the high
152 * word first! If the mask bit in the low word is clear, we will enable
153 * the interrupt, and we need to make sure the entry is fully populated
154 * before that happens.
157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
159 union entry_union eu;
161 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
162 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
168 spin_lock_irqsave(&ioapic_lock, flags);
169 __ioapic_write_entry(apic, pin, e);
170 spin_unlock_irqrestore(&ioapic_lock, flags);
174 * When we mask an IO APIC routing entry, we need to write the low
175 * word first, in order to set the mask bit before we change the
178 static void ioapic_mask_entry(int apic, int pin)
181 union entry_union eu = { .entry.mask = 1 };
183 spin_lock_irqsave(&ioapic_lock, flags);
184 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
186 spin_unlock_irqrestore(&ioapic_lock, flags);
190 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191 * shared ISA-space IRQs, so we have to support them. We are super
192 * fast in the common case, and fast for shared ISA-space IRQs.
194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
196 static int first_free_entry = NR_IRQS;
197 struct irq_pin_list *entry = irq_2_pin + irq;
200 entry = irq_2_pin + entry->next;
202 if (entry->pin != -1) {
203 entry->next = first_free_entry;
204 entry = irq_2_pin + entry->next;
205 if (++first_free_entry >= PIN_MAP_SIZE)
206 panic("io_apic.c: whoops");
213 * Reroute an IRQ to a different pin.
215 static void __init replace_pin_at_irq(unsigned int irq,
216 int oldapic, int oldpin,
217 int newapic, int newpin)
219 struct irq_pin_list *entry = irq_2_pin + irq;
222 if (entry->apic == oldapic && entry->pin == oldpin) {
223 entry->apic = newapic;
228 entry = irq_2_pin + entry->next;
232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
234 struct irq_pin_list *entry = irq_2_pin + irq;
235 unsigned int pin, reg;
241 reg = io_apic_read(entry->apic, 0x10 + pin*2);
244 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
247 entry = irq_2_pin + entry->next;
252 static void __mask_IO_APIC_irq (unsigned int irq)
254 __modify_IO_APIC_irq(irq, 0x00010000, 0);
258 static void __unmask_IO_APIC_irq (unsigned int irq)
260 __modify_IO_APIC_irq(irq, 0, 0x00010000);
263 /* mask = 1, trigger = 0 */
264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
266 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
269 /* mask = 0, trigger = 1 */
270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
272 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
275 static void mask_IO_APIC_irq (unsigned int irq)
279 spin_lock_irqsave(&ioapic_lock, flags);
280 __mask_IO_APIC_irq(irq);
281 spin_unlock_irqrestore(&ioapic_lock, flags);
284 static void unmask_IO_APIC_irq (unsigned int irq)
288 spin_lock_irqsave(&ioapic_lock, flags);
289 __unmask_IO_APIC_irq(irq);
290 spin_unlock_irqrestore(&ioapic_lock, flags);
293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
295 struct IO_APIC_route_entry entry;
297 /* Check delivery_mode to be sure we're not clearing an SMI pin */
298 entry = ioapic_read_entry(apic, pin);
299 if (entry.delivery_mode == dest_SMI)
303 * Disable it in the IO-APIC irq-routing table:
305 ioapic_mask_entry(apic, pin);
308 static void clear_IO_APIC (void)
312 for (apic = 0; apic < nr_ioapics; apic++)
313 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
314 clear_IO_APIC_pin(apic, pin);
318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
322 struct irq_pin_list *entry = irq_2_pin + irq;
323 unsigned int apicid_value;
326 cpus_and(tmp, cpumask, cpu_online_map);
330 cpus_and(cpumask, tmp, CPU_MASK_ALL);
332 apicid_value = cpu_mask_to_apicid(cpumask);
333 /* Prepare to do the io_apic_write */
334 apicid_value = apicid_value << 24;
335 spin_lock_irqsave(&ioapic_lock, flags);
340 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
343 entry = irq_2_pin + entry->next;
345 irq_desc[irq].affinity = cpumask;
346 spin_unlock_irqrestore(&ioapic_lock, flags);
349 #if defined(CONFIG_IRQBALANCE)
350 # include <asm/processor.h> /* kernel_thread() */
351 # include <linux/kernel_stat.h> /* kstat */
352 # include <linux/slab.h> /* kmalloc() */
353 # include <linux/timer.h>
355 #define IRQBALANCE_CHECK_ARCH -999
356 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
357 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
358 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
359 #define BALANCED_IRQ_LESS_DELTA (HZ)
361 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
362 static int physical_balance __read_mostly;
363 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
365 static struct irq_cpu_info {
366 unsigned long * last_irq;
367 unsigned long * irq_delta;
369 } irq_cpu_data[NR_CPUS];
371 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
372 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
373 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
375 #define IDLE_ENOUGH(cpu,now) \
376 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
378 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
382 static cpumask_t balance_irq_affinity[NR_IRQS] = {
383 [0 ... NR_IRQS-1] = CPU_MASK_ALL
386 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
388 balance_irq_affinity[irq] = mask;
391 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
392 unsigned long now, int direction)
400 if (unlikely(cpu == curr_cpu))
403 if (direction == 1) {
412 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
413 (search_idle && !IDLE_ENOUGH(cpu,now)));
418 static inline void balance_irq(int cpu, int irq)
420 unsigned long now = jiffies;
421 cpumask_t allowed_mask;
422 unsigned int new_cpu;
424 if (irqbalance_disabled)
427 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
428 new_cpu = move(cpu, allowed_mask, now, 1);
429 if (cpu != new_cpu) {
430 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
438 for_each_online_cpu(i) {
439 for (j = 0; j < NR_IRQS; j++) {
440 if (!irq_desc[j].action)
442 /* Is it a significant load ? */
443 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
444 useful_load_threshold)
449 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
450 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
454 static void do_irq_balance(void)
457 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
458 unsigned long move_this_load = 0;
459 int max_loaded = 0, min_loaded = 0;
461 unsigned long useful_load_threshold = balanced_irq_interval + 10;
463 int tmp_loaded, first_attempt = 1;
464 unsigned long tmp_cpu_irq;
465 unsigned long imbalance = 0;
466 cpumask_t allowed_mask, target_cpu_mask, tmp;
468 for_each_possible_cpu(i) {
473 package_index = CPU_TO_PACKAGEINDEX(i);
474 for (j = 0; j < NR_IRQS; j++) {
475 unsigned long value_now, delta;
476 /* Is this an active IRQ or balancing disabled ? */
477 if (!irq_desc[j].action || irq_balancing_disabled(j))
479 if ( package_index == i )
480 IRQ_DELTA(package_index,j) = 0;
481 /* Determine the total count per processor per IRQ */
482 value_now = (unsigned long) kstat_cpu(i).irqs[j];
484 /* Determine the activity per processor per IRQ */
485 delta = value_now - LAST_CPU_IRQ(i,j);
487 /* Update last_cpu_irq[][] for the next time */
488 LAST_CPU_IRQ(i,j) = value_now;
490 /* Ignore IRQs whose rate is less than the clock */
491 if (delta < useful_load_threshold)
493 /* update the load for the processor or package total */
494 IRQ_DELTA(package_index,j) += delta;
496 /* Keep track of the higher numbered sibling as well */
497 if (i != package_index)
500 * We have sibling A and sibling B in the package
502 * cpu_irq[A] = load for cpu A + load for cpu B
503 * cpu_irq[B] = load for cpu B
505 CPU_IRQ(package_index) += delta;
508 /* Find the least loaded processor package */
509 for_each_online_cpu(i) {
510 if (i != CPU_TO_PACKAGEINDEX(i))
512 if (min_cpu_irq > CPU_IRQ(i)) {
513 min_cpu_irq = CPU_IRQ(i);
517 max_cpu_irq = ULONG_MAX;
520 /* Look for heaviest loaded processor.
521 * We may come back to get the next heaviest loaded processor.
522 * Skip processors with trivial loads.
526 for_each_online_cpu(i) {
527 if (i != CPU_TO_PACKAGEINDEX(i))
529 if (max_cpu_irq <= CPU_IRQ(i))
531 if (tmp_cpu_irq < CPU_IRQ(i)) {
532 tmp_cpu_irq = CPU_IRQ(i);
537 if (tmp_loaded == -1) {
538 /* In the case of small number of heavy interrupt sources,
539 * loading some of the cpus too much. We use Ingo's original
540 * approach to rotate them around.
542 if (!first_attempt && imbalance >= useful_load_threshold) {
543 rotate_irqs_among_cpus(useful_load_threshold);
546 goto not_worth_the_effort;
549 first_attempt = 0; /* heaviest search */
550 max_cpu_irq = tmp_cpu_irq; /* load */
551 max_loaded = tmp_loaded; /* processor */
552 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
554 /* if imbalance is less than approx 10% of max load, then
555 * observe diminishing returns action. - quit
557 if (imbalance < (max_cpu_irq >> 3))
558 goto not_worth_the_effort;
561 /* if we select an IRQ to move that can't go where we want, then
562 * see if there is another one to try.
566 for (j = 0; j < NR_IRQS; j++) {
567 /* Is this an active IRQ? */
568 if (!irq_desc[j].action)
570 if (imbalance <= IRQ_DELTA(max_loaded,j))
572 /* Try to find the IRQ that is closest to the imbalance
573 * without going over.
575 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
576 move_this_load = IRQ_DELTA(max_loaded,j);
580 if (selected_irq == -1) {
584 imbalance = move_this_load;
586 /* For physical_balance case, we accumulated both load
587 * values in the one of the siblings cpu_irq[],
588 * to use the same code for physical and logical processors
589 * as much as possible.
591 * NOTE: the cpu_irq[] array holds the sum of the load for
592 * sibling A and sibling B in the slot for the lowest numbered
593 * sibling (A), _AND_ the load for sibling B in the slot for
594 * the higher numbered sibling.
596 * We seek the least loaded sibling by making the comparison
599 load = CPU_IRQ(min_loaded) >> 1;
600 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
601 if (load > CPU_IRQ(j)) {
602 /* This won't change cpu_sibling_map[min_loaded] */
608 cpus_and(allowed_mask,
610 balance_irq_affinity[selected_irq]);
611 target_cpu_mask = cpumask_of_cpu(min_loaded);
612 cpus_and(tmp, target_cpu_mask, allowed_mask);
614 if (!cpus_empty(tmp)) {
615 /* mark for change destination */
616 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
618 /* Since we made a change, come back sooner to
619 * check for more variation.
621 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
622 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
627 not_worth_the_effort:
629 * if we did not find an IRQ to move, then adjust the time interval
632 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
633 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
637 static int balanced_irq(void *unused)
640 unsigned long prev_balance_time = jiffies;
641 long time_remaining = balanced_irq_interval;
643 /* push everything to CPU 0 to give us a starting point. */
644 for (i = 0 ; i < NR_IRQS ; i++) {
645 irq_desc[i].pending_mask = cpumask_of_cpu(0);
646 set_pending_irq(i, cpumask_of_cpu(0));
651 time_remaining = schedule_timeout_interruptible(time_remaining);
653 if (time_after(jiffies,
654 prev_balance_time+balanced_irq_interval)) {
657 prev_balance_time = jiffies;
658 time_remaining = balanced_irq_interval;
665 static int __init balanced_irq_init(void)
668 struct cpuinfo_x86 *c;
671 cpus_shift_right(tmp, cpu_online_map, 2);
673 /* When not overwritten by the command line ask subarchitecture. */
674 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
675 irqbalance_disabled = NO_BALANCE_IRQ;
676 if (irqbalance_disabled)
679 /* disable irqbalance completely if there is only one processor online */
680 if (num_online_cpus() < 2) {
681 irqbalance_disabled = 1;
685 * Enable physical balance only if more than 1 physical processor
688 if (smp_num_siblings > 1 && !cpus_empty(tmp))
689 physical_balance = 1;
691 for_each_online_cpu(i) {
692 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
693 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
694 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
695 printk(KERN_ERR "balanced_irq_init: out of memory");
698 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
699 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
702 printk(KERN_INFO "Starting balanced_irq\n");
703 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
705 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
707 for_each_possible_cpu(i) {
708 kfree(irq_cpu_data[i].irq_delta);
709 irq_cpu_data[i].irq_delta = NULL;
710 kfree(irq_cpu_data[i].last_irq);
711 irq_cpu_data[i].last_irq = NULL;
716 int __devinit irqbalance_disable(char *str)
718 irqbalance_disabled = 1;
722 __setup("noirqbalance", irqbalance_disable);
724 late_initcall(balanced_irq_init);
725 #endif /* CONFIG_IRQBALANCE */
726 #endif /* CONFIG_SMP */
729 void send_IPI_self(int vector)
736 apic_wait_icr_idle();
737 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
739 * Send the IPI. The write to APIC_ICR fires this off.
741 apic_write_around(APIC_ICR, cfg);
743 #endif /* !CONFIG_SMP */
747 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
748 * specific CPU-side IRQs.
752 static int pirq_entries [MAX_PIRQS];
753 static int pirqs_enabled;
754 int skip_ioapic_setup;
756 static int __init ioapic_pirq_setup(char *str)
759 int ints[MAX_PIRQS+1];
761 get_options(str, ARRAY_SIZE(ints), ints);
763 for (i = 0; i < MAX_PIRQS; i++)
764 pirq_entries[i] = -1;
767 apic_printk(APIC_VERBOSE, KERN_INFO
768 "PIRQ redirection, working around broken MP-BIOS.\n");
770 if (ints[0] < MAX_PIRQS)
773 for (i = 0; i < max; i++) {
774 apic_printk(APIC_VERBOSE, KERN_DEBUG
775 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
777 * PIRQs are mapped upside down, usually.
779 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
784 __setup("pirq=", ioapic_pirq_setup);
787 * Find the IRQ entry number of a certain pin.
789 static int find_irq_entry(int apic, int pin, int type)
793 for (i = 0; i < mp_irq_entries; i++)
794 if (mp_irqs[i].mpc_irqtype == type &&
795 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
796 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
797 mp_irqs[i].mpc_dstirq == pin)
804 * Find the pin to which IRQ[irq] (ISA) is connected
806 static int __init find_isa_irq_pin(int irq, int type)
810 for (i = 0; i < mp_irq_entries; i++) {
811 int lbus = mp_irqs[i].mpc_srcbus;
813 if (test_bit(lbus, mp_bus_not_pci) &&
814 (mp_irqs[i].mpc_irqtype == type) &&
815 (mp_irqs[i].mpc_srcbusirq == irq))
817 return mp_irqs[i].mpc_dstirq;
822 static int __init find_isa_irq_apic(int irq, int type)
826 for (i = 0; i < mp_irq_entries; i++) {
827 int lbus = mp_irqs[i].mpc_srcbus;
829 if (test_bit(lbus, mp_bus_not_pci) &&
830 (mp_irqs[i].mpc_irqtype == type) &&
831 (mp_irqs[i].mpc_srcbusirq == irq))
834 if (i < mp_irq_entries) {
836 for(apic = 0; apic < nr_ioapics; apic++) {
837 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
846 * Find a specific PCI IRQ entry.
847 * Not an __init, possibly needed by modules
849 static int pin_2_irq(int idx, int apic, int pin);
851 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
853 int apic, i, best_guess = -1;
855 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
856 "slot:%d, pin:%d.\n", bus, slot, pin);
857 if (mp_bus_id_to_pci_bus[bus] == -1) {
858 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
861 for (i = 0; i < mp_irq_entries; i++) {
862 int lbus = mp_irqs[i].mpc_srcbus;
864 for (apic = 0; apic < nr_ioapics; apic++)
865 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
866 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
869 if (!test_bit(lbus, mp_bus_not_pci) &&
870 !mp_irqs[i].mpc_irqtype &&
872 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
873 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
875 if (!(apic || IO_APIC_IRQ(irq)))
878 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
881 * Use the first all-but-pin matching entry as a
882 * best-guess fuzzy result for broken mptables.
890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
893 * This function currently is only a helper for the i386 smp boot process where
894 * we need to reprogram the ioredtbls to cater for the cpus which have come online
895 * so mask in all cases should simply be TARGET_CPUS
898 void __init setup_ioapic_dest(void)
900 int pin, ioapic, irq, irq_entry;
902 if (skip_ioapic_setup == 1)
905 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
906 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
907 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
910 irq = pin_2_irq(irq_entry, ioapic, pin);
911 set_ioapic_affinity_irq(irq, TARGET_CPUS);
919 * EISA Edge/Level control register, ELCR
921 static int EISA_ELCR(unsigned int irq)
924 unsigned int port = 0x4d0 + (irq >> 3);
925 return (inb(port) >> (irq & 7)) & 1;
927 apic_printk(APIC_VERBOSE, KERN_INFO
928 "Broken MPtable reports ISA irq %d\n", irq);
932 /* ISA interrupts are always polarity zero edge triggered,
933 * when listed as conforming in the MP table. */
935 #define default_ISA_trigger(idx) (0)
936 #define default_ISA_polarity(idx) (0)
938 /* EISA interrupts are always polarity zero and can be edge or level
939 * trigger depending on the ELCR value. If an interrupt is listed as
940 * EISA conforming in the MP table, that means its trigger type must
941 * be read in from the ELCR */
943 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
944 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
946 /* PCI interrupts are always polarity one level triggered,
947 * when listed as conforming in the MP table. */
949 #define default_PCI_trigger(idx) (1)
950 #define default_PCI_polarity(idx) (1)
952 /* MCA interrupts are always polarity zero level triggered,
953 * when listed as conforming in the MP table. */
955 #define default_MCA_trigger(idx) (1)
956 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
958 static int MPBIOS_polarity(int idx)
960 int bus = mp_irqs[idx].mpc_srcbus;
964 * Determine IRQ line polarity (high active or low active):
966 switch (mp_irqs[idx].mpc_irqflag & 3)
968 case 0: /* conforms, ie. bus-type dependent polarity */
970 polarity = test_bit(bus, mp_bus_not_pci)?
971 default_ISA_polarity(idx):
972 default_PCI_polarity(idx);
975 case 1: /* high active */
980 case 2: /* reserved */
982 printk(KERN_WARNING "broken BIOS!!\n");
986 case 3: /* low active */
991 default: /* invalid */
993 printk(KERN_WARNING "broken BIOS!!\n");
1001 static int MPBIOS_trigger(int idx)
1003 int bus = mp_irqs[idx].mpc_srcbus;
1007 * Determine IRQ trigger mode (edge or level sensitive):
1009 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1011 case 0: /* conforms, ie. bus-type dependent */
1013 trigger = test_bit(bus, mp_bus_not_pci)?
1014 default_ISA_trigger(idx):
1015 default_PCI_trigger(idx);
1016 switch (mp_bus_id_to_type[bus])
1018 case MP_BUS_ISA: /* ISA pin */
1020 /* set before the switch */
1023 case MP_BUS_EISA: /* EISA pin */
1025 trigger = default_EISA_trigger(idx);
1028 case MP_BUS_PCI: /* PCI pin */
1030 /* set before the switch */
1033 case MP_BUS_MCA: /* MCA pin */
1035 trigger = default_MCA_trigger(idx);
1040 printk(KERN_WARNING "broken BIOS!!\n");
1052 case 2: /* reserved */
1054 printk(KERN_WARNING "broken BIOS!!\n");
1063 default: /* invalid */
1065 printk(KERN_WARNING "broken BIOS!!\n");
1073 static inline int irq_polarity(int idx)
1075 return MPBIOS_polarity(idx);
1078 static inline int irq_trigger(int idx)
1080 return MPBIOS_trigger(idx);
1083 static int pin_2_irq(int idx, int apic, int pin)
1086 int bus = mp_irqs[idx].mpc_srcbus;
1089 * Debugging check, we are in big trouble if this message pops up!
1091 if (mp_irqs[idx].mpc_dstirq != pin)
1092 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1094 switch (mp_bus_id_to_type[bus])
1096 case MP_BUS_ISA: /* ISA pin */
1100 irq = mp_irqs[idx].mpc_srcbusirq;
1103 case MP_BUS_PCI: /* PCI pin */
1106 * PCI IRQs are mapped in order
1110 irq += nr_ioapic_registers[i++];
1114 * For MPS mode, so far only needed by ES7000 platform
1116 if (ioapic_renumber_irq)
1117 irq = ioapic_renumber_irq(apic, irq);
1123 printk(KERN_ERR "unknown bus type %d.\n",bus);
1130 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1132 if ((pin >= 16) && (pin <= 23)) {
1133 if (pirq_entries[pin-16] != -1) {
1134 if (!pirq_entries[pin-16]) {
1135 apic_printk(APIC_VERBOSE, KERN_DEBUG
1136 "disabling PIRQ%d\n", pin-16);
1138 irq = pirq_entries[pin-16];
1139 apic_printk(APIC_VERBOSE, KERN_DEBUG
1140 "using PIRQ%d -> IRQ %d\n",
1148 static inline int IO_APIC_irq_trigger(int irq)
1152 for (apic = 0; apic < nr_ioapics; apic++) {
1153 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1154 idx = find_irq_entry(apic,pin,mp_INT);
1155 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1156 return irq_trigger(idx);
1160 * nonexistent IRQs are edge default
1165 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1166 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1168 static int __assign_irq_vector(int irq)
1170 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1173 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1175 if (irq_vector[irq] > 0)
1176 return irq_vector[irq];
1178 vector = current_vector;
1179 offset = current_offset;
1182 if (vector >= FIRST_SYSTEM_VECTOR) {
1183 offset = (offset + 1) % 8;
1184 vector = FIRST_DEVICE_VECTOR + offset;
1186 if (vector == current_vector)
1188 if (test_and_set_bit(vector, used_vectors))
1191 current_vector = vector;
1192 current_offset = offset;
1193 irq_vector[irq] = vector;
1198 static int assign_irq_vector(int irq)
1200 unsigned long flags;
1203 spin_lock_irqsave(&vector_lock, flags);
1204 vector = __assign_irq_vector(irq);
1205 spin_unlock_irqrestore(&vector_lock, flags);
1209 static struct irq_chip ioapic_chip;
1211 #define IOAPIC_AUTO -1
1212 #define IOAPIC_EDGE 0
1213 #define IOAPIC_LEVEL 1
1215 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1217 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1218 trigger == IOAPIC_LEVEL) {
1219 irq_desc[irq].status |= IRQ_LEVEL;
1220 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1221 handle_fasteoi_irq, "fasteoi");
1223 irq_desc[irq].status &= ~IRQ_LEVEL;
1224 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1225 handle_edge_irq, "edge");
1227 set_intr_gate(vector, interrupt[irq]);
1230 static void __init setup_IO_APIC_irqs(void)
1232 struct IO_APIC_route_entry entry;
1233 int apic, pin, idx, irq, first_notcon = 1, vector;
1234 unsigned long flags;
1236 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1238 for (apic = 0; apic < nr_ioapics; apic++) {
1239 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1242 * add it to the IO-APIC irq-routing table:
1244 memset(&entry,0,sizeof(entry));
1246 entry.delivery_mode = INT_DELIVERY_MODE;
1247 entry.dest_mode = INT_DEST_MODE;
1248 entry.mask = 0; /* enable IRQ */
1249 entry.dest.logical.logical_dest =
1250 cpu_mask_to_apicid(TARGET_CPUS);
1252 idx = find_irq_entry(apic,pin,mp_INT);
1255 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256 " IO-APIC (apicid-pin) %d-%d",
1257 mp_ioapics[apic].mpc_apicid,
1261 apic_printk(APIC_VERBOSE, ", %d-%d",
1262 mp_ioapics[apic].mpc_apicid, pin);
1266 if (!first_notcon) {
1267 apic_printk(APIC_VERBOSE, " not connected.\n");
1271 entry.trigger = irq_trigger(idx);
1272 entry.polarity = irq_polarity(idx);
1274 if (irq_trigger(idx)) {
1279 irq = pin_2_irq(idx, apic, pin);
1281 * skip adding the timer int on secondary nodes, which causes
1282 * a small but painful rift in the time-space continuum
1284 if (multi_timer_check(apic, irq))
1287 add_pin_to_irq(irq, apic, pin);
1289 if (!apic && !IO_APIC_IRQ(irq))
1292 if (IO_APIC_IRQ(irq)) {
1293 vector = assign_irq_vector(irq);
1294 entry.vector = vector;
1295 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1297 if (!apic && (irq < 16))
1298 disable_8259A_irq(irq);
1300 spin_lock_irqsave(&ioapic_lock, flags);
1301 __ioapic_write_entry(apic, pin, entry);
1302 spin_unlock_irqrestore(&ioapic_lock, flags);
1307 apic_printk(APIC_VERBOSE, " not connected.\n");
1311 * Set up the 8259A-master output pin:
1313 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1315 struct IO_APIC_route_entry entry;
1317 memset(&entry,0,sizeof(entry));
1319 disable_8259A_irq(0);
1322 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1325 * We use logical delivery to get the timer IRQ
1328 entry.dest_mode = INT_DEST_MODE;
1329 entry.mask = 0; /* unmask IRQ now */
1330 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1331 entry.delivery_mode = INT_DELIVERY_MODE;
1334 entry.vector = vector;
1337 * The timer IRQ doesn't have to know that behind the
1338 * scene we have a 8259A-master in AEOI mode ...
1340 irq_desc[0].chip = &ioapic_chip;
1341 set_irq_handler(0, handle_edge_irq);
1344 * Add it to the IO-APIC irq-routing table:
1346 ioapic_write_entry(apic, pin, entry);
1348 enable_8259A_irq(0);
1351 void __init print_IO_APIC(void)
1354 union IO_APIC_reg_00 reg_00;
1355 union IO_APIC_reg_01 reg_01;
1356 union IO_APIC_reg_02 reg_02;
1357 union IO_APIC_reg_03 reg_03;
1358 unsigned long flags;
1360 if (apic_verbosity == APIC_QUIET)
1363 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1364 for (i = 0; i < nr_ioapics; i++)
1365 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1366 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1369 * We are a bit conservative about what we expect. We have to
1370 * know about every hardware change ASAP.
1372 printk(KERN_INFO "testing the IO APIC.......................\n");
1374 for (apic = 0; apic < nr_ioapics; apic++) {
1376 spin_lock_irqsave(&ioapic_lock, flags);
1377 reg_00.raw = io_apic_read(apic, 0);
1378 reg_01.raw = io_apic_read(apic, 1);
1379 if (reg_01.bits.version >= 0x10)
1380 reg_02.raw = io_apic_read(apic, 2);
1381 if (reg_01.bits.version >= 0x20)
1382 reg_03.raw = io_apic_read(apic, 3);
1383 spin_unlock_irqrestore(&ioapic_lock, flags);
1385 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1386 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1387 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1388 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1389 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1391 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1392 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1394 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1395 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1398 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1399 * but the value of reg_02 is read as the previous read register
1400 * value, so ignore it if reg_02 == reg_01.
1402 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1403 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1404 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1408 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1409 * or reg_03, but the value of reg_0[23] is read as the previous read
1410 * register value, so ignore it if reg_03 == reg_0[12].
1412 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1413 reg_03.raw != reg_01.raw) {
1414 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1415 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1418 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1420 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1421 " Stat Dest Deli Vect: \n");
1423 for (i = 0; i <= reg_01.bits.entries; i++) {
1424 struct IO_APIC_route_entry entry;
1426 entry = ioapic_read_entry(apic, i);
1428 printk(KERN_DEBUG " %02x %03X %02X ",
1430 entry.dest.logical.logical_dest,
1431 entry.dest.physical.physical_dest
1434 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1439 entry.delivery_status,
1441 entry.delivery_mode,
1446 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1447 for (i = 0; i < NR_IRQS; i++) {
1448 struct irq_pin_list *entry = irq_2_pin + i;
1451 printk(KERN_DEBUG "IRQ%d ", i);
1453 printk("-> %d:%d", entry->apic, entry->pin);
1456 entry = irq_2_pin + entry->next;
1461 printk(KERN_INFO ".................................... done.\n");
1468 static void print_APIC_bitfield (int base)
1473 if (apic_verbosity == APIC_QUIET)
1476 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1477 for (i = 0; i < 8; i++) {
1478 v = apic_read(base + i*0x10);
1479 for (j = 0; j < 32; j++) {
1489 void /*__init*/ print_local_APIC(void * dummy)
1491 unsigned int v, ver, maxlvt;
1493 if (apic_verbosity == APIC_QUIET)
1496 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1497 smp_processor_id(), hard_smp_processor_id());
1498 v = apic_read(APIC_ID);
1499 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1500 v = apic_read(APIC_LVR);
1501 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1502 ver = GET_APIC_VERSION(v);
1503 maxlvt = lapic_get_maxlvt();
1505 v = apic_read(APIC_TASKPRI);
1506 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1508 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1509 v = apic_read(APIC_ARBPRI);
1510 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1511 v & APIC_ARBPRI_MASK);
1512 v = apic_read(APIC_PROCPRI);
1513 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1516 v = apic_read(APIC_EOI);
1517 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1518 v = apic_read(APIC_RRR);
1519 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1520 v = apic_read(APIC_LDR);
1521 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1522 v = apic_read(APIC_DFR);
1523 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1524 v = apic_read(APIC_SPIV);
1525 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1527 printk(KERN_DEBUG "... APIC ISR field:\n");
1528 print_APIC_bitfield(APIC_ISR);
1529 printk(KERN_DEBUG "... APIC TMR field:\n");
1530 print_APIC_bitfield(APIC_TMR);
1531 printk(KERN_DEBUG "... APIC IRR field:\n");
1532 print_APIC_bitfield(APIC_IRR);
1534 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1535 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1536 apic_write(APIC_ESR, 0);
1537 v = apic_read(APIC_ESR);
1538 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1541 v = apic_read(APIC_ICR);
1542 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1543 v = apic_read(APIC_ICR2);
1544 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1546 v = apic_read(APIC_LVTT);
1547 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1549 if (maxlvt > 3) { /* PC is LVT#4. */
1550 v = apic_read(APIC_LVTPC);
1551 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1553 v = apic_read(APIC_LVT0);
1554 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1555 v = apic_read(APIC_LVT1);
1556 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1558 if (maxlvt > 2) { /* ERR is LVT#3. */
1559 v = apic_read(APIC_LVTERR);
1560 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1563 v = apic_read(APIC_TMICT);
1564 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1565 v = apic_read(APIC_TMCCT);
1566 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1567 v = apic_read(APIC_TDCR);
1568 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1572 void print_all_local_APICs (void)
1574 on_each_cpu(print_local_APIC, NULL, 1, 1);
1577 void /*__init*/ print_PIC(void)
1580 unsigned long flags;
1582 if (apic_verbosity == APIC_QUIET)
1585 printk(KERN_DEBUG "\nprinting PIC contents\n");
1587 spin_lock_irqsave(&i8259A_lock, flags);
1589 v = inb(0xa1) << 8 | inb(0x21);
1590 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1592 v = inb(0xa0) << 8 | inb(0x20);
1593 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1597 v = inb(0xa0) << 8 | inb(0x20);
1601 spin_unlock_irqrestore(&i8259A_lock, flags);
1603 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1605 v = inb(0x4d1) << 8 | inb(0x4d0);
1606 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1611 static void __init enable_IO_APIC(void)
1613 union IO_APIC_reg_01 reg_01;
1614 int i8259_apic, i8259_pin;
1616 unsigned long flags;
1618 for (i = 0; i < PIN_MAP_SIZE; i++) {
1619 irq_2_pin[i].pin = -1;
1620 irq_2_pin[i].next = 0;
1623 for (i = 0; i < MAX_PIRQS; i++)
1624 pirq_entries[i] = -1;
1627 * The number of IO-APIC IRQ registers (== #pins):
1629 for (apic = 0; apic < nr_ioapics; apic++) {
1630 spin_lock_irqsave(&ioapic_lock, flags);
1631 reg_01.raw = io_apic_read(apic, 1);
1632 spin_unlock_irqrestore(&ioapic_lock, flags);
1633 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1635 for(apic = 0; apic < nr_ioapics; apic++) {
1637 /* See if any of the pins is in ExtINT mode */
1638 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1639 struct IO_APIC_route_entry entry;
1640 entry = ioapic_read_entry(apic, pin);
1643 /* If the interrupt line is enabled and in ExtInt mode
1644 * I have found the pin where the i8259 is connected.
1646 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1647 ioapic_i8259.apic = apic;
1648 ioapic_i8259.pin = pin;
1654 /* Look to see what if the MP table has reported the ExtINT */
1655 /* If we could not find the appropriate pin by looking at the ioapic
1656 * the i8259 probably is not connected the ioapic but give the
1657 * mptable a chance anyway.
1659 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1660 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1661 /* Trust the MP table if nothing is setup in the hardware */
1662 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1663 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1664 ioapic_i8259.pin = i8259_pin;
1665 ioapic_i8259.apic = i8259_apic;
1667 /* Complain if the MP table and the hardware disagree */
1668 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1669 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1671 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1675 * Do not trust the IO-APIC being empty at bootup
1681 * Not an __init, needed by the reboot code
1683 void disable_IO_APIC(void)
1686 * Clear the IO-APIC before rebooting:
1691 * If the i8259 is routed through an IOAPIC
1692 * Put that IOAPIC in virtual wire mode
1693 * so legacy interrupts can be delivered.
1695 if (ioapic_i8259.pin != -1) {
1696 struct IO_APIC_route_entry entry;
1698 memset(&entry, 0, sizeof(entry));
1699 entry.mask = 0; /* Enabled */
1700 entry.trigger = 0; /* Edge */
1702 entry.polarity = 0; /* High */
1703 entry.delivery_status = 0;
1704 entry.dest_mode = 0; /* Physical */
1705 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1707 entry.dest.physical.physical_dest =
1708 GET_APIC_ID(apic_read(APIC_ID));
1711 * Add it to the IO-APIC irq-routing table:
1713 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1715 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1719 * function to set the IO-APIC physical IDs based on the
1720 * values stored in the MPC table.
1722 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1725 #ifndef CONFIG_X86_NUMAQ
1726 static void __init setup_ioapic_ids_from_mpc(void)
1728 union IO_APIC_reg_00 reg_00;
1729 physid_mask_t phys_id_present_map;
1732 unsigned char old_id;
1733 unsigned long flags;
1736 * Don't check I/O APIC IDs for xAPIC systems. They have
1737 * no meaning without the serial APIC bus.
1739 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1740 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1743 * This is broken; anything with a real cpu count has to
1744 * circumvent this idiocy regardless.
1746 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1749 * Set the IOAPIC ID to the value stored in the MPC table.
1751 for (apic = 0; apic < nr_ioapics; apic++) {
1753 /* Read the register 0 value */
1754 spin_lock_irqsave(&ioapic_lock, flags);
1755 reg_00.raw = io_apic_read(apic, 0);
1756 spin_unlock_irqrestore(&ioapic_lock, flags);
1758 old_id = mp_ioapics[apic].mpc_apicid;
1760 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1761 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1762 apic, mp_ioapics[apic].mpc_apicid);
1763 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1765 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1769 * Sanity check, is the ID really free? Every APIC in a
1770 * system must have a unique ID or we get lots of nice
1771 * 'stuck on smp_invalidate_needed IPI wait' messages.
1773 if (check_apicid_used(phys_id_present_map,
1774 mp_ioapics[apic].mpc_apicid)) {
1775 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1776 apic, mp_ioapics[apic].mpc_apicid);
1777 for (i = 0; i < get_physical_broadcast(); i++)
1778 if (!physid_isset(i, phys_id_present_map))
1780 if (i >= get_physical_broadcast())
1781 panic("Max APIC ID exceeded!\n");
1782 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1784 physid_set(i, phys_id_present_map);
1785 mp_ioapics[apic].mpc_apicid = i;
1788 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1789 apic_printk(APIC_VERBOSE, "Setting %d in the "
1790 "phys_id_present_map\n",
1791 mp_ioapics[apic].mpc_apicid);
1792 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1797 * We need to adjust the IRQ routing table
1798 * if the ID changed.
1800 if (old_id != mp_ioapics[apic].mpc_apicid)
1801 for (i = 0; i < mp_irq_entries; i++)
1802 if (mp_irqs[i].mpc_dstapic == old_id)
1803 mp_irqs[i].mpc_dstapic
1804 = mp_ioapics[apic].mpc_apicid;
1807 * Read the right value from the MPC table and
1808 * write it into the ID register.
1810 apic_printk(APIC_VERBOSE, KERN_INFO
1811 "...changing IO-APIC physical APIC ID to %d ...",
1812 mp_ioapics[apic].mpc_apicid);
1814 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1815 spin_lock_irqsave(&ioapic_lock, flags);
1816 io_apic_write(apic, 0, reg_00.raw);
1817 spin_unlock_irqrestore(&ioapic_lock, flags);
1822 spin_lock_irqsave(&ioapic_lock, flags);
1823 reg_00.raw = io_apic_read(apic, 0);
1824 spin_unlock_irqrestore(&ioapic_lock, flags);
1825 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1826 printk("could not set ID!\n");
1828 apic_printk(APIC_VERBOSE, " ok.\n");
1832 static void __init setup_ioapic_ids_from_mpc(void) { }
1835 int no_timer_check __initdata;
1837 static int __init notimercheck(char *s)
1842 __setup("no_timer_check", notimercheck);
1845 * There is a nasty bug in some older SMP boards, their mptable lies
1846 * about the timer IRQ. We do the following to work around the situation:
1848 * - timer IRQ defaults to IO-APIC IRQ
1849 * - if this function detects that timer IRQs are defunct, then we fall
1850 * back to ISA timer IRQs
1852 static int __init timer_irq_works(void)
1854 unsigned long t1 = jiffies;
1855 unsigned long flags;
1860 local_save_flags(flags);
1862 /* Let ten ticks pass... */
1863 mdelay((10 * 1000) / HZ);
1864 local_irq_restore(flags);
1867 * Expect a few ticks at least, to be sure some possible
1868 * glue logic does not lock up after one or two first
1869 * ticks in a non-ExtINT mode. Also the local APIC
1870 * might have cached one ExtINT interrupt. Finally, at
1871 * least one tick may be lost due to delays.
1873 if (time_after(jiffies, t1 + 4))
1880 * In the SMP+IOAPIC case it might happen that there are an unspecified
1881 * number of pending IRQ events unhandled. These cases are very rare,
1882 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1883 * better to do it this way as thus we do not have to be aware of
1884 * 'pending' interrupts in the IRQ path, except at this point.
1887 * Edge triggered needs to resend any interrupt
1888 * that was delayed but this is now handled in the device
1895 * Starting up a edge-triggered IO-APIC interrupt is
1896 * nasty - we need to make sure that we get the edge.
1897 * If it is already asserted for some reason, we need
1898 * return 1 to indicate that is was pending.
1900 * This is not complete - we should be able to fake
1901 * an edge even if it isn't on the 8259A...
1903 * (We do this for level-triggered IRQs too - it cannot hurt.)
1905 static unsigned int startup_ioapic_irq(unsigned int irq)
1907 int was_pending = 0;
1908 unsigned long flags;
1910 spin_lock_irqsave(&ioapic_lock, flags);
1912 disable_8259A_irq(irq);
1913 if (i8259A_irq_pending(irq))
1916 __unmask_IO_APIC_irq(irq);
1917 spin_unlock_irqrestore(&ioapic_lock, flags);
1922 static void ack_ioapic_irq(unsigned int irq)
1924 move_native_irq(irq);
1928 static void ack_ioapic_quirk_irq(unsigned int irq)
1933 move_native_irq(irq);
1935 * It appears there is an erratum which affects at least version 0x11
1936 * of I/O APIC (that's the 82093AA and cores integrated into various
1937 * chipsets). Under certain conditions a level-triggered interrupt is
1938 * erroneously delivered as edge-triggered one but the respective IRR
1939 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1940 * message but it will never arrive and further interrupts are blocked
1941 * from the source. The exact reason is so far unknown, but the
1942 * phenomenon was observed when two consecutive interrupt requests
1943 * from a given source get delivered to the same CPU and the source is
1944 * temporarily disabled in between.
1946 * A workaround is to simulate an EOI message manually. We achieve it
1947 * by setting the trigger mode to edge and then to level when the edge
1948 * trigger mode gets detected in the TMR of a local APIC for a
1949 * level-triggered interrupt. We mask the source for the time of the
1950 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1951 * The idea is from Manfred Spraul. --macro
1953 i = irq_vector[irq];
1955 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1959 if (!(v & (1 << (i & 0x1f)))) {
1960 atomic_inc(&irq_mis_count);
1961 spin_lock(&ioapic_lock);
1962 __mask_and_edge_IO_APIC_irq(irq);
1963 __unmask_and_level_IO_APIC_irq(irq);
1964 spin_unlock(&ioapic_lock);
1968 static int ioapic_retrigger_irq(unsigned int irq)
1970 send_IPI_self(irq_vector[irq]);
1975 static struct irq_chip ioapic_chip __read_mostly = {
1977 .startup = startup_ioapic_irq,
1978 .mask = mask_IO_APIC_irq,
1979 .unmask = unmask_IO_APIC_irq,
1980 .ack = ack_ioapic_irq,
1981 .eoi = ack_ioapic_quirk_irq,
1983 .set_affinity = set_ioapic_affinity_irq,
1985 .retrigger = ioapic_retrigger_irq,
1989 static inline void init_IO_APIC_traps(void)
1994 * NOTE! The local APIC isn't very good at handling
1995 * multiple interrupts at the same interrupt level.
1996 * As the interrupt level is determined by taking the
1997 * vector number and shifting that right by 4, we
1998 * want to spread these out a bit so that they don't
1999 * all fall in the same interrupt level.
2001 * Also, we've got to be careful not to trash gate
2002 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2004 for (irq = 0; irq < NR_IRQS ; irq++) {
2006 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2008 * Hmm.. We don't have an entry for this,
2009 * so default to an old-fashioned 8259
2010 * interrupt if we can..
2013 make_8259A_irq(irq);
2015 /* Strange. Oh, well.. */
2016 irq_desc[irq].chip = &no_irq_chip;
2022 * The local APIC irq-chip implementation:
2025 static void ack_apic(unsigned int irq)
2030 static void mask_lapic_irq (unsigned int irq)
2034 v = apic_read(APIC_LVT0);
2035 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2038 static void unmask_lapic_irq (unsigned int irq)
2042 v = apic_read(APIC_LVT0);
2043 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2046 static struct irq_chip lapic_chip __read_mostly = {
2047 .name = "local-APIC-edge",
2048 .mask = mask_lapic_irq,
2049 .unmask = unmask_lapic_irq,
2053 static void __init setup_nmi(void)
2056 * Dirty trick to enable the NMI watchdog ...
2057 * We put the 8259A master into AEOI mode and
2058 * unmask on all local APICs LVT0 as NMI.
2060 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2061 * is from Maciej W. Rozycki - so we do not have to EOI from
2062 * the NMI handler or the timer interrupt.
2064 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2066 enable_NMI_through_LVT0();
2068 apic_printk(APIC_VERBOSE, " done.\n");
2072 * This looks a bit hackish but it's about the only one way of sending
2073 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2074 * not support the ExtINT mode, unfortunately. We need to send these
2075 * cycles as some i82489DX-based boards have glue logic that keeps the
2076 * 8259A interrupt line asserted until INTA. --macro
2078 static inline void unlock_ExtINT_logic(void)
2081 struct IO_APIC_route_entry entry0, entry1;
2082 unsigned char save_control, save_freq_select;
2084 pin = find_isa_irq_pin(8, mp_INT);
2089 apic = find_isa_irq_apic(8, mp_INT);
2095 entry0 = ioapic_read_entry(apic, pin);
2096 clear_IO_APIC_pin(apic, pin);
2098 memset(&entry1, 0, sizeof(entry1));
2100 entry1.dest_mode = 0; /* physical delivery */
2101 entry1.mask = 0; /* unmask IRQ now */
2102 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2103 entry1.delivery_mode = dest_ExtINT;
2104 entry1.polarity = entry0.polarity;
2108 ioapic_write_entry(apic, pin, entry1);
2110 save_control = CMOS_READ(RTC_CONTROL);
2111 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2112 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2114 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2119 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2123 CMOS_WRITE(save_control, RTC_CONTROL);
2124 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2125 clear_IO_APIC_pin(apic, pin);
2127 ioapic_write_entry(apic, pin, entry0);
2130 int timer_uses_ioapic_pin_0;
2133 * This code may look a bit paranoid, but it's supposed to cooperate with
2134 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2135 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2136 * fanatically on his truly buggy board.
2138 static inline void __init check_timer(void)
2140 int apic1, pin1, apic2, pin2;
2142 unsigned long flags;
2144 local_irq_save(flags);
2147 * get/set the timer IRQ vector:
2149 disable_8259A_irq(0);
2150 vector = assign_irq_vector(0);
2151 set_intr_gate(vector, interrupt[0]);
2154 * Subtle, code in do_timer_interrupt() expects an AEOI
2155 * mode for the 8259A whenever interrupts are routed
2156 * through I/O APICs. Also IRQ0 has to be enabled in
2157 * the 8259A which implies the virtual wire has to be
2158 * disabled in the local APIC.
2160 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2163 if (timer_over_8254 > 0)
2164 enable_8259A_irq(0);
2166 pin1 = find_isa_irq_pin(0, mp_INT);
2167 apic1 = find_isa_irq_apic(0, mp_INT);
2168 pin2 = ioapic_i8259.pin;
2169 apic2 = ioapic_i8259.apic;
2172 timer_uses_ioapic_pin_0 = 1;
2174 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2175 vector, apic1, pin1, apic2, pin2);
2179 * Ok, does IRQ0 through the IOAPIC work?
2181 unmask_IO_APIC_irq(0);
2182 if (timer_irq_works()) {
2183 if (nmi_watchdog == NMI_IO_APIC) {
2184 disable_8259A_irq(0);
2186 enable_8259A_irq(0);
2188 if (disable_timer_pin_1 > 0)
2189 clear_IO_APIC_pin(0, pin1);
2192 clear_IO_APIC_pin(apic1, pin1);
2193 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2197 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2199 printk("\n..... (found pin %d) ...", pin2);
2201 * legacy devices should be connected to IO APIC #0
2203 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2204 if (timer_irq_works()) {
2207 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2209 add_pin_to_irq(0, apic2, pin2);
2210 if (nmi_watchdog == NMI_IO_APIC) {
2216 * Cleanup, just in case ...
2218 clear_IO_APIC_pin(apic2, pin2);
2220 printk(" failed.\n");
2222 if (nmi_watchdog == NMI_IO_APIC) {
2223 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2227 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2229 disable_8259A_irq(0);
2230 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2232 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2233 enable_8259A_irq(0);
2235 if (timer_irq_works()) {
2236 printk(" works.\n");
2239 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2240 printk(" failed.\n");
2242 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2247 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2249 unlock_ExtINT_logic();
2251 if (timer_irq_works()) {
2252 printk(" works.\n");
2255 printk(" failed :(.\n");
2256 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2257 "report. Then try booting with the 'noapic' option");
2259 local_irq_restore(flags);
2264 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2265 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2266 * Linux doesn't really care, as it's not actually used
2267 * for any interrupt handling anyway.
2269 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2271 void __init setup_IO_APIC(void)
2275 /* Reserve all the system vectors. */
2276 for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2277 set_bit(i, used_vectors);
2282 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2284 io_apic_irqs = ~PIC_IRQS;
2286 printk("ENABLING IO-APIC IRQs\n");
2289 * Set up IO-APIC IRQ routing.
2292 setup_ioapic_ids_from_mpc();
2294 setup_IO_APIC_irqs();
2295 init_IO_APIC_traps();
2301 static int __init setup_disable_8254_timer(char *s)
2303 timer_over_8254 = -1;
2306 static int __init setup_enable_8254_timer(char *s)
2308 timer_over_8254 = 2;
2312 __setup("disable_8254_timer", setup_disable_8254_timer);
2313 __setup("enable_8254_timer", setup_enable_8254_timer);
2316 * Called after all the initialization is done. If we didnt find any
2317 * APIC bugs then we can allow the modify fast path
2320 static int __init io_apic_bug_finalize(void)
2322 if(sis_apic_bug == -1)
2327 late_initcall(io_apic_bug_finalize);
2329 struct sysfs_ioapic_data {
2330 struct sys_device dev;
2331 struct IO_APIC_route_entry entry[0];
2333 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2335 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2337 struct IO_APIC_route_entry *entry;
2338 struct sysfs_ioapic_data *data;
2341 data = container_of(dev, struct sysfs_ioapic_data, dev);
2342 entry = data->entry;
2343 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2344 entry[i] = ioapic_read_entry(dev->id, i);
2349 static int ioapic_resume(struct sys_device *dev)
2351 struct IO_APIC_route_entry *entry;
2352 struct sysfs_ioapic_data *data;
2353 unsigned long flags;
2354 union IO_APIC_reg_00 reg_00;
2357 data = container_of(dev, struct sysfs_ioapic_data, dev);
2358 entry = data->entry;
2360 spin_lock_irqsave(&ioapic_lock, flags);
2361 reg_00.raw = io_apic_read(dev->id, 0);
2362 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2363 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2364 io_apic_write(dev->id, 0, reg_00.raw);
2366 spin_unlock_irqrestore(&ioapic_lock, flags);
2367 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2368 ioapic_write_entry(dev->id, i, entry[i]);
2373 static struct sysdev_class ioapic_sysdev_class = {
2375 .suspend = ioapic_suspend,
2376 .resume = ioapic_resume,
2379 static int __init ioapic_init_sysfs(void)
2381 struct sys_device * dev;
2382 int i, size, error = 0;
2384 error = sysdev_class_register(&ioapic_sysdev_class);
2388 for (i = 0; i < nr_ioapics; i++ ) {
2389 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2390 * sizeof(struct IO_APIC_route_entry);
2391 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2392 if (!mp_ioapic_data[i]) {
2393 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2396 memset(mp_ioapic_data[i], 0, size);
2397 dev = &mp_ioapic_data[i]->dev;
2399 dev->cls = &ioapic_sysdev_class;
2400 error = sysdev_register(dev);
2402 kfree(mp_ioapic_data[i]);
2403 mp_ioapic_data[i] = NULL;
2404 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2412 device_initcall(ioapic_init_sysfs);
2415 * Dynamic irq allocate and deallocation
2417 int create_irq(void)
2419 /* Allocate an unused irq */
2420 int irq, new, vector = 0;
2421 unsigned long flags;
2424 spin_lock_irqsave(&vector_lock, flags);
2425 for (new = (NR_IRQS - 1); new >= 0; new--) {
2426 if (platform_legacy_irq(new))
2428 if (irq_vector[new] != 0)
2430 vector = __assign_irq_vector(new);
2431 if (likely(vector > 0))
2435 spin_unlock_irqrestore(&vector_lock, flags);
2438 set_intr_gate(vector, interrupt[irq]);
2439 dynamic_irq_init(irq);
2444 void destroy_irq(unsigned int irq)
2446 unsigned long flags;
2448 dynamic_irq_cleanup(irq);
2450 spin_lock_irqsave(&vector_lock, flags);
2451 irq_vector[irq] = 0;
2452 spin_unlock_irqrestore(&vector_lock, flags);
2456 * MSI message composition
2458 #ifdef CONFIG_PCI_MSI
2459 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2464 vector = assign_irq_vector(irq);
2466 dest = cpu_mask_to_apicid(TARGET_CPUS);
2468 msg->address_hi = MSI_ADDR_BASE_HI;
2471 ((INT_DEST_MODE == 0) ?
2472 MSI_ADDR_DEST_MODE_PHYSICAL:
2473 MSI_ADDR_DEST_MODE_LOGICAL) |
2474 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2475 MSI_ADDR_REDIRECTION_CPU:
2476 MSI_ADDR_REDIRECTION_LOWPRI) |
2477 MSI_ADDR_DEST_ID(dest);
2480 MSI_DATA_TRIGGER_EDGE |
2481 MSI_DATA_LEVEL_ASSERT |
2482 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2483 MSI_DATA_DELIVERY_FIXED:
2484 MSI_DATA_DELIVERY_LOWPRI) |
2485 MSI_DATA_VECTOR(vector);
2491 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2498 cpus_and(tmp, mask, cpu_online_map);
2499 if (cpus_empty(tmp))
2502 vector = assign_irq_vector(irq);
2506 dest = cpu_mask_to_apicid(mask);
2508 read_msi_msg(irq, &msg);
2510 msg.data &= ~MSI_DATA_VECTOR_MASK;
2511 msg.data |= MSI_DATA_VECTOR(vector);
2512 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2513 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2515 write_msi_msg(irq, &msg);
2516 irq_desc[irq].affinity = mask;
2518 #endif /* CONFIG_SMP */
2521 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2522 * which implement the MSI or MSI-X Capability Structure.
2524 static struct irq_chip msi_chip = {
2526 .unmask = unmask_msi_irq,
2527 .mask = mask_msi_irq,
2528 .ack = ack_ioapic_irq,
2530 .set_affinity = set_msi_irq_affinity,
2532 .retrigger = ioapic_retrigger_irq,
2535 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2543 ret = msi_compose_msg(dev, irq, &msg);
2549 set_irq_msi(irq, desc);
2550 write_msi_msg(irq, &msg);
2552 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2558 void arch_teardown_msi_irq(unsigned int irq)
2563 #endif /* CONFIG_PCI_MSI */
2566 * Hypertransport interrupt support
2568 #ifdef CONFIG_HT_IRQ
2572 static void target_ht_irq(unsigned int irq, unsigned int dest)
2574 struct ht_irq_msg msg;
2575 fetch_ht_irq_msg(irq, &msg);
2577 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2578 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2580 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2581 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2583 write_ht_irq_msg(irq, &msg);
2586 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2591 cpus_and(tmp, mask, cpu_online_map);
2592 if (cpus_empty(tmp))
2595 cpus_and(mask, tmp, CPU_MASK_ALL);
2597 dest = cpu_mask_to_apicid(mask);
2599 target_ht_irq(irq, dest);
2600 irq_desc[irq].affinity = mask;
2604 static struct irq_chip ht_irq_chip = {
2606 .mask = mask_ht_irq,
2607 .unmask = unmask_ht_irq,
2608 .ack = ack_ioapic_irq,
2610 .set_affinity = set_ht_irq_affinity,
2612 .retrigger = ioapic_retrigger_irq,
2615 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2619 vector = assign_irq_vector(irq);
2621 struct ht_irq_msg msg;
2626 cpu_set(vector >> 8, tmp);
2627 dest = cpu_mask_to_apicid(tmp);
2629 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2633 HT_IRQ_LOW_DEST_ID(dest) |
2634 HT_IRQ_LOW_VECTOR(vector) |
2635 ((INT_DEST_MODE == 0) ?
2636 HT_IRQ_LOW_DM_PHYSICAL :
2637 HT_IRQ_LOW_DM_LOGICAL) |
2638 HT_IRQ_LOW_RQEOI_EDGE |
2639 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2640 HT_IRQ_LOW_MT_FIXED :
2641 HT_IRQ_LOW_MT_ARBITRATED) |
2642 HT_IRQ_LOW_IRQ_MASKED;
2644 write_ht_irq_msg(irq, &msg);
2646 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2647 handle_edge_irq, "edge");
2651 #endif /* CONFIG_HT_IRQ */
2653 /* --------------------------------------------------------------------------
2654 ACPI-based IOAPIC Configuration
2655 -------------------------------------------------------------------------- */
2659 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2661 union IO_APIC_reg_00 reg_00;
2662 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2664 unsigned long flags;
2668 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2669 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2670 * supports up to 16 on one shared APIC bus.
2672 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2673 * advantage of new APIC bus architecture.
2676 if (physids_empty(apic_id_map))
2677 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2679 spin_lock_irqsave(&ioapic_lock, flags);
2680 reg_00.raw = io_apic_read(ioapic, 0);
2681 spin_unlock_irqrestore(&ioapic_lock, flags);
2683 if (apic_id >= get_physical_broadcast()) {
2684 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2685 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2686 apic_id = reg_00.bits.ID;
2690 * Every APIC in a system must have a unique ID or we get lots of nice
2691 * 'stuck on smp_invalidate_needed IPI wait' messages.
2693 if (check_apicid_used(apic_id_map, apic_id)) {
2695 for (i = 0; i < get_physical_broadcast(); i++) {
2696 if (!check_apicid_used(apic_id_map, i))
2700 if (i == get_physical_broadcast())
2701 panic("Max apic_id exceeded!\n");
2703 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2704 "trying %d\n", ioapic, apic_id, i);
2709 tmp = apicid_to_cpu_present(apic_id);
2710 physids_or(apic_id_map, apic_id_map, tmp);
2712 if (reg_00.bits.ID != apic_id) {
2713 reg_00.bits.ID = apic_id;
2715 spin_lock_irqsave(&ioapic_lock, flags);
2716 io_apic_write(ioapic, 0, reg_00.raw);
2717 reg_00.raw = io_apic_read(ioapic, 0);
2718 spin_unlock_irqrestore(&ioapic_lock, flags);
2721 if (reg_00.bits.ID != apic_id) {
2722 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2727 apic_printk(APIC_VERBOSE, KERN_INFO
2728 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2734 int __init io_apic_get_version (int ioapic)
2736 union IO_APIC_reg_01 reg_01;
2737 unsigned long flags;
2739 spin_lock_irqsave(&ioapic_lock, flags);
2740 reg_01.raw = io_apic_read(ioapic, 1);
2741 spin_unlock_irqrestore(&ioapic_lock, flags);
2743 return reg_01.bits.version;
2747 int __init io_apic_get_redir_entries (int ioapic)
2749 union IO_APIC_reg_01 reg_01;
2750 unsigned long flags;
2752 spin_lock_irqsave(&ioapic_lock, flags);
2753 reg_01.raw = io_apic_read(ioapic, 1);
2754 spin_unlock_irqrestore(&ioapic_lock, flags);
2756 return reg_01.bits.entries;
2760 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2762 struct IO_APIC_route_entry entry;
2763 unsigned long flags;
2765 if (!IO_APIC_IRQ(irq)) {
2766 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2772 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2773 * Note that we mask (disable) IRQs now -- these get enabled when the
2774 * corresponding device driver registers for this IRQ.
2777 memset(&entry,0,sizeof(entry));
2779 entry.delivery_mode = INT_DELIVERY_MODE;
2780 entry.dest_mode = INT_DEST_MODE;
2781 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2782 entry.trigger = edge_level;
2783 entry.polarity = active_high_low;
2787 * IRQs < 16 are already in the irq_2_pin[] map
2790 add_pin_to_irq(irq, ioapic, pin);
2792 entry.vector = assign_irq_vector(irq);
2794 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2795 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2796 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2797 edge_level, active_high_low);
2799 ioapic_register_intr(irq, entry.vector, edge_level);
2801 if (!ioapic && (irq < 16))
2802 disable_8259A_irq(irq);
2804 spin_lock_irqsave(&ioapic_lock, flags);
2805 __ioapic_write_entry(ioapic, pin, entry);
2806 spin_unlock_irqrestore(&ioapic_lock, flags);
2811 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2815 if (skip_ioapic_setup)
2818 for (i = 0; i < mp_irq_entries; i++)
2819 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2820 mp_irqs[i].mpc_srcbusirq == bus_irq)
2822 if (i >= mp_irq_entries)
2825 *trigger = irq_trigger(i);
2826 *polarity = irq_polarity(i);
2830 #endif /* CONFIG_ACPI */
2832 static int __init parse_disable_timer_pin_1(char *arg)
2834 disable_timer_pin_1 = 1;
2837 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2839 static int __init parse_enable_timer_pin_1(char *arg)
2841 disable_timer_pin_1 = -1;
2844 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2846 static int __init parse_noapic(char *arg)
2848 /* disable IO-APIC */
2849 disable_ioapic_setup();
2852 early_param("noapic", parse_noapic);