2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
61 int timer_over_8254 __initdata = 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug = -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers[MAX_IO_APICS];
74 static int disable_timer_pin_1 __initdata;
77 * Rough estimation of how many shared IRQs there are, can
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84 * This is performance-critical, we want to do it O(1)
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
90 static struct irq_pin_list {
92 } irq_2_pin[PIN_MAP_SIZE];
96 unsigned int unused[3];
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
102 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
108 struct io_apic __iomem *io_apic = io_apic_base(apic);
109 writel(reg, &io_apic->index);
110 return readl(&io_apic->data);
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
115 struct io_apic __iomem *io_apic = io_apic_base(apic);
116 writel(reg, &io_apic->index);
117 writel(value, &io_apic->data);
121 * Re-write a value: to be used for read-modify-write
122 * cycles where the read already set up the index register.
124 * Older SiS APIC requires we rewrite the index register
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
128 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
130 writel(reg, &io_apic->index);
131 writel(value, &io_apic->data);
135 struct { u32 w1, w2; };
136 struct IO_APIC_route_entry entry;
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
141 union entry_union eu;
143 spin_lock_irqsave(&ioapic_lock, flags);
144 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146 spin_unlock_irqrestore(&ioapic_lock, flags);
151 * When we write a new IO APIC routing entry, we need to write the high
152 * word first! If the mask bit in the low word is clear, we will enable
153 * the interrupt, and we need to make sure the entry is fully populated
154 * before that happens.
157 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
159 union entry_union eu;
161 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
162 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
165 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
168 spin_lock_irqsave(&ioapic_lock, flags);
169 __ioapic_write_entry(apic, pin, e);
170 spin_unlock_irqrestore(&ioapic_lock, flags);
174 * When we mask an IO APIC routing entry, we need to write the low
175 * word first, in order to set the mask bit before we change the
178 static void ioapic_mask_entry(int apic, int pin)
181 union entry_union eu = { .entry.mask = 1 };
183 spin_lock_irqsave(&ioapic_lock, flags);
184 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
185 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
186 spin_unlock_irqrestore(&ioapic_lock, flags);
190 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191 * shared ISA-space IRQs, so we have to support them. We are super
192 * fast in the common case, and fast for shared ISA-space IRQs.
194 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
196 static int first_free_entry = NR_IRQS;
197 struct irq_pin_list *entry = irq_2_pin + irq;
200 entry = irq_2_pin + entry->next;
202 if (entry->pin != -1) {
203 entry->next = first_free_entry;
204 entry = irq_2_pin + entry->next;
205 if (++first_free_entry >= PIN_MAP_SIZE)
206 panic("io_apic.c: whoops");
213 * Reroute an IRQ to a different pin.
215 static void __init replace_pin_at_irq(unsigned int irq,
216 int oldapic, int oldpin,
217 int newapic, int newpin)
219 struct irq_pin_list *entry = irq_2_pin + irq;
222 if (entry->apic == oldapic && entry->pin == oldpin) {
223 entry->apic = newapic;
228 entry = irq_2_pin + entry->next;
232 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
234 struct irq_pin_list *entry = irq_2_pin + irq;
235 unsigned int pin, reg;
241 reg = io_apic_read(entry->apic, 0x10 + pin*2);
244 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
247 entry = irq_2_pin + entry->next;
252 static void __mask_IO_APIC_irq (unsigned int irq)
254 __modify_IO_APIC_irq(irq, 0x00010000, 0);
258 static void __unmask_IO_APIC_irq (unsigned int irq)
260 __modify_IO_APIC_irq(irq, 0, 0x00010000);
263 /* mask = 1, trigger = 0 */
264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
266 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
269 /* mask = 0, trigger = 1 */
270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
272 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
275 static void mask_IO_APIC_irq (unsigned int irq)
279 spin_lock_irqsave(&ioapic_lock, flags);
280 __mask_IO_APIC_irq(irq);
281 spin_unlock_irqrestore(&ioapic_lock, flags);
284 static void unmask_IO_APIC_irq (unsigned int irq)
288 spin_lock_irqsave(&ioapic_lock, flags);
289 __unmask_IO_APIC_irq(irq);
290 spin_unlock_irqrestore(&ioapic_lock, flags);
293 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
295 struct IO_APIC_route_entry entry;
297 /* Check delivery_mode to be sure we're not clearing an SMI pin */
298 entry = ioapic_read_entry(apic, pin);
299 if (entry.delivery_mode == dest_SMI)
303 * Disable it in the IO-APIC irq-routing table:
305 ioapic_mask_entry(apic, pin);
308 static void clear_IO_APIC (void)
312 for (apic = 0; apic < nr_ioapics; apic++)
313 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
314 clear_IO_APIC_pin(apic, pin);
318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
322 struct irq_pin_list *entry = irq_2_pin + irq;
323 unsigned int apicid_value;
326 cpus_and(tmp, cpumask, cpu_online_map);
330 cpus_and(cpumask, tmp, CPU_MASK_ALL);
332 apicid_value = cpu_mask_to_apicid(cpumask);
333 /* Prepare to do the io_apic_write */
334 apicid_value = apicid_value << 24;
335 spin_lock_irqsave(&ioapic_lock, flags);
340 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
343 entry = irq_2_pin + entry->next;
345 irq_desc[irq].affinity = cpumask;
346 spin_unlock_irqrestore(&ioapic_lock, flags);
349 #if defined(CONFIG_IRQBALANCE)
350 # include <asm/processor.h> /* kernel_thread() */
351 # include <linux/kernel_stat.h> /* kstat */
352 # include <linux/slab.h> /* kmalloc() */
353 # include <linux/timer.h>
355 #define IRQBALANCE_CHECK_ARCH -999
356 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
357 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
358 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
359 #define BALANCED_IRQ_LESS_DELTA (HZ)
361 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
362 static int physical_balance __read_mostly;
363 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
365 static struct irq_cpu_info {
366 unsigned long * last_irq;
367 unsigned long * irq_delta;
369 } irq_cpu_data[NR_CPUS];
371 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
372 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
373 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
375 #define IDLE_ENOUGH(cpu,now) \
376 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
378 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
382 static cpumask_t balance_irq_affinity[NR_IRQS] = {
383 [0 ... NR_IRQS-1] = CPU_MASK_ALL
386 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
388 balance_irq_affinity[irq] = mask;
391 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
392 unsigned long now, int direction)
400 if (unlikely(cpu == curr_cpu))
403 if (direction == 1) {
412 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
413 (search_idle && !IDLE_ENOUGH(cpu,now)));
418 static inline void balance_irq(int cpu, int irq)
420 unsigned long now = jiffies;
421 cpumask_t allowed_mask;
422 unsigned int new_cpu;
424 if (irqbalance_disabled)
427 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
428 new_cpu = move(cpu, allowed_mask, now, 1);
429 if (cpu != new_cpu) {
430 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
438 for_each_online_cpu(i) {
439 for (j = 0; j < NR_IRQS; j++) {
440 if (!irq_desc[j].action)
442 /* Is it a significant load ? */
443 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
444 useful_load_threshold)
449 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
450 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
454 static void do_irq_balance(void)
457 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
458 unsigned long move_this_load = 0;
459 int max_loaded = 0, min_loaded = 0;
461 unsigned long useful_load_threshold = balanced_irq_interval + 10;
463 int tmp_loaded, first_attempt = 1;
464 unsigned long tmp_cpu_irq;
465 unsigned long imbalance = 0;
466 cpumask_t allowed_mask, target_cpu_mask, tmp;
468 for_each_possible_cpu(i) {
473 package_index = CPU_TO_PACKAGEINDEX(i);
474 for (j = 0; j < NR_IRQS; j++) {
475 unsigned long value_now, delta;
476 /* Is this an active IRQ or balancing disabled ? */
477 if (!irq_desc[j].action || irq_balancing_disabled(j))
479 if ( package_index == i )
480 IRQ_DELTA(package_index,j) = 0;
481 /* Determine the total count per processor per IRQ */
482 value_now = (unsigned long) kstat_cpu(i).irqs[j];
484 /* Determine the activity per processor per IRQ */
485 delta = value_now - LAST_CPU_IRQ(i,j);
487 /* Update last_cpu_irq[][] for the next time */
488 LAST_CPU_IRQ(i,j) = value_now;
490 /* Ignore IRQs whose rate is less than the clock */
491 if (delta < useful_load_threshold)
493 /* update the load for the processor or package total */
494 IRQ_DELTA(package_index,j) += delta;
496 /* Keep track of the higher numbered sibling as well */
497 if (i != package_index)
500 * We have sibling A and sibling B in the package
502 * cpu_irq[A] = load for cpu A + load for cpu B
503 * cpu_irq[B] = load for cpu B
505 CPU_IRQ(package_index) += delta;
508 /* Find the least loaded processor package */
509 for_each_online_cpu(i) {
510 if (i != CPU_TO_PACKAGEINDEX(i))
512 if (min_cpu_irq > CPU_IRQ(i)) {
513 min_cpu_irq = CPU_IRQ(i);
517 max_cpu_irq = ULONG_MAX;
520 /* Look for heaviest loaded processor.
521 * We may come back to get the next heaviest loaded processor.
522 * Skip processors with trivial loads.
526 for_each_online_cpu(i) {
527 if (i != CPU_TO_PACKAGEINDEX(i))
529 if (max_cpu_irq <= CPU_IRQ(i))
531 if (tmp_cpu_irq < CPU_IRQ(i)) {
532 tmp_cpu_irq = CPU_IRQ(i);
537 if (tmp_loaded == -1) {
538 /* In the case of small number of heavy interrupt sources,
539 * loading some of the cpus too much. We use Ingo's original
540 * approach to rotate them around.
542 if (!first_attempt && imbalance >= useful_load_threshold) {
543 rotate_irqs_among_cpus(useful_load_threshold);
546 goto not_worth_the_effort;
549 first_attempt = 0; /* heaviest search */
550 max_cpu_irq = tmp_cpu_irq; /* load */
551 max_loaded = tmp_loaded; /* processor */
552 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
554 /* if imbalance is less than approx 10% of max load, then
555 * observe diminishing returns action. - quit
557 if (imbalance < (max_cpu_irq >> 3))
558 goto not_worth_the_effort;
561 /* if we select an IRQ to move that can't go where we want, then
562 * see if there is another one to try.
566 for (j = 0; j < NR_IRQS; j++) {
567 /* Is this an active IRQ? */
568 if (!irq_desc[j].action)
570 if (imbalance <= IRQ_DELTA(max_loaded,j))
572 /* Try to find the IRQ that is closest to the imbalance
573 * without going over.
575 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
576 move_this_load = IRQ_DELTA(max_loaded,j);
580 if (selected_irq == -1) {
584 imbalance = move_this_load;
586 /* For physical_balance case, we accumulated both load
587 * values in the one of the siblings cpu_irq[],
588 * to use the same code for physical and logical processors
589 * as much as possible.
591 * NOTE: the cpu_irq[] array holds the sum of the load for
592 * sibling A and sibling B in the slot for the lowest numbered
593 * sibling (A), _AND_ the load for sibling B in the slot for
594 * the higher numbered sibling.
596 * We seek the least loaded sibling by making the comparison
599 load = CPU_IRQ(min_loaded) >> 1;
600 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
601 if (load > CPU_IRQ(j)) {
602 /* This won't change cpu_sibling_map[min_loaded] */
608 cpus_and(allowed_mask,
610 balance_irq_affinity[selected_irq]);
611 target_cpu_mask = cpumask_of_cpu(min_loaded);
612 cpus_and(tmp, target_cpu_mask, allowed_mask);
614 if (!cpus_empty(tmp)) {
615 /* mark for change destination */
616 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
618 /* Since we made a change, come back sooner to
619 * check for more variation.
621 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
622 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
627 not_worth_the_effort:
629 * if we did not find an IRQ to move, then adjust the time interval
632 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
633 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
637 static int balanced_irq(void *unused)
640 unsigned long prev_balance_time = jiffies;
641 long time_remaining = balanced_irq_interval;
643 /* push everything to CPU 0 to give us a starting point. */
644 for (i = 0 ; i < NR_IRQS ; i++) {
645 irq_desc[i].pending_mask = cpumask_of_cpu(0);
646 set_pending_irq(i, cpumask_of_cpu(0));
651 time_remaining = schedule_timeout_interruptible(time_remaining);
653 if (time_after(jiffies,
654 prev_balance_time+balanced_irq_interval)) {
657 prev_balance_time = jiffies;
658 time_remaining = balanced_irq_interval;
665 static int __init balanced_irq_init(void)
668 struct cpuinfo_x86 *c;
671 cpus_shift_right(tmp, cpu_online_map, 2);
673 /* When not overwritten by the command line ask subarchitecture. */
674 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
675 irqbalance_disabled = NO_BALANCE_IRQ;
676 if (irqbalance_disabled)
679 /* disable irqbalance completely if there is only one processor online */
680 if (num_online_cpus() < 2) {
681 irqbalance_disabled = 1;
685 * Enable physical balance only if more than 1 physical processor
688 if (smp_num_siblings > 1 && !cpus_empty(tmp))
689 physical_balance = 1;
691 for_each_online_cpu(i) {
692 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
693 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
694 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
695 printk(KERN_ERR "balanced_irq_init: out of memory");
698 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
699 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
702 printk(KERN_INFO "Starting balanced_irq\n");
703 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
705 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
707 for_each_possible_cpu(i) {
708 kfree(irq_cpu_data[i].irq_delta);
709 irq_cpu_data[i].irq_delta = NULL;
710 kfree(irq_cpu_data[i].last_irq);
711 irq_cpu_data[i].last_irq = NULL;
716 int __devinit irqbalance_disable(char *str)
718 irqbalance_disabled = 1;
722 __setup("noirqbalance", irqbalance_disable);
724 late_initcall(balanced_irq_init);
725 #endif /* CONFIG_IRQBALANCE */
726 #endif /* CONFIG_SMP */
729 void send_IPI_self(int vector)
736 apic_wait_icr_idle();
737 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
739 * Send the IPI. The write to APIC_ICR fires this off.
741 apic_write_around(APIC_ICR, cfg);
743 #endif /* !CONFIG_SMP */
747 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
748 * specific CPU-side IRQs.
752 static int pirq_entries [MAX_PIRQS];
753 static int pirqs_enabled;
754 int skip_ioapic_setup;
756 static int __init ioapic_pirq_setup(char *str)
759 int ints[MAX_PIRQS+1];
761 get_options(str, ARRAY_SIZE(ints), ints);
763 for (i = 0; i < MAX_PIRQS; i++)
764 pirq_entries[i] = -1;
767 apic_printk(APIC_VERBOSE, KERN_INFO
768 "PIRQ redirection, working around broken MP-BIOS.\n");
770 if (ints[0] < MAX_PIRQS)
773 for (i = 0; i < max; i++) {
774 apic_printk(APIC_VERBOSE, KERN_DEBUG
775 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
777 * PIRQs are mapped upside down, usually.
779 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
784 __setup("pirq=", ioapic_pirq_setup);
787 * Find the IRQ entry number of a certain pin.
789 static int find_irq_entry(int apic, int pin, int type)
793 for (i = 0; i < mp_irq_entries; i++)
794 if (mp_irqs[i].mpc_irqtype == type &&
795 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
796 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
797 mp_irqs[i].mpc_dstirq == pin)
804 * Find the pin to which IRQ[irq] (ISA) is connected
806 static int __init find_isa_irq_pin(int irq, int type)
810 for (i = 0; i < mp_irq_entries; i++) {
811 int lbus = mp_irqs[i].mpc_srcbus;
813 if (test_bit(lbus, mp_bus_not_pci) &&
814 (mp_irqs[i].mpc_irqtype == type) &&
815 (mp_irqs[i].mpc_srcbusirq == irq))
817 return mp_irqs[i].mpc_dstirq;
822 static int __init find_isa_irq_apic(int irq, int type)
826 for (i = 0; i < mp_irq_entries; i++) {
827 int lbus = mp_irqs[i].mpc_srcbus;
829 if (test_bit(lbus, mp_bus_not_pci) &&
830 (mp_irqs[i].mpc_irqtype == type) &&
831 (mp_irqs[i].mpc_srcbusirq == irq))
834 if (i < mp_irq_entries) {
836 for(apic = 0; apic < nr_ioapics; apic++) {
837 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
846 * Find a specific PCI IRQ entry.
847 * Not an __init, possibly needed by modules
849 static int pin_2_irq(int idx, int apic, int pin);
851 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
853 int apic, i, best_guess = -1;
855 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
856 "slot:%d, pin:%d.\n", bus, slot, pin);
857 if (mp_bus_id_to_pci_bus[bus] == -1) {
858 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
861 for (i = 0; i < mp_irq_entries; i++) {
862 int lbus = mp_irqs[i].mpc_srcbus;
864 for (apic = 0; apic < nr_ioapics; apic++)
865 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
866 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
869 if (!test_bit(lbus, mp_bus_not_pci) &&
870 !mp_irqs[i].mpc_irqtype &&
872 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
873 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
875 if (!(apic || IO_APIC_IRQ(irq)))
878 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
881 * Use the first all-but-pin matching entry as a
882 * best-guess fuzzy result for broken mptables.
890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
893 * This function currently is only a helper for the i386 smp boot process where
894 * we need to reprogram the ioredtbls to cater for the cpus which have come online
895 * so mask in all cases should simply be TARGET_CPUS
898 void __init setup_ioapic_dest(void)
900 int pin, ioapic, irq, irq_entry;
902 if (skip_ioapic_setup == 1)
905 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
906 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
907 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
910 irq = pin_2_irq(irq_entry, ioapic, pin);
911 set_ioapic_affinity_irq(irq, TARGET_CPUS);
919 * EISA Edge/Level control register, ELCR
921 static int EISA_ELCR(unsigned int irq)
924 unsigned int port = 0x4d0 + (irq >> 3);
925 return (inb(port) >> (irq & 7)) & 1;
927 apic_printk(APIC_VERBOSE, KERN_INFO
928 "Broken MPtable reports ISA irq %d\n", irq);
932 /* EISA interrupts are always polarity zero and can be edge or level
933 * trigger depending on the ELCR value. If an interrupt is listed as
934 * EISA conforming in the MP table, that means its trigger type must
935 * be read in from the ELCR */
937 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
938 #define default_EISA_polarity(idx) (0)
940 /* ISA interrupts are always polarity zero edge triggered,
941 * when listed as conforming in the MP table. */
943 #define default_ISA_trigger(idx) (0)
944 #define default_ISA_polarity(idx) (0)
946 /* PCI interrupts are always polarity one level triggered,
947 * when listed as conforming in the MP table. */
949 #define default_PCI_trigger(idx) (1)
950 #define default_PCI_polarity(idx) (1)
952 /* MCA interrupts are always polarity zero level triggered,
953 * when listed as conforming in the MP table. */
955 #define default_MCA_trigger(idx) (1)
956 #define default_MCA_polarity(idx) (0)
958 static int MPBIOS_polarity(int idx)
960 int bus = mp_irqs[idx].mpc_srcbus;
964 * Determine IRQ line polarity (high active or low active):
966 switch (mp_irqs[idx].mpc_irqflag & 3)
968 case 0: /* conforms, ie. bus-type dependent polarity */
970 switch (mp_bus_id_to_type[bus])
972 case MP_BUS_ISA: /* ISA pin */
974 polarity = default_ISA_polarity(idx);
977 case MP_BUS_EISA: /* EISA pin */
979 polarity = default_EISA_polarity(idx);
982 case MP_BUS_PCI: /* PCI pin */
984 polarity = default_PCI_polarity(idx);
987 case MP_BUS_MCA: /* MCA pin */
989 polarity = default_MCA_polarity(idx);
994 printk(KERN_WARNING "broken BIOS!!\n");
1001 case 1: /* high active */
1006 case 2: /* reserved */
1008 printk(KERN_WARNING "broken BIOS!!\n");
1012 case 3: /* low active */
1017 default: /* invalid */
1019 printk(KERN_WARNING "broken BIOS!!\n");
1027 static int MPBIOS_trigger(int idx)
1029 int bus = mp_irqs[idx].mpc_srcbus;
1033 * Determine IRQ trigger mode (edge or level sensitive):
1035 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1037 case 0: /* conforms, ie. bus-type dependent */
1039 switch (mp_bus_id_to_type[bus])
1041 case MP_BUS_ISA: /* ISA pin */
1043 trigger = default_ISA_trigger(idx);
1046 case MP_BUS_EISA: /* EISA pin */
1048 trigger = default_EISA_trigger(idx);
1051 case MP_BUS_PCI: /* PCI pin */
1053 trigger = default_PCI_trigger(idx);
1056 case MP_BUS_MCA: /* MCA pin */
1058 trigger = default_MCA_trigger(idx);
1063 printk(KERN_WARNING "broken BIOS!!\n");
1075 case 2: /* reserved */
1077 printk(KERN_WARNING "broken BIOS!!\n");
1086 default: /* invalid */
1088 printk(KERN_WARNING "broken BIOS!!\n");
1096 static inline int irq_polarity(int idx)
1098 return MPBIOS_polarity(idx);
1101 static inline int irq_trigger(int idx)
1103 return MPBIOS_trigger(idx);
1106 static int pin_2_irq(int idx, int apic, int pin)
1109 int bus = mp_irqs[idx].mpc_srcbus;
1112 * Debugging check, we are in big trouble if this message pops up!
1114 if (mp_irqs[idx].mpc_dstirq != pin)
1115 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1117 switch (mp_bus_id_to_type[bus])
1119 case MP_BUS_ISA: /* ISA pin */
1123 irq = mp_irqs[idx].mpc_srcbusirq;
1126 case MP_BUS_PCI: /* PCI pin */
1129 * PCI IRQs are mapped in order
1133 irq += nr_ioapic_registers[i++];
1137 * For MPS mode, so far only needed by ES7000 platform
1139 if (ioapic_renumber_irq)
1140 irq = ioapic_renumber_irq(apic, irq);
1146 printk(KERN_ERR "unknown bus type %d.\n",bus);
1153 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1155 if ((pin >= 16) && (pin <= 23)) {
1156 if (pirq_entries[pin-16] != -1) {
1157 if (!pirq_entries[pin-16]) {
1158 apic_printk(APIC_VERBOSE, KERN_DEBUG
1159 "disabling PIRQ%d\n", pin-16);
1161 irq = pirq_entries[pin-16];
1162 apic_printk(APIC_VERBOSE, KERN_DEBUG
1163 "using PIRQ%d -> IRQ %d\n",
1171 static inline int IO_APIC_irq_trigger(int irq)
1175 for (apic = 0; apic < nr_ioapics; apic++) {
1176 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1177 idx = find_irq_entry(apic,pin,mp_INT);
1178 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1179 return irq_trigger(idx);
1183 * nonexistent IRQs are edge default
1188 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1189 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1191 static int __assign_irq_vector(int irq)
1193 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1196 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1198 if (irq_vector[irq] > 0)
1199 return irq_vector[irq];
1201 vector = current_vector;
1202 offset = current_offset;
1205 if (vector >= FIRST_SYSTEM_VECTOR) {
1206 offset = (offset + 1) % 8;
1207 vector = FIRST_DEVICE_VECTOR + offset;
1209 if (vector == current_vector)
1211 if (test_and_set_bit(vector, used_vectors))
1214 current_vector = vector;
1215 current_offset = offset;
1216 irq_vector[irq] = vector;
1221 static int assign_irq_vector(int irq)
1223 unsigned long flags;
1226 spin_lock_irqsave(&vector_lock, flags);
1227 vector = __assign_irq_vector(irq);
1228 spin_unlock_irqrestore(&vector_lock, flags);
1232 static struct irq_chip ioapic_chip;
1234 #define IOAPIC_AUTO -1
1235 #define IOAPIC_EDGE 0
1236 #define IOAPIC_LEVEL 1
1238 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1240 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1241 trigger == IOAPIC_LEVEL) {
1242 irq_desc[irq].status |= IRQ_LEVEL;
1243 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1244 handle_fasteoi_irq, "fasteoi");
1246 irq_desc[irq].status &= ~IRQ_LEVEL;
1247 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1248 handle_edge_irq, "edge");
1250 set_intr_gate(vector, interrupt[irq]);
1253 static void __init setup_IO_APIC_irqs(void)
1255 struct IO_APIC_route_entry entry;
1256 int apic, pin, idx, irq, first_notcon = 1, vector;
1257 unsigned long flags;
1259 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1261 for (apic = 0; apic < nr_ioapics; apic++) {
1262 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1265 * add it to the IO-APIC irq-routing table:
1267 memset(&entry,0,sizeof(entry));
1269 entry.delivery_mode = INT_DELIVERY_MODE;
1270 entry.dest_mode = INT_DEST_MODE;
1271 entry.mask = 0; /* enable IRQ */
1272 entry.dest.logical.logical_dest =
1273 cpu_mask_to_apicid(TARGET_CPUS);
1275 idx = find_irq_entry(apic,pin,mp_INT);
1278 apic_printk(APIC_VERBOSE, KERN_DEBUG
1279 " IO-APIC (apicid-pin) %d-%d",
1280 mp_ioapics[apic].mpc_apicid,
1284 apic_printk(APIC_VERBOSE, ", %d-%d",
1285 mp_ioapics[apic].mpc_apicid, pin);
1289 if (!first_notcon) {
1290 apic_printk(APIC_VERBOSE, " not connected.\n");
1294 entry.trigger = irq_trigger(idx);
1295 entry.polarity = irq_polarity(idx);
1297 if (irq_trigger(idx)) {
1302 irq = pin_2_irq(idx, apic, pin);
1304 * skip adding the timer int on secondary nodes, which causes
1305 * a small but painful rift in the time-space continuum
1307 if (multi_timer_check(apic, irq))
1310 add_pin_to_irq(irq, apic, pin);
1312 if (!apic && !IO_APIC_IRQ(irq))
1315 if (IO_APIC_IRQ(irq)) {
1316 vector = assign_irq_vector(irq);
1317 entry.vector = vector;
1318 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1320 if (!apic && (irq < 16))
1321 disable_8259A_irq(irq);
1323 spin_lock_irqsave(&ioapic_lock, flags);
1324 __ioapic_write_entry(apic, pin, entry);
1325 spin_unlock_irqrestore(&ioapic_lock, flags);
1330 apic_printk(APIC_VERBOSE, " not connected.\n");
1334 * Set up the 8259A-master output pin:
1336 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1338 struct IO_APIC_route_entry entry;
1340 memset(&entry,0,sizeof(entry));
1342 disable_8259A_irq(0);
1345 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1348 * We use logical delivery to get the timer IRQ
1351 entry.dest_mode = INT_DEST_MODE;
1352 entry.mask = 0; /* unmask IRQ now */
1353 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1354 entry.delivery_mode = INT_DELIVERY_MODE;
1357 entry.vector = vector;
1360 * The timer IRQ doesn't have to know that behind the
1361 * scene we have a 8259A-master in AEOI mode ...
1363 irq_desc[0].chip = &ioapic_chip;
1364 set_irq_handler(0, handle_edge_irq);
1367 * Add it to the IO-APIC irq-routing table:
1369 ioapic_write_entry(apic, pin, entry);
1371 enable_8259A_irq(0);
1374 void __init print_IO_APIC(void)
1377 union IO_APIC_reg_00 reg_00;
1378 union IO_APIC_reg_01 reg_01;
1379 union IO_APIC_reg_02 reg_02;
1380 union IO_APIC_reg_03 reg_03;
1381 unsigned long flags;
1383 if (apic_verbosity == APIC_QUIET)
1386 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1387 for (i = 0; i < nr_ioapics; i++)
1388 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1389 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1392 * We are a bit conservative about what we expect. We have to
1393 * know about every hardware change ASAP.
1395 printk(KERN_INFO "testing the IO APIC.......................\n");
1397 for (apic = 0; apic < nr_ioapics; apic++) {
1399 spin_lock_irqsave(&ioapic_lock, flags);
1400 reg_00.raw = io_apic_read(apic, 0);
1401 reg_01.raw = io_apic_read(apic, 1);
1402 if (reg_01.bits.version >= 0x10)
1403 reg_02.raw = io_apic_read(apic, 2);
1404 if (reg_01.bits.version >= 0x20)
1405 reg_03.raw = io_apic_read(apic, 3);
1406 spin_unlock_irqrestore(&ioapic_lock, flags);
1408 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1409 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1410 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1411 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1412 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1414 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1415 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1417 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1418 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1421 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1422 * but the value of reg_02 is read as the previous read register
1423 * value, so ignore it if reg_02 == reg_01.
1425 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1426 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1427 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1431 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1432 * or reg_03, but the value of reg_0[23] is read as the previous read
1433 * register value, so ignore it if reg_03 == reg_0[12].
1435 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1436 reg_03.raw != reg_01.raw) {
1437 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1438 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1441 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1443 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1444 " Stat Dest Deli Vect: \n");
1446 for (i = 0; i <= reg_01.bits.entries; i++) {
1447 struct IO_APIC_route_entry entry;
1449 entry = ioapic_read_entry(apic, i);
1451 printk(KERN_DEBUG " %02x %03X %02X ",
1453 entry.dest.logical.logical_dest,
1454 entry.dest.physical.physical_dest
1457 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1462 entry.delivery_status,
1464 entry.delivery_mode,
1469 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1470 for (i = 0; i < NR_IRQS; i++) {
1471 struct irq_pin_list *entry = irq_2_pin + i;
1474 printk(KERN_DEBUG "IRQ%d ", i);
1476 printk("-> %d:%d", entry->apic, entry->pin);
1479 entry = irq_2_pin + entry->next;
1484 printk(KERN_INFO ".................................... done.\n");
1491 static void print_APIC_bitfield (int base)
1496 if (apic_verbosity == APIC_QUIET)
1499 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1500 for (i = 0; i < 8; i++) {
1501 v = apic_read(base + i*0x10);
1502 for (j = 0; j < 32; j++) {
1512 void /*__init*/ print_local_APIC(void * dummy)
1514 unsigned int v, ver, maxlvt;
1516 if (apic_verbosity == APIC_QUIET)
1519 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1520 smp_processor_id(), hard_smp_processor_id());
1521 v = apic_read(APIC_ID);
1522 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1523 v = apic_read(APIC_LVR);
1524 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1525 ver = GET_APIC_VERSION(v);
1526 maxlvt = lapic_get_maxlvt();
1528 v = apic_read(APIC_TASKPRI);
1529 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1531 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1532 v = apic_read(APIC_ARBPRI);
1533 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1534 v & APIC_ARBPRI_MASK);
1535 v = apic_read(APIC_PROCPRI);
1536 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1539 v = apic_read(APIC_EOI);
1540 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1541 v = apic_read(APIC_RRR);
1542 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1543 v = apic_read(APIC_LDR);
1544 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1545 v = apic_read(APIC_DFR);
1546 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1547 v = apic_read(APIC_SPIV);
1548 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1550 printk(KERN_DEBUG "... APIC ISR field:\n");
1551 print_APIC_bitfield(APIC_ISR);
1552 printk(KERN_DEBUG "... APIC TMR field:\n");
1553 print_APIC_bitfield(APIC_TMR);
1554 printk(KERN_DEBUG "... APIC IRR field:\n");
1555 print_APIC_bitfield(APIC_IRR);
1557 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1558 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1559 apic_write(APIC_ESR, 0);
1560 v = apic_read(APIC_ESR);
1561 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1564 v = apic_read(APIC_ICR);
1565 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1566 v = apic_read(APIC_ICR2);
1567 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1569 v = apic_read(APIC_LVTT);
1570 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1572 if (maxlvt > 3) { /* PC is LVT#4. */
1573 v = apic_read(APIC_LVTPC);
1574 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1576 v = apic_read(APIC_LVT0);
1577 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1578 v = apic_read(APIC_LVT1);
1579 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1581 if (maxlvt > 2) { /* ERR is LVT#3. */
1582 v = apic_read(APIC_LVTERR);
1583 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1586 v = apic_read(APIC_TMICT);
1587 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1588 v = apic_read(APIC_TMCCT);
1589 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1590 v = apic_read(APIC_TDCR);
1591 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1595 void print_all_local_APICs (void)
1597 on_each_cpu(print_local_APIC, NULL, 1, 1);
1600 void /*__init*/ print_PIC(void)
1603 unsigned long flags;
1605 if (apic_verbosity == APIC_QUIET)
1608 printk(KERN_DEBUG "\nprinting PIC contents\n");
1610 spin_lock_irqsave(&i8259A_lock, flags);
1612 v = inb(0xa1) << 8 | inb(0x21);
1613 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1615 v = inb(0xa0) << 8 | inb(0x20);
1616 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1620 v = inb(0xa0) << 8 | inb(0x20);
1624 spin_unlock_irqrestore(&i8259A_lock, flags);
1626 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1628 v = inb(0x4d1) << 8 | inb(0x4d0);
1629 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1634 static void __init enable_IO_APIC(void)
1636 union IO_APIC_reg_01 reg_01;
1637 int i8259_apic, i8259_pin;
1639 unsigned long flags;
1641 for (i = 0; i < PIN_MAP_SIZE; i++) {
1642 irq_2_pin[i].pin = -1;
1643 irq_2_pin[i].next = 0;
1646 for (i = 0; i < MAX_PIRQS; i++)
1647 pirq_entries[i] = -1;
1650 * The number of IO-APIC IRQ registers (== #pins):
1652 for (apic = 0; apic < nr_ioapics; apic++) {
1653 spin_lock_irqsave(&ioapic_lock, flags);
1654 reg_01.raw = io_apic_read(apic, 1);
1655 spin_unlock_irqrestore(&ioapic_lock, flags);
1656 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1658 for(apic = 0; apic < nr_ioapics; apic++) {
1660 /* See if any of the pins is in ExtINT mode */
1661 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1662 struct IO_APIC_route_entry entry;
1663 entry = ioapic_read_entry(apic, pin);
1666 /* If the interrupt line is enabled and in ExtInt mode
1667 * I have found the pin where the i8259 is connected.
1669 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1670 ioapic_i8259.apic = apic;
1671 ioapic_i8259.pin = pin;
1677 /* Look to see what if the MP table has reported the ExtINT */
1678 /* If we could not find the appropriate pin by looking at the ioapic
1679 * the i8259 probably is not connected the ioapic but give the
1680 * mptable a chance anyway.
1682 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1683 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1684 /* Trust the MP table if nothing is setup in the hardware */
1685 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1686 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1687 ioapic_i8259.pin = i8259_pin;
1688 ioapic_i8259.apic = i8259_apic;
1690 /* Complain if the MP table and the hardware disagree */
1691 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1692 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1694 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1698 * Do not trust the IO-APIC being empty at bootup
1704 * Not an __init, needed by the reboot code
1706 void disable_IO_APIC(void)
1709 * Clear the IO-APIC before rebooting:
1714 * If the i8259 is routed through an IOAPIC
1715 * Put that IOAPIC in virtual wire mode
1716 * so legacy interrupts can be delivered.
1718 if (ioapic_i8259.pin != -1) {
1719 struct IO_APIC_route_entry entry;
1721 memset(&entry, 0, sizeof(entry));
1722 entry.mask = 0; /* Enabled */
1723 entry.trigger = 0; /* Edge */
1725 entry.polarity = 0; /* High */
1726 entry.delivery_status = 0;
1727 entry.dest_mode = 0; /* Physical */
1728 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1730 entry.dest.physical.physical_dest =
1731 GET_APIC_ID(apic_read(APIC_ID));
1734 * Add it to the IO-APIC irq-routing table:
1736 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1738 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1742 * function to set the IO-APIC physical IDs based on the
1743 * values stored in the MPC table.
1745 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1748 #ifndef CONFIG_X86_NUMAQ
1749 static void __init setup_ioapic_ids_from_mpc(void)
1751 union IO_APIC_reg_00 reg_00;
1752 physid_mask_t phys_id_present_map;
1755 unsigned char old_id;
1756 unsigned long flags;
1759 * Don't check I/O APIC IDs for xAPIC systems. They have
1760 * no meaning without the serial APIC bus.
1762 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1763 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1766 * This is broken; anything with a real cpu count has to
1767 * circumvent this idiocy regardless.
1769 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1772 * Set the IOAPIC ID to the value stored in the MPC table.
1774 for (apic = 0; apic < nr_ioapics; apic++) {
1776 /* Read the register 0 value */
1777 spin_lock_irqsave(&ioapic_lock, flags);
1778 reg_00.raw = io_apic_read(apic, 0);
1779 spin_unlock_irqrestore(&ioapic_lock, flags);
1781 old_id = mp_ioapics[apic].mpc_apicid;
1783 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1784 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1785 apic, mp_ioapics[apic].mpc_apicid);
1786 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1788 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1792 * Sanity check, is the ID really free? Every APIC in a
1793 * system must have a unique ID or we get lots of nice
1794 * 'stuck on smp_invalidate_needed IPI wait' messages.
1796 if (check_apicid_used(phys_id_present_map,
1797 mp_ioapics[apic].mpc_apicid)) {
1798 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1799 apic, mp_ioapics[apic].mpc_apicid);
1800 for (i = 0; i < get_physical_broadcast(); i++)
1801 if (!physid_isset(i, phys_id_present_map))
1803 if (i >= get_physical_broadcast())
1804 panic("Max APIC ID exceeded!\n");
1805 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1807 physid_set(i, phys_id_present_map);
1808 mp_ioapics[apic].mpc_apicid = i;
1811 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1812 apic_printk(APIC_VERBOSE, "Setting %d in the "
1813 "phys_id_present_map\n",
1814 mp_ioapics[apic].mpc_apicid);
1815 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1820 * We need to adjust the IRQ routing table
1821 * if the ID changed.
1823 if (old_id != mp_ioapics[apic].mpc_apicid)
1824 for (i = 0; i < mp_irq_entries; i++)
1825 if (mp_irqs[i].mpc_dstapic == old_id)
1826 mp_irqs[i].mpc_dstapic
1827 = mp_ioapics[apic].mpc_apicid;
1830 * Read the right value from the MPC table and
1831 * write it into the ID register.
1833 apic_printk(APIC_VERBOSE, KERN_INFO
1834 "...changing IO-APIC physical APIC ID to %d ...",
1835 mp_ioapics[apic].mpc_apicid);
1837 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1838 spin_lock_irqsave(&ioapic_lock, flags);
1839 io_apic_write(apic, 0, reg_00.raw);
1840 spin_unlock_irqrestore(&ioapic_lock, flags);
1845 spin_lock_irqsave(&ioapic_lock, flags);
1846 reg_00.raw = io_apic_read(apic, 0);
1847 spin_unlock_irqrestore(&ioapic_lock, flags);
1848 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1849 printk("could not set ID!\n");
1851 apic_printk(APIC_VERBOSE, " ok.\n");
1855 static void __init setup_ioapic_ids_from_mpc(void) { }
1858 int no_timer_check __initdata;
1860 static int __init notimercheck(char *s)
1865 __setup("no_timer_check", notimercheck);
1868 * There is a nasty bug in some older SMP boards, their mptable lies
1869 * about the timer IRQ. We do the following to work around the situation:
1871 * - timer IRQ defaults to IO-APIC IRQ
1872 * - if this function detects that timer IRQs are defunct, then we fall
1873 * back to ISA timer IRQs
1875 static int __init timer_irq_works(void)
1877 unsigned long t1 = jiffies;
1878 unsigned long flags;
1883 local_save_flags(flags);
1885 /* Let ten ticks pass... */
1886 mdelay((10 * 1000) / HZ);
1887 local_irq_restore(flags);
1890 * Expect a few ticks at least, to be sure some possible
1891 * glue logic does not lock up after one or two first
1892 * ticks in a non-ExtINT mode. Also the local APIC
1893 * might have cached one ExtINT interrupt. Finally, at
1894 * least one tick may be lost due to delays.
1896 if (time_after(jiffies, t1 + 4))
1903 * In the SMP+IOAPIC case it might happen that there are an unspecified
1904 * number of pending IRQ events unhandled. These cases are very rare,
1905 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1906 * better to do it this way as thus we do not have to be aware of
1907 * 'pending' interrupts in the IRQ path, except at this point.
1910 * Edge triggered needs to resend any interrupt
1911 * that was delayed but this is now handled in the device
1918 * Starting up a edge-triggered IO-APIC interrupt is
1919 * nasty - we need to make sure that we get the edge.
1920 * If it is already asserted for some reason, we need
1921 * return 1 to indicate that is was pending.
1923 * This is not complete - we should be able to fake
1924 * an edge even if it isn't on the 8259A...
1926 * (We do this for level-triggered IRQs too - it cannot hurt.)
1928 static unsigned int startup_ioapic_irq(unsigned int irq)
1930 int was_pending = 0;
1931 unsigned long flags;
1933 spin_lock_irqsave(&ioapic_lock, flags);
1935 disable_8259A_irq(irq);
1936 if (i8259A_irq_pending(irq))
1939 __unmask_IO_APIC_irq(irq);
1940 spin_unlock_irqrestore(&ioapic_lock, flags);
1945 static void ack_ioapic_irq(unsigned int irq)
1947 move_native_irq(irq);
1951 static void ack_ioapic_quirk_irq(unsigned int irq)
1956 move_native_irq(irq);
1958 * It appears there is an erratum which affects at least version 0x11
1959 * of I/O APIC (that's the 82093AA and cores integrated into various
1960 * chipsets). Under certain conditions a level-triggered interrupt is
1961 * erroneously delivered as edge-triggered one but the respective IRR
1962 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1963 * message but it will never arrive and further interrupts are blocked
1964 * from the source. The exact reason is so far unknown, but the
1965 * phenomenon was observed when two consecutive interrupt requests
1966 * from a given source get delivered to the same CPU and the source is
1967 * temporarily disabled in between.
1969 * A workaround is to simulate an EOI message manually. We achieve it
1970 * by setting the trigger mode to edge and then to level when the edge
1971 * trigger mode gets detected in the TMR of a local APIC for a
1972 * level-triggered interrupt. We mask the source for the time of the
1973 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1974 * The idea is from Manfred Spraul. --macro
1976 i = irq_vector[irq];
1978 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1982 if (!(v & (1 << (i & 0x1f)))) {
1983 atomic_inc(&irq_mis_count);
1984 spin_lock(&ioapic_lock);
1985 __mask_and_edge_IO_APIC_irq(irq);
1986 __unmask_and_level_IO_APIC_irq(irq);
1987 spin_unlock(&ioapic_lock);
1991 static int ioapic_retrigger_irq(unsigned int irq)
1993 send_IPI_self(irq_vector[irq]);
1998 static struct irq_chip ioapic_chip __read_mostly = {
2000 .startup = startup_ioapic_irq,
2001 .mask = mask_IO_APIC_irq,
2002 .unmask = unmask_IO_APIC_irq,
2003 .ack = ack_ioapic_irq,
2004 .eoi = ack_ioapic_quirk_irq,
2006 .set_affinity = set_ioapic_affinity_irq,
2008 .retrigger = ioapic_retrigger_irq,
2012 static inline void init_IO_APIC_traps(void)
2017 * NOTE! The local APIC isn't very good at handling
2018 * multiple interrupts at the same interrupt level.
2019 * As the interrupt level is determined by taking the
2020 * vector number and shifting that right by 4, we
2021 * want to spread these out a bit so that they don't
2022 * all fall in the same interrupt level.
2024 * Also, we've got to be careful not to trash gate
2025 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2027 for (irq = 0; irq < NR_IRQS ; irq++) {
2029 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2031 * Hmm.. We don't have an entry for this,
2032 * so default to an old-fashioned 8259
2033 * interrupt if we can..
2036 make_8259A_irq(irq);
2038 /* Strange. Oh, well.. */
2039 irq_desc[irq].chip = &no_irq_chip;
2045 * The local APIC irq-chip implementation:
2048 static void ack_apic(unsigned int irq)
2053 static void mask_lapic_irq (unsigned int irq)
2057 v = apic_read(APIC_LVT0);
2058 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2061 static void unmask_lapic_irq (unsigned int irq)
2065 v = apic_read(APIC_LVT0);
2066 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2069 static struct irq_chip lapic_chip __read_mostly = {
2070 .name = "local-APIC-edge",
2071 .mask = mask_lapic_irq,
2072 .unmask = unmask_lapic_irq,
2076 static void __init setup_nmi(void)
2079 * Dirty trick to enable the NMI watchdog ...
2080 * We put the 8259A master into AEOI mode and
2081 * unmask on all local APICs LVT0 as NMI.
2083 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2084 * is from Maciej W. Rozycki - so we do not have to EOI from
2085 * the NMI handler or the timer interrupt.
2087 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2089 enable_NMI_through_LVT0();
2091 apic_printk(APIC_VERBOSE, " done.\n");
2095 * This looks a bit hackish but it's about the only one way of sending
2096 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2097 * not support the ExtINT mode, unfortunately. We need to send these
2098 * cycles as some i82489DX-based boards have glue logic that keeps the
2099 * 8259A interrupt line asserted until INTA. --macro
2101 static inline void unlock_ExtINT_logic(void)
2104 struct IO_APIC_route_entry entry0, entry1;
2105 unsigned char save_control, save_freq_select;
2107 pin = find_isa_irq_pin(8, mp_INT);
2112 apic = find_isa_irq_apic(8, mp_INT);
2118 entry0 = ioapic_read_entry(apic, pin);
2119 clear_IO_APIC_pin(apic, pin);
2121 memset(&entry1, 0, sizeof(entry1));
2123 entry1.dest_mode = 0; /* physical delivery */
2124 entry1.mask = 0; /* unmask IRQ now */
2125 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2126 entry1.delivery_mode = dest_ExtINT;
2127 entry1.polarity = entry0.polarity;
2131 ioapic_write_entry(apic, pin, entry1);
2133 save_control = CMOS_READ(RTC_CONTROL);
2134 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2135 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2137 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2142 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2146 CMOS_WRITE(save_control, RTC_CONTROL);
2147 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2148 clear_IO_APIC_pin(apic, pin);
2150 ioapic_write_entry(apic, pin, entry0);
2153 int timer_uses_ioapic_pin_0;
2156 * This code may look a bit paranoid, but it's supposed to cooperate with
2157 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2158 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2159 * fanatically on his truly buggy board.
2161 static inline void __init check_timer(void)
2163 int apic1, pin1, apic2, pin2;
2165 unsigned long flags;
2167 local_irq_save(flags);
2170 * get/set the timer IRQ vector:
2172 disable_8259A_irq(0);
2173 vector = assign_irq_vector(0);
2174 set_intr_gate(vector, interrupt[0]);
2177 * Subtle, code in do_timer_interrupt() expects an AEOI
2178 * mode for the 8259A whenever interrupts are routed
2179 * through I/O APICs. Also IRQ0 has to be enabled in
2180 * the 8259A which implies the virtual wire has to be
2181 * disabled in the local APIC.
2183 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2186 if (timer_over_8254 > 0)
2187 enable_8259A_irq(0);
2189 pin1 = find_isa_irq_pin(0, mp_INT);
2190 apic1 = find_isa_irq_apic(0, mp_INT);
2191 pin2 = ioapic_i8259.pin;
2192 apic2 = ioapic_i8259.apic;
2195 timer_uses_ioapic_pin_0 = 1;
2197 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2198 vector, apic1, pin1, apic2, pin2);
2202 * Ok, does IRQ0 through the IOAPIC work?
2204 unmask_IO_APIC_irq(0);
2205 if (timer_irq_works()) {
2206 if (nmi_watchdog == NMI_IO_APIC) {
2207 disable_8259A_irq(0);
2209 enable_8259A_irq(0);
2211 if (disable_timer_pin_1 > 0)
2212 clear_IO_APIC_pin(0, pin1);
2215 clear_IO_APIC_pin(apic1, pin1);
2216 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2220 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2222 printk("\n..... (found pin %d) ...", pin2);
2224 * legacy devices should be connected to IO APIC #0
2226 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2227 if (timer_irq_works()) {
2230 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2232 add_pin_to_irq(0, apic2, pin2);
2233 if (nmi_watchdog == NMI_IO_APIC) {
2239 * Cleanup, just in case ...
2241 clear_IO_APIC_pin(apic2, pin2);
2243 printk(" failed.\n");
2245 if (nmi_watchdog == NMI_IO_APIC) {
2246 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2250 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2252 disable_8259A_irq(0);
2253 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2255 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2256 enable_8259A_irq(0);
2258 if (timer_irq_works()) {
2259 printk(" works.\n");
2262 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2263 printk(" failed.\n");
2265 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2270 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2272 unlock_ExtINT_logic();
2274 if (timer_irq_works()) {
2275 printk(" works.\n");
2278 printk(" failed :(.\n");
2279 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2280 "report. Then try booting with the 'noapic' option");
2282 local_irq_restore(flags);
2287 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2288 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2289 * Linux doesn't really care, as it's not actually used
2290 * for any interrupt handling anyway.
2292 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2294 void __init setup_IO_APIC(void)
2298 /* Reserve all the system vectors. */
2299 for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2300 set_bit(i, used_vectors);
2305 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2307 io_apic_irqs = ~PIC_IRQS;
2309 printk("ENABLING IO-APIC IRQs\n");
2312 * Set up IO-APIC IRQ routing.
2315 setup_ioapic_ids_from_mpc();
2317 setup_IO_APIC_irqs();
2318 init_IO_APIC_traps();
2324 static int __init setup_disable_8254_timer(char *s)
2326 timer_over_8254 = -1;
2329 static int __init setup_enable_8254_timer(char *s)
2331 timer_over_8254 = 2;
2335 __setup("disable_8254_timer", setup_disable_8254_timer);
2336 __setup("enable_8254_timer", setup_enable_8254_timer);
2339 * Called after all the initialization is done. If we didnt find any
2340 * APIC bugs then we can allow the modify fast path
2343 static int __init io_apic_bug_finalize(void)
2345 if(sis_apic_bug == -1)
2350 late_initcall(io_apic_bug_finalize);
2352 struct sysfs_ioapic_data {
2353 struct sys_device dev;
2354 struct IO_APIC_route_entry entry[0];
2356 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2358 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2360 struct IO_APIC_route_entry *entry;
2361 struct sysfs_ioapic_data *data;
2364 data = container_of(dev, struct sysfs_ioapic_data, dev);
2365 entry = data->entry;
2366 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2367 entry[i] = ioapic_read_entry(dev->id, i);
2372 static int ioapic_resume(struct sys_device *dev)
2374 struct IO_APIC_route_entry *entry;
2375 struct sysfs_ioapic_data *data;
2376 unsigned long flags;
2377 union IO_APIC_reg_00 reg_00;
2380 data = container_of(dev, struct sysfs_ioapic_data, dev);
2381 entry = data->entry;
2383 spin_lock_irqsave(&ioapic_lock, flags);
2384 reg_00.raw = io_apic_read(dev->id, 0);
2385 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2386 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2387 io_apic_write(dev->id, 0, reg_00.raw);
2389 spin_unlock_irqrestore(&ioapic_lock, flags);
2390 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2391 ioapic_write_entry(dev->id, i, entry[i]);
2396 static struct sysdev_class ioapic_sysdev_class = {
2398 .suspend = ioapic_suspend,
2399 .resume = ioapic_resume,
2402 static int __init ioapic_init_sysfs(void)
2404 struct sys_device * dev;
2405 int i, size, error = 0;
2407 error = sysdev_class_register(&ioapic_sysdev_class);
2411 for (i = 0; i < nr_ioapics; i++ ) {
2412 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2413 * sizeof(struct IO_APIC_route_entry);
2414 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2415 if (!mp_ioapic_data[i]) {
2416 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2419 memset(mp_ioapic_data[i], 0, size);
2420 dev = &mp_ioapic_data[i]->dev;
2422 dev->cls = &ioapic_sysdev_class;
2423 error = sysdev_register(dev);
2425 kfree(mp_ioapic_data[i]);
2426 mp_ioapic_data[i] = NULL;
2427 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2435 device_initcall(ioapic_init_sysfs);
2438 * Dynamic irq allocate and deallocation
2440 int create_irq(void)
2442 /* Allocate an unused irq */
2443 int irq, new, vector = 0;
2444 unsigned long flags;
2447 spin_lock_irqsave(&vector_lock, flags);
2448 for (new = (NR_IRQS - 1); new >= 0; new--) {
2449 if (platform_legacy_irq(new))
2451 if (irq_vector[new] != 0)
2453 vector = __assign_irq_vector(new);
2454 if (likely(vector > 0))
2458 spin_unlock_irqrestore(&vector_lock, flags);
2461 set_intr_gate(vector, interrupt[irq]);
2462 dynamic_irq_init(irq);
2467 void destroy_irq(unsigned int irq)
2469 unsigned long flags;
2471 dynamic_irq_cleanup(irq);
2473 spin_lock_irqsave(&vector_lock, flags);
2474 irq_vector[irq] = 0;
2475 spin_unlock_irqrestore(&vector_lock, flags);
2479 * MSI message composition
2481 #ifdef CONFIG_PCI_MSI
2482 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2487 vector = assign_irq_vector(irq);
2489 dest = cpu_mask_to_apicid(TARGET_CPUS);
2491 msg->address_hi = MSI_ADDR_BASE_HI;
2494 ((INT_DEST_MODE == 0) ?
2495 MSI_ADDR_DEST_MODE_PHYSICAL:
2496 MSI_ADDR_DEST_MODE_LOGICAL) |
2497 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2498 MSI_ADDR_REDIRECTION_CPU:
2499 MSI_ADDR_REDIRECTION_LOWPRI) |
2500 MSI_ADDR_DEST_ID(dest);
2503 MSI_DATA_TRIGGER_EDGE |
2504 MSI_DATA_LEVEL_ASSERT |
2505 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2506 MSI_DATA_DELIVERY_FIXED:
2507 MSI_DATA_DELIVERY_LOWPRI) |
2508 MSI_DATA_VECTOR(vector);
2514 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2521 cpus_and(tmp, mask, cpu_online_map);
2522 if (cpus_empty(tmp))
2525 vector = assign_irq_vector(irq);
2529 dest = cpu_mask_to_apicid(mask);
2531 read_msi_msg(irq, &msg);
2533 msg.data &= ~MSI_DATA_VECTOR_MASK;
2534 msg.data |= MSI_DATA_VECTOR(vector);
2535 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2536 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2538 write_msi_msg(irq, &msg);
2539 irq_desc[irq].affinity = mask;
2541 #endif /* CONFIG_SMP */
2544 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2545 * which implement the MSI or MSI-X Capability Structure.
2547 static struct irq_chip msi_chip = {
2549 .unmask = unmask_msi_irq,
2550 .mask = mask_msi_irq,
2551 .ack = ack_ioapic_irq,
2553 .set_affinity = set_msi_irq_affinity,
2555 .retrigger = ioapic_retrigger_irq,
2558 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2566 ret = msi_compose_msg(dev, irq, &msg);
2572 set_irq_msi(irq, desc);
2573 write_msi_msg(irq, &msg);
2575 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2581 void arch_teardown_msi_irq(unsigned int irq)
2586 #endif /* CONFIG_PCI_MSI */
2589 * Hypertransport interrupt support
2591 #ifdef CONFIG_HT_IRQ
2595 static void target_ht_irq(unsigned int irq, unsigned int dest)
2597 struct ht_irq_msg msg;
2598 fetch_ht_irq_msg(irq, &msg);
2600 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2601 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2603 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2604 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2606 write_ht_irq_msg(irq, &msg);
2609 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2614 cpus_and(tmp, mask, cpu_online_map);
2615 if (cpus_empty(tmp))
2618 cpus_and(mask, tmp, CPU_MASK_ALL);
2620 dest = cpu_mask_to_apicid(mask);
2622 target_ht_irq(irq, dest);
2623 irq_desc[irq].affinity = mask;
2627 static struct irq_chip ht_irq_chip = {
2629 .mask = mask_ht_irq,
2630 .unmask = unmask_ht_irq,
2631 .ack = ack_ioapic_irq,
2633 .set_affinity = set_ht_irq_affinity,
2635 .retrigger = ioapic_retrigger_irq,
2638 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2642 vector = assign_irq_vector(irq);
2644 struct ht_irq_msg msg;
2649 cpu_set(vector >> 8, tmp);
2650 dest = cpu_mask_to_apicid(tmp);
2652 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2656 HT_IRQ_LOW_DEST_ID(dest) |
2657 HT_IRQ_LOW_VECTOR(vector) |
2658 ((INT_DEST_MODE == 0) ?
2659 HT_IRQ_LOW_DM_PHYSICAL :
2660 HT_IRQ_LOW_DM_LOGICAL) |
2661 HT_IRQ_LOW_RQEOI_EDGE |
2662 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2663 HT_IRQ_LOW_MT_FIXED :
2664 HT_IRQ_LOW_MT_ARBITRATED) |
2665 HT_IRQ_LOW_IRQ_MASKED;
2667 write_ht_irq_msg(irq, &msg);
2669 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2670 handle_edge_irq, "edge");
2674 #endif /* CONFIG_HT_IRQ */
2676 /* --------------------------------------------------------------------------
2677 ACPI-based IOAPIC Configuration
2678 -------------------------------------------------------------------------- */
2682 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2684 union IO_APIC_reg_00 reg_00;
2685 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2687 unsigned long flags;
2691 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2692 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2693 * supports up to 16 on one shared APIC bus.
2695 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2696 * advantage of new APIC bus architecture.
2699 if (physids_empty(apic_id_map))
2700 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2702 spin_lock_irqsave(&ioapic_lock, flags);
2703 reg_00.raw = io_apic_read(ioapic, 0);
2704 spin_unlock_irqrestore(&ioapic_lock, flags);
2706 if (apic_id >= get_physical_broadcast()) {
2707 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2708 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2709 apic_id = reg_00.bits.ID;
2713 * Every APIC in a system must have a unique ID or we get lots of nice
2714 * 'stuck on smp_invalidate_needed IPI wait' messages.
2716 if (check_apicid_used(apic_id_map, apic_id)) {
2718 for (i = 0; i < get_physical_broadcast(); i++) {
2719 if (!check_apicid_used(apic_id_map, i))
2723 if (i == get_physical_broadcast())
2724 panic("Max apic_id exceeded!\n");
2726 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2727 "trying %d\n", ioapic, apic_id, i);
2732 tmp = apicid_to_cpu_present(apic_id);
2733 physids_or(apic_id_map, apic_id_map, tmp);
2735 if (reg_00.bits.ID != apic_id) {
2736 reg_00.bits.ID = apic_id;
2738 spin_lock_irqsave(&ioapic_lock, flags);
2739 io_apic_write(ioapic, 0, reg_00.raw);
2740 reg_00.raw = io_apic_read(ioapic, 0);
2741 spin_unlock_irqrestore(&ioapic_lock, flags);
2744 if (reg_00.bits.ID != apic_id) {
2745 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2750 apic_printk(APIC_VERBOSE, KERN_INFO
2751 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2757 int __init io_apic_get_version (int ioapic)
2759 union IO_APIC_reg_01 reg_01;
2760 unsigned long flags;
2762 spin_lock_irqsave(&ioapic_lock, flags);
2763 reg_01.raw = io_apic_read(ioapic, 1);
2764 spin_unlock_irqrestore(&ioapic_lock, flags);
2766 return reg_01.bits.version;
2770 int __init io_apic_get_redir_entries (int ioapic)
2772 union IO_APIC_reg_01 reg_01;
2773 unsigned long flags;
2775 spin_lock_irqsave(&ioapic_lock, flags);
2776 reg_01.raw = io_apic_read(ioapic, 1);
2777 spin_unlock_irqrestore(&ioapic_lock, flags);
2779 return reg_01.bits.entries;
2783 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2785 struct IO_APIC_route_entry entry;
2786 unsigned long flags;
2788 if (!IO_APIC_IRQ(irq)) {
2789 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2795 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2796 * Note that we mask (disable) IRQs now -- these get enabled when the
2797 * corresponding device driver registers for this IRQ.
2800 memset(&entry,0,sizeof(entry));
2802 entry.delivery_mode = INT_DELIVERY_MODE;
2803 entry.dest_mode = INT_DEST_MODE;
2804 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2805 entry.trigger = edge_level;
2806 entry.polarity = active_high_low;
2810 * IRQs < 16 are already in the irq_2_pin[] map
2813 add_pin_to_irq(irq, ioapic, pin);
2815 entry.vector = assign_irq_vector(irq);
2817 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2818 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2819 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2820 edge_level, active_high_low);
2822 ioapic_register_intr(irq, entry.vector, edge_level);
2824 if (!ioapic && (irq < 16))
2825 disable_8259A_irq(irq);
2827 spin_lock_irqsave(&ioapic_lock, flags);
2828 __ioapic_write_entry(ioapic, pin, entry);
2829 spin_unlock_irqrestore(&ioapic_lock, flags);
2834 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2838 if (skip_ioapic_setup)
2841 for (i = 0; i < mp_irq_entries; i++)
2842 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2843 mp_irqs[i].mpc_srcbusirq == bus_irq)
2845 if (i >= mp_irq_entries)
2848 *trigger = irq_trigger(i);
2849 *polarity = irq_polarity(i);
2853 #endif /* CONFIG_ACPI */
2855 static int __init parse_disable_timer_pin_1(char *arg)
2857 disable_timer_pin_1 = 1;
2860 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2862 static int __init parse_enable_timer_pin_1(char *arg)
2864 disable_timer_pin_1 = -1;
2867 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2869 static int __init parse_noapic(char *arg)
2871 /* disable IO-APIC */
2872 disable_ioapic_setup();
2875 early_param("noapic", parse_noapic);