2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
61 int timer_over_8254 __initdata = 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug = -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers[MAX_IO_APICS];
74 /* I/O APIC entries */
75 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
78 /* MP IRQ source entries */
79 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
81 /* # of MP IRQ source entries */
84 static int disable_timer_pin_1 __initdata;
86 int first_system_vector = 0xfe;
88 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
91 * Rough estimation of how many shared IRQs there are, can
94 #define MAX_PLUS_SHARED_IRQS NR_IRQS
95 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
98 * This is performance-critical, we want to do it O(1)
100 * the indexing order of this array favors 1:1 mappings
101 * between pins and IRQs.
104 static struct irq_pin_list {
106 } irq_2_pin[PIN_MAP_SIZE];
110 unsigned int unused[3];
114 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
116 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
117 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
120 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
122 struct io_apic __iomem *io_apic = io_apic_base(apic);
123 writel(reg, &io_apic->index);
124 return readl(&io_apic->data);
127 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
129 struct io_apic __iomem *io_apic = io_apic_base(apic);
130 writel(reg, &io_apic->index);
131 writel(value, &io_apic->data);
135 * Re-write a value: to be used for read-modify-write
136 * cycles where the read already set up the index register.
138 * Older SiS APIC requires we rewrite the index register
140 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
142 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
144 writel(reg, &io_apic->index);
145 writel(value, &io_apic->data);
149 struct { u32 w1, w2; };
150 struct IO_APIC_route_entry entry;
153 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
155 union entry_union eu;
157 spin_lock_irqsave(&ioapic_lock, flags);
158 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
159 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
160 spin_unlock_irqrestore(&ioapic_lock, flags);
165 * When we write a new IO APIC routing entry, we need to write the high
166 * word first! If the mask bit in the low word is clear, we will enable
167 * the interrupt, and we need to make sure the entry is fully populated
168 * before that happens.
171 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
173 union entry_union eu;
175 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
176 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
179 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
182 spin_lock_irqsave(&ioapic_lock, flags);
183 __ioapic_write_entry(apic, pin, e);
184 spin_unlock_irqrestore(&ioapic_lock, flags);
188 * When we mask an IO APIC routing entry, we need to write the low
189 * word first, in order to set the mask bit before we change the
192 static void ioapic_mask_entry(int apic, int pin)
195 union entry_union eu = { .entry.mask = 1 };
197 spin_lock_irqsave(&ioapic_lock, flags);
198 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
199 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
200 spin_unlock_irqrestore(&ioapic_lock, flags);
204 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
205 * shared ISA-space IRQs, so we have to support them. We are super
206 * fast in the common case, and fast for shared ISA-space IRQs.
208 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
210 static int first_free_entry = NR_IRQS;
211 struct irq_pin_list *entry = irq_2_pin + irq;
214 entry = irq_2_pin + entry->next;
216 if (entry->pin != -1) {
217 entry->next = first_free_entry;
218 entry = irq_2_pin + entry->next;
219 if (++first_free_entry >= PIN_MAP_SIZE)
220 panic("io_apic.c: whoops");
227 * Reroute an IRQ to a different pin.
229 static void __init replace_pin_at_irq(unsigned int irq,
230 int oldapic, int oldpin,
231 int newapic, int newpin)
233 struct irq_pin_list *entry = irq_2_pin + irq;
236 if (entry->apic == oldapic && entry->pin == oldpin) {
237 entry->apic = newapic;
242 entry = irq_2_pin + entry->next;
246 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
248 struct irq_pin_list *entry = irq_2_pin + irq;
249 unsigned int pin, reg;
255 reg = io_apic_read(entry->apic, 0x10 + pin*2);
258 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
261 entry = irq_2_pin + entry->next;
266 static void __mask_IO_APIC_irq (unsigned int irq)
268 __modify_IO_APIC_irq(irq, 0x00010000, 0);
272 static void __unmask_IO_APIC_irq (unsigned int irq)
274 __modify_IO_APIC_irq(irq, 0, 0x00010000);
277 /* mask = 1, trigger = 0 */
278 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
280 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
283 /* mask = 0, trigger = 1 */
284 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
286 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
289 static void mask_IO_APIC_irq (unsigned int irq)
293 spin_lock_irqsave(&ioapic_lock, flags);
294 __mask_IO_APIC_irq(irq);
295 spin_unlock_irqrestore(&ioapic_lock, flags);
298 static void unmask_IO_APIC_irq (unsigned int irq)
302 spin_lock_irqsave(&ioapic_lock, flags);
303 __unmask_IO_APIC_irq(irq);
304 spin_unlock_irqrestore(&ioapic_lock, flags);
307 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
309 struct IO_APIC_route_entry entry;
311 /* Check delivery_mode to be sure we're not clearing an SMI pin */
312 entry = ioapic_read_entry(apic, pin);
313 if (entry.delivery_mode == dest_SMI)
317 * Disable it in the IO-APIC irq-routing table:
319 ioapic_mask_entry(apic, pin);
322 static void clear_IO_APIC (void)
326 for (apic = 0; apic < nr_ioapics; apic++)
327 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
328 clear_IO_APIC_pin(apic, pin);
332 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
336 struct irq_pin_list *entry = irq_2_pin + irq;
337 unsigned int apicid_value;
340 cpus_and(tmp, cpumask, cpu_online_map);
344 cpus_and(cpumask, tmp, CPU_MASK_ALL);
346 apicid_value = cpu_mask_to_apicid(cpumask);
347 /* Prepare to do the io_apic_write */
348 apicid_value = apicid_value << 24;
349 spin_lock_irqsave(&ioapic_lock, flags);
354 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
357 entry = irq_2_pin + entry->next;
359 irq_desc[irq].affinity = cpumask;
360 spin_unlock_irqrestore(&ioapic_lock, flags);
363 #if defined(CONFIG_IRQBALANCE)
364 # include <asm/processor.h> /* kernel_thread() */
365 # include <linux/kernel_stat.h> /* kstat */
366 # include <linux/slab.h> /* kmalloc() */
367 # include <linux/timer.h>
369 #define IRQBALANCE_CHECK_ARCH -999
370 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
371 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
372 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
373 #define BALANCED_IRQ_LESS_DELTA (HZ)
375 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
376 static int physical_balance __read_mostly;
377 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
379 static struct irq_cpu_info {
380 unsigned long * last_irq;
381 unsigned long * irq_delta;
383 } irq_cpu_data[NR_CPUS];
385 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
386 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
387 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
389 #define IDLE_ENOUGH(cpu,now) \
390 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
392 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
394 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
396 static cpumask_t balance_irq_affinity[NR_IRQS] = {
397 [0 ... NR_IRQS-1] = CPU_MASK_ALL
400 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
402 balance_irq_affinity[irq] = mask;
405 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
406 unsigned long now, int direction)
414 if (unlikely(cpu == curr_cpu))
417 if (direction == 1) {
426 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
427 (search_idle && !IDLE_ENOUGH(cpu,now)));
432 static inline void balance_irq(int cpu, int irq)
434 unsigned long now = jiffies;
435 cpumask_t allowed_mask;
436 unsigned int new_cpu;
438 if (irqbalance_disabled)
441 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
442 new_cpu = move(cpu, allowed_mask, now, 1);
443 if (cpu != new_cpu) {
444 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
448 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
452 for_each_online_cpu(i) {
453 for (j = 0; j < NR_IRQS; j++) {
454 if (!irq_desc[j].action)
456 /* Is it a significant load ? */
457 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
458 useful_load_threshold)
463 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
464 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
468 static void do_irq_balance(void)
471 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
472 unsigned long move_this_load = 0;
473 int max_loaded = 0, min_loaded = 0;
475 unsigned long useful_load_threshold = balanced_irq_interval + 10;
477 int tmp_loaded, first_attempt = 1;
478 unsigned long tmp_cpu_irq;
479 unsigned long imbalance = 0;
480 cpumask_t allowed_mask, target_cpu_mask, tmp;
482 for_each_possible_cpu(i) {
487 package_index = CPU_TO_PACKAGEINDEX(i);
488 for (j = 0; j < NR_IRQS; j++) {
489 unsigned long value_now, delta;
490 /* Is this an active IRQ or balancing disabled ? */
491 if (!irq_desc[j].action || irq_balancing_disabled(j))
493 if ( package_index == i )
494 IRQ_DELTA(package_index,j) = 0;
495 /* Determine the total count per processor per IRQ */
496 value_now = (unsigned long) kstat_cpu(i).irqs[j];
498 /* Determine the activity per processor per IRQ */
499 delta = value_now - LAST_CPU_IRQ(i,j);
501 /* Update last_cpu_irq[][] for the next time */
502 LAST_CPU_IRQ(i,j) = value_now;
504 /* Ignore IRQs whose rate is less than the clock */
505 if (delta < useful_load_threshold)
507 /* update the load for the processor or package total */
508 IRQ_DELTA(package_index,j) += delta;
510 /* Keep track of the higher numbered sibling as well */
511 if (i != package_index)
514 * We have sibling A and sibling B in the package
516 * cpu_irq[A] = load for cpu A + load for cpu B
517 * cpu_irq[B] = load for cpu B
519 CPU_IRQ(package_index) += delta;
522 /* Find the least loaded processor package */
523 for_each_online_cpu(i) {
524 if (i != CPU_TO_PACKAGEINDEX(i))
526 if (min_cpu_irq > CPU_IRQ(i)) {
527 min_cpu_irq = CPU_IRQ(i);
531 max_cpu_irq = ULONG_MAX;
534 /* Look for heaviest loaded processor.
535 * We may come back to get the next heaviest loaded processor.
536 * Skip processors with trivial loads.
540 for_each_online_cpu(i) {
541 if (i != CPU_TO_PACKAGEINDEX(i))
543 if (max_cpu_irq <= CPU_IRQ(i))
545 if (tmp_cpu_irq < CPU_IRQ(i)) {
546 tmp_cpu_irq = CPU_IRQ(i);
551 if (tmp_loaded == -1) {
552 /* In the case of small number of heavy interrupt sources,
553 * loading some of the cpus too much. We use Ingo's original
554 * approach to rotate them around.
556 if (!first_attempt && imbalance >= useful_load_threshold) {
557 rotate_irqs_among_cpus(useful_load_threshold);
560 goto not_worth_the_effort;
563 first_attempt = 0; /* heaviest search */
564 max_cpu_irq = tmp_cpu_irq; /* load */
565 max_loaded = tmp_loaded; /* processor */
566 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
568 /* if imbalance is less than approx 10% of max load, then
569 * observe diminishing returns action. - quit
571 if (imbalance < (max_cpu_irq >> 3))
572 goto not_worth_the_effort;
575 /* if we select an IRQ to move that can't go where we want, then
576 * see if there is another one to try.
580 for (j = 0; j < NR_IRQS; j++) {
581 /* Is this an active IRQ? */
582 if (!irq_desc[j].action)
584 if (imbalance <= IRQ_DELTA(max_loaded,j))
586 /* Try to find the IRQ that is closest to the imbalance
587 * without going over.
589 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
590 move_this_load = IRQ_DELTA(max_loaded,j);
594 if (selected_irq == -1) {
598 imbalance = move_this_load;
600 /* For physical_balance case, we accumulated both load
601 * values in the one of the siblings cpu_irq[],
602 * to use the same code for physical and logical processors
603 * as much as possible.
605 * NOTE: the cpu_irq[] array holds the sum of the load for
606 * sibling A and sibling B in the slot for the lowest numbered
607 * sibling (A), _AND_ the load for sibling B in the slot for
608 * the higher numbered sibling.
610 * We seek the least loaded sibling by making the comparison
613 load = CPU_IRQ(min_loaded) >> 1;
614 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
615 if (load > CPU_IRQ(j)) {
616 /* This won't change cpu_sibling_map[min_loaded] */
622 cpus_and(allowed_mask,
624 balance_irq_affinity[selected_irq]);
625 target_cpu_mask = cpumask_of_cpu(min_loaded);
626 cpus_and(tmp, target_cpu_mask, allowed_mask);
628 if (!cpus_empty(tmp)) {
629 /* mark for change destination */
630 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
632 /* Since we made a change, come back sooner to
633 * check for more variation.
635 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
636 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
641 not_worth_the_effort:
643 * if we did not find an IRQ to move, then adjust the time interval
646 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
647 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
651 static int balanced_irq(void *unused)
654 unsigned long prev_balance_time = jiffies;
655 long time_remaining = balanced_irq_interval;
657 /* push everything to CPU 0 to give us a starting point. */
658 for (i = 0 ; i < NR_IRQS ; i++) {
659 irq_desc[i].pending_mask = cpumask_of_cpu(0);
660 set_pending_irq(i, cpumask_of_cpu(0));
665 time_remaining = schedule_timeout_interruptible(time_remaining);
667 if (time_after(jiffies,
668 prev_balance_time+balanced_irq_interval)) {
671 prev_balance_time = jiffies;
672 time_remaining = balanced_irq_interval;
679 static int __init balanced_irq_init(void)
682 struct cpuinfo_x86 *c;
685 cpus_shift_right(tmp, cpu_online_map, 2);
687 /* When not overwritten by the command line ask subarchitecture. */
688 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
689 irqbalance_disabled = NO_BALANCE_IRQ;
690 if (irqbalance_disabled)
693 /* disable irqbalance completely if there is only one processor online */
694 if (num_online_cpus() < 2) {
695 irqbalance_disabled = 1;
699 * Enable physical balance only if more than 1 physical processor
702 if (smp_num_siblings > 1 && !cpus_empty(tmp))
703 physical_balance = 1;
705 for_each_online_cpu(i) {
706 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
707 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
708 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
709 printk(KERN_ERR "balanced_irq_init: out of memory");
712 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
713 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
716 printk(KERN_INFO "Starting balanced_irq\n");
717 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
719 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
721 for_each_possible_cpu(i) {
722 kfree(irq_cpu_data[i].irq_delta);
723 irq_cpu_data[i].irq_delta = NULL;
724 kfree(irq_cpu_data[i].last_irq);
725 irq_cpu_data[i].last_irq = NULL;
730 int __devinit irqbalance_disable(char *str)
732 irqbalance_disabled = 1;
736 __setup("noirqbalance", irqbalance_disable);
738 late_initcall(balanced_irq_init);
739 #endif /* CONFIG_IRQBALANCE */
740 #endif /* CONFIG_SMP */
743 void send_IPI_self(int vector)
750 apic_wait_icr_idle();
751 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
753 * Send the IPI. The write to APIC_ICR fires this off.
755 apic_write_around(APIC_ICR, cfg);
757 #endif /* !CONFIG_SMP */
761 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
762 * specific CPU-side IRQs.
766 static int pirq_entries [MAX_PIRQS];
767 static int pirqs_enabled;
768 int skip_ioapic_setup;
770 static int __init ioapic_pirq_setup(char *str)
773 int ints[MAX_PIRQS+1];
775 get_options(str, ARRAY_SIZE(ints), ints);
777 for (i = 0; i < MAX_PIRQS; i++)
778 pirq_entries[i] = -1;
781 apic_printk(APIC_VERBOSE, KERN_INFO
782 "PIRQ redirection, working around broken MP-BIOS.\n");
784 if (ints[0] < MAX_PIRQS)
787 for (i = 0; i < max; i++) {
788 apic_printk(APIC_VERBOSE, KERN_DEBUG
789 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
791 * PIRQs are mapped upside down, usually.
793 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
798 __setup("pirq=", ioapic_pirq_setup);
801 * Find the IRQ entry number of a certain pin.
803 static int find_irq_entry(int apic, int pin, int type)
807 for (i = 0; i < mp_irq_entries; i++)
808 if (mp_irqs[i].mpc_irqtype == type &&
809 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
810 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
811 mp_irqs[i].mpc_dstirq == pin)
818 * Find the pin to which IRQ[irq] (ISA) is connected
820 static int __init find_isa_irq_pin(int irq, int type)
824 for (i = 0; i < mp_irq_entries; i++) {
825 int lbus = mp_irqs[i].mpc_srcbus;
827 if (test_bit(lbus, mp_bus_not_pci) &&
828 (mp_irqs[i].mpc_irqtype == type) &&
829 (mp_irqs[i].mpc_srcbusirq == irq))
831 return mp_irqs[i].mpc_dstirq;
836 static int __init find_isa_irq_apic(int irq, int type)
840 for (i = 0; i < mp_irq_entries; i++) {
841 int lbus = mp_irqs[i].mpc_srcbus;
843 if (test_bit(lbus, mp_bus_not_pci) &&
844 (mp_irqs[i].mpc_irqtype == type) &&
845 (mp_irqs[i].mpc_srcbusirq == irq))
848 if (i < mp_irq_entries) {
850 for(apic = 0; apic < nr_ioapics; apic++) {
851 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
860 * Find a specific PCI IRQ entry.
861 * Not an __init, possibly needed by modules
863 static int pin_2_irq(int idx, int apic, int pin);
865 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
867 int apic, i, best_guess = -1;
869 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
870 "slot:%d, pin:%d.\n", bus, slot, pin);
871 if (mp_bus_id_to_pci_bus[bus] == -1) {
872 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
875 for (i = 0; i < mp_irq_entries; i++) {
876 int lbus = mp_irqs[i].mpc_srcbus;
878 for (apic = 0; apic < nr_ioapics; apic++)
879 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
880 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
883 if (!test_bit(lbus, mp_bus_not_pci) &&
884 !mp_irqs[i].mpc_irqtype &&
886 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
887 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
889 if (!(apic || IO_APIC_IRQ(irq)))
892 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
895 * Use the first all-but-pin matching entry as a
896 * best-guess fuzzy result for broken mptables.
904 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
907 * This function currently is only a helper for the i386 smp boot process where
908 * we need to reprogram the ioredtbls to cater for the cpus which have come online
909 * so mask in all cases should simply be TARGET_CPUS
912 void __init setup_ioapic_dest(void)
914 int pin, ioapic, irq, irq_entry;
916 if (skip_ioapic_setup == 1)
919 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
920 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
921 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
924 irq = pin_2_irq(irq_entry, ioapic, pin);
925 set_ioapic_affinity_irq(irq, TARGET_CPUS);
932 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
934 * EISA Edge/Level control register, ELCR
936 static int EISA_ELCR(unsigned int irq)
939 unsigned int port = 0x4d0 + (irq >> 3);
940 return (inb(port) >> (irq & 7)) & 1;
942 apic_printk(APIC_VERBOSE, KERN_INFO
943 "Broken MPtable reports ISA irq %d\n", irq);
948 /* ISA interrupts are always polarity zero edge triggered,
949 * when listed as conforming in the MP table. */
951 #define default_ISA_trigger(idx) (0)
952 #define default_ISA_polarity(idx) (0)
954 /* EISA interrupts are always polarity zero and can be edge or level
955 * trigger depending on the ELCR value. If an interrupt is listed as
956 * EISA conforming in the MP table, that means its trigger type must
957 * be read in from the ELCR */
959 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
960 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
962 /* PCI interrupts are always polarity one level triggered,
963 * when listed as conforming in the MP table. */
965 #define default_PCI_trigger(idx) (1)
966 #define default_PCI_polarity(idx) (1)
968 /* MCA interrupts are always polarity zero level triggered,
969 * when listed as conforming in the MP table. */
971 #define default_MCA_trigger(idx) (1)
972 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
974 static int MPBIOS_polarity(int idx)
976 int bus = mp_irqs[idx].mpc_srcbus;
980 * Determine IRQ line polarity (high active or low active):
982 switch (mp_irqs[idx].mpc_irqflag & 3)
984 case 0: /* conforms, ie. bus-type dependent polarity */
986 polarity = test_bit(bus, mp_bus_not_pci)?
987 default_ISA_polarity(idx):
988 default_PCI_polarity(idx);
991 case 1: /* high active */
996 case 2: /* reserved */
998 printk(KERN_WARNING "broken BIOS!!\n");
1002 case 3: /* low active */
1007 default: /* invalid */
1009 printk(KERN_WARNING "broken BIOS!!\n");
1017 static int MPBIOS_trigger(int idx)
1019 int bus = mp_irqs[idx].mpc_srcbus;
1023 * Determine IRQ trigger mode (edge or level sensitive):
1025 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1027 case 0: /* conforms, ie. bus-type dependent */
1029 trigger = test_bit(bus, mp_bus_not_pci)?
1030 default_ISA_trigger(idx):
1031 default_PCI_trigger(idx);
1032 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1033 switch (mp_bus_id_to_type[bus])
1035 case MP_BUS_ISA: /* ISA pin */
1037 /* set before the switch */
1040 case MP_BUS_EISA: /* EISA pin */
1042 trigger = default_EISA_trigger(idx);
1045 case MP_BUS_PCI: /* PCI pin */
1047 /* set before the switch */
1050 case MP_BUS_MCA: /* MCA pin */
1052 trigger = default_MCA_trigger(idx);
1057 printk(KERN_WARNING "broken BIOS!!\n");
1070 case 2: /* reserved */
1072 printk(KERN_WARNING "broken BIOS!!\n");
1081 default: /* invalid */
1083 printk(KERN_WARNING "broken BIOS!!\n");
1091 static inline int irq_polarity(int idx)
1093 return MPBIOS_polarity(idx);
1096 static inline int irq_trigger(int idx)
1098 return MPBIOS_trigger(idx);
1101 static int pin_2_irq(int idx, int apic, int pin)
1104 int bus = mp_irqs[idx].mpc_srcbus;
1107 * Debugging check, we are in big trouble if this message pops up!
1109 if (mp_irqs[idx].mpc_dstirq != pin)
1110 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1112 if (test_bit(bus, mp_bus_not_pci))
1113 irq = mp_irqs[idx].mpc_srcbusirq;
1116 * PCI IRQs are mapped in order
1120 irq += nr_ioapic_registers[i++];
1124 * For MPS mode, so far only needed by ES7000 platform
1126 if (ioapic_renumber_irq)
1127 irq = ioapic_renumber_irq(apic, irq);
1131 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1133 if ((pin >= 16) && (pin <= 23)) {
1134 if (pirq_entries[pin-16] != -1) {
1135 if (!pirq_entries[pin-16]) {
1136 apic_printk(APIC_VERBOSE, KERN_DEBUG
1137 "disabling PIRQ%d\n", pin-16);
1139 irq = pirq_entries[pin-16];
1140 apic_printk(APIC_VERBOSE, KERN_DEBUG
1141 "using PIRQ%d -> IRQ %d\n",
1149 static inline int IO_APIC_irq_trigger(int irq)
1153 for (apic = 0; apic < nr_ioapics; apic++) {
1154 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1155 idx = find_irq_entry(apic,pin,mp_INT);
1156 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1157 return irq_trigger(idx);
1161 * nonexistent IRQs are edge default
1166 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1167 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1169 static int __assign_irq_vector(int irq)
1171 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1174 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1176 if (irq_vector[irq] > 0)
1177 return irq_vector[irq];
1179 vector = current_vector;
1180 offset = current_offset;
1183 if (vector >= first_system_vector) {
1184 offset = (offset + 1) % 8;
1185 vector = FIRST_DEVICE_VECTOR + offset;
1187 if (vector == current_vector)
1189 if (test_and_set_bit(vector, used_vectors))
1192 current_vector = vector;
1193 current_offset = offset;
1194 irq_vector[irq] = vector;
1199 static int assign_irq_vector(int irq)
1201 unsigned long flags;
1204 spin_lock_irqsave(&vector_lock, flags);
1205 vector = __assign_irq_vector(irq);
1206 spin_unlock_irqrestore(&vector_lock, flags);
1210 static struct irq_chip ioapic_chip;
1212 #define IOAPIC_AUTO -1
1213 #define IOAPIC_EDGE 0
1214 #define IOAPIC_LEVEL 1
1216 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1218 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1219 trigger == IOAPIC_LEVEL) {
1220 irq_desc[irq].status |= IRQ_LEVEL;
1221 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1222 handle_fasteoi_irq, "fasteoi");
1224 irq_desc[irq].status &= ~IRQ_LEVEL;
1225 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1226 handle_edge_irq, "edge");
1228 set_intr_gate(vector, interrupt[irq]);
1231 static void __init setup_IO_APIC_irqs(void)
1233 struct IO_APIC_route_entry entry;
1234 int apic, pin, idx, irq, first_notcon = 1, vector;
1236 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1238 for (apic = 0; apic < nr_ioapics; apic++) {
1239 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1242 * add it to the IO-APIC irq-routing table:
1244 memset(&entry,0,sizeof(entry));
1246 entry.delivery_mode = INT_DELIVERY_MODE;
1247 entry.dest_mode = INT_DEST_MODE;
1248 entry.mask = 0; /* enable IRQ */
1249 entry.dest.logical.logical_dest =
1250 cpu_mask_to_apicid(TARGET_CPUS);
1252 idx = find_irq_entry(apic,pin,mp_INT);
1255 apic_printk(APIC_VERBOSE, KERN_DEBUG
1256 " IO-APIC (apicid-pin) %d-%d",
1257 mp_ioapics[apic].mpc_apicid,
1261 apic_printk(APIC_VERBOSE, ", %d-%d",
1262 mp_ioapics[apic].mpc_apicid, pin);
1266 if (!first_notcon) {
1267 apic_printk(APIC_VERBOSE, " not connected.\n");
1271 entry.trigger = irq_trigger(idx);
1272 entry.polarity = irq_polarity(idx);
1274 if (irq_trigger(idx)) {
1279 irq = pin_2_irq(idx, apic, pin);
1281 * skip adding the timer int on secondary nodes, which causes
1282 * a small but painful rift in the time-space continuum
1284 if (multi_timer_check(apic, irq))
1287 add_pin_to_irq(irq, apic, pin);
1289 if (!apic && !IO_APIC_IRQ(irq))
1292 if (IO_APIC_IRQ(irq)) {
1293 vector = assign_irq_vector(irq);
1294 entry.vector = vector;
1295 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1297 if (!apic && (irq < 16))
1298 disable_8259A_irq(irq);
1300 ioapic_write_entry(apic, pin, entry);
1305 apic_printk(APIC_VERBOSE, " not connected.\n");
1309 * Set up the 8259A-master output pin:
1311 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1313 struct IO_APIC_route_entry entry;
1315 memset(&entry,0,sizeof(entry));
1317 disable_8259A_irq(0);
1320 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1323 * We use logical delivery to get the timer IRQ
1326 entry.dest_mode = INT_DEST_MODE;
1327 entry.mask = 0; /* unmask IRQ now */
1328 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1329 entry.delivery_mode = INT_DELIVERY_MODE;
1332 entry.vector = vector;
1335 * The timer IRQ doesn't have to know that behind the
1336 * scene we have a 8259A-master in AEOI mode ...
1338 irq_desc[0].chip = &ioapic_chip;
1339 set_irq_handler(0, handle_edge_irq);
1342 * Add it to the IO-APIC irq-routing table:
1344 ioapic_write_entry(apic, pin, entry);
1346 enable_8259A_irq(0);
1349 void __init print_IO_APIC(void)
1352 union IO_APIC_reg_00 reg_00;
1353 union IO_APIC_reg_01 reg_01;
1354 union IO_APIC_reg_02 reg_02;
1355 union IO_APIC_reg_03 reg_03;
1356 unsigned long flags;
1358 if (apic_verbosity == APIC_QUIET)
1361 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1362 for (i = 0; i < nr_ioapics; i++)
1363 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1364 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1367 * We are a bit conservative about what we expect. We have to
1368 * know about every hardware change ASAP.
1370 printk(KERN_INFO "testing the IO APIC.......................\n");
1372 for (apic = 0; apic < nr_ioapics; apic++) {
1374 spin_lock_irqsave(&ioapic_lock, flags);
1375 reg_00.raw = io_apic_read(apic, 0);
1376 reg_01.raw = io_apic_read(apic, 1);
1377 if (reg_01.bits.version >= 0x10)
1378 reg_02.raw = io_apic_read(apic, 2);
1379 if (reg_01.bits.version >= 0x20)
1380 reg_03.raw = io_apic_read(apic, 3);
1381 spin_unlock_irqrestore(&ioapic_lock, flags);
1383 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1384 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1385 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1386 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1387 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1389 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1390 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1392 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1393 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1396 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1397 * but the value of reg_02 is read as the previous read register
1398 * value, so ignore it if reg_02 == reg_01.
1400 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1401 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1402 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1406 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1407 * or reg_03, but the value of reg_0[23] is read as the previous read
1408 * register value, so ignore it if reg_03 == reg_0[12].
1410 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1411 reg_03.raw != reg_01.raw) {
1412 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1413 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1416 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1418 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1419 " Stat Dest Deli Vect: \n");
1421 for (i = 0; i <= reg_01.bits.entries; i++) {
1422 struct IO_APIC_route_entry entry;
1424 entry = ioapic_read_entry(apic, i);
1426 printk(KERN_DEBUG " %02x %03X %02X ",
1428 entry.dest.logical.logical_dest,
1429 entry.dest.physical.physical_dest
1432 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1437 entry.delivery_status,
1439 entry.delivery_mode,
1444 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1445 for (i = 0; i < NR_IRQS; i++) {
1446 struct irq_pin_list *entry = irq_2_pin + i;
1449 printk(KERN_DEBUG "IRQ%d ", i);
1451 printk("-> %d:%d", entry->apic, entry->pin);
1454 entry = irq_2_pin + entry->next;
1459 printk(KERN_INFO ".................................... done.\n");
1466 static void print_APIC_bitfield (int base)
1471 if (apic_verbosity == APIC_QUIET)
1474 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1475 for (i = 0; i < 8; i++) {
1476 v = apic_read(base + i*0x10);
1477 for (j = 0; j < 32; j++) {
1487 void /*__init*/ print_local_APIC(void * dummy)
1489 unsigned int v, ver, maxlvt;
1491 if (apic_verbosity == APIC_QUIET)
1494 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1495 smp_processor_id(), hard_smp_processor_id());
1496 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1497 GET_APIC_ID(read_apic_id()));
1498 v = apic_read(APIC_LVR);
1499 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1500 ver = GET_APIC_VERSION(v);
1501 maxlvt = lapic_get_maxlvt();
1503 v = apic_read(APIC_TASKPRI);
1504 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1506 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1507 v = apic_read(APIC_ARBPRI);
1508 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1509 v & APIC_ARBPRI_MASK);
1510 v = apic_read(APIC_PROCPRI);
1511 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1514 v = apic_read(APIC_EOI);
1515 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1516 v = apic_read(APIC_RRR);
1517 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1518 v = apic_read(APIC_LDR);
1519 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1520 v = apic_read(APIC_DFR);
1521 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1522 v = apic_read(APIC_SPIV);
1523 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1525 printk(KERN_DEBUG "... APIC ISR field:\n");
1526 print_APIC_bitfield(APIC_ISR);
1527 printk(KERN_DEBUG "... APIC TMR field:\n");
1528 print_APIC_bitfield(APIC_TMR);
1529 printk(KERN_DEBUG "... APIC IRR field:\n");
1530 print_APIC_bitfield(APIC_IRR);
1532 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1533 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1534 apic_write(APIC_ESR, 0);
1535 v = apic_read(APIC_ESR);
1536 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1539 v = apic_read(APIC_ICR);
1540 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1541 v = apic_read(APIC_ICR2);
1542 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1544 v = apic_read(APIC_LVTT);
1545 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1547 if (maxlvt > 3) { /* PC is LVT#4. */
1548 v = apic_read(APIC_LVTPC);
1549 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1551 v = apic_read(APIC_LVT0);
1552 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1553 v = apic_read(APIC_LVT1);
1554 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1556 if (maxlvt > 2) { /* ERR is LVT#3. */
1557 v = apic_read(APIC_LVTERR);
1558 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1561 v = apic_read(APIC_TMICT);
1562 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1563 v = apic_read(APIC_TMCCT);
1564 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1565 v = apic_read(APIC_TDCR);
1566 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1570 void print_all_local_APICs (void)
1572 on_each_cpu(print_local_APIC, NULL, 1, 1);
1575 void /*__init*/ print_PIC(void)
1578 unsigned long flags;
1580 if (apic_verbosity == APIC_QUIET)
1583 printk(KERN_DEBUG "\nprinting PIC contents\n");
1585 spin_lock_irqsave(&i8259A_lock, flags);
1587 v = inb(0xa1) << 8 | inb(0x21);
1588 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1590 v = inb(0xa0) << 8 | inb(0x20);
1591 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1595 v = inb(0xa0) << 8 | inb(0x20);
1599 spin_unlock_irqrestore(&i8259A_lock, flags);
1601 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1603 v = inb(0x4d1) << 8 | inb(0x4d0);
1604 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1609 static void __init enable_IO_APIC(void)
1611 union IO_APIC_reg_01 reg_01;
1612 int i8259_apic, i8259_pin;
1614 unsigned long flags;
1616 for (i = 0; i < PIN_MAP_SIZE; i++) {
1617 irq_2_pin[i].pin = -1;
1618 irq_2_pin[i].next = 0;
1621 for (i = 0; i < MAX_PIRQS; i++)
1622 pirq_entries[i] = -1;
1625 * The number of IO-APIC IRQ registers (== #pins):
1627 for (apic = 0; apic < nr_ioapics; apic++) {
1628 spin_lock_irqsave(&ioapic_lock, flags);
1629 reg_01.raw = io_apic_read(apic, 1);
1630 spin_unlock_irqrestore(&ioapic_lock, flags);
1631 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1633 for(apic = 0; apic < nr_ioapics; apic++) {
1635 /* See if any of the pins is in ExtINT mode */
1636 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1637 struct IO_APIC_route_entry entry;
1638 entry = ioapic_read_entry(apic, pin);
1641 /* If the interrupt line is enabled and in ExtInt mode
1642 * I have found the pin where the i8259 is connected.
1644 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1645 ioapic_i8259.apic = apic;
1646 ioapic_i8259.pin = pin;
1652 /* Look to see what if the MP table has reported the ExtINT */
1653 /* If we could not find the appropriate pin by looking at the ioapic
1654 * the i8259 probably is not connected the ioapic but give the
1655 * mptable a chance anyway.
1657 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1658 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1659 /* Trust the MP table if nothing is setup in the hardware */
1660 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1661 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1662 ioapic_i8259.pin = i8259_pin;
1663 ioapic_i8259.apic = i8259_apic;
1665 /* Complain if the MP table and the hardware disagree */
1666 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1667 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1669 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1673 * Do not trust the IO-APIC being empty at bootup
1679 * Not an __init, needed by the reboot code
1681 void disable_IO_APIC(void)
1684 * Clear the IO-APIC before rebooting:
1689 * If the i8259 is routed through an IOAPIC
1690 * Put that IOAPIC in virtual wire mode
1691 * so legacy interrupts can be delivered.
1693 if (ioapic_i8259.pin != -1) {
1694 struct IO_APIC_route_entry entry;
1696 memset(&entry, 0, sizeof(entry));
1697 entry.mask = 0; /* Enabled */
1698 entry.trigger = 0; /* Edge */
1700 entry.polarity = 0; /* High */
1701 entry.delivery_status = 0;
1702 entry.dest_mode = 0; /* Physical */
1703 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1705 entry.dest.physical.physical_dest =
1706 GET_APIC_ID(read_apic_id());
1709 * Add it to the IO-APIC irq-routing table:
1711 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1713 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1717 * function to set the IO-APIC physical IDs based on the
1718 * values stored in the MPC table.
1720 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1723 #ifndef CONFIG_X86_NUMAQ
1724 static void __init setup_ioapic_ids_from_mpc(void)
1726 union IO_APIC_reg_00 reg_00;
1727 physid_mask_t phys_id_present_map;
1730 unsigned char old_id;
1731 unsigned long flags;
1734 * Don't check I/O APIC IDs for xAPIC systems. They have
1735 * no meaning without the serial APIC bus.
1737 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1738 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1741 * This is broken; anything with a real cpu count has to
1742 * circumvent this idiocy regardless.
1744 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1747 * Set the IOAPIC ID to the value stored in the MPC table.
1749 for (apic = 0; apic < nr_ioapics; apic++) {
1751 /* Read the register 0 value */
1752 spin_lock_irqsave(&ioapic_lock, flags);
1753 reg_00.raw = io_apic_read(apic, 0);
1754 spin_unlock_irqrestore(&ioapic_lock, flags);
1756 old_id = mp_ioapics[apic].mpc_apicid;
1758 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1759 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1760 apic, mp_ioapics[apic].mpc_apicid);
1761 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1763 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1767 * Sanity check, is the ID really free? Every APIC in a
1768 * system must have a unique ID or we get lots of nice
1769 * 'stuck on smp_invalidate_needed IPI wait' messages.
1771 if (check_apicid_used(phys_id_present_map,
1772 mp_ioapics[apic].mpc_apicid)) {
1773 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1774 apic, mp_ioapics[apic].mpc_apicid);
1775 for (i = 0; i < get_physical_broadcast(); i++)
1776 if (!physid_isset(i, phys_id_present_map))
1778 if (i >= get_physical_broadcast())
1779 panic("Max APIC ID exceeded!\n");
1780 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1782 physid_set(i, phys_id_present_map);
1783 mp_ioapics[apic].mpc_apicid = i;
1786 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1787 apic_printk(APIC_VERBOSE, "Setting %d in the "
1788 "phys_id_present_map\n",
1789 mp_ioapics[apic].mpc_apicid);
1790 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1795 * We need to adjust the IRQ routing table
1796 * if the ID changed.
1798 if (old_id != mp_ioapics[apic].mpc_apicid)
1799 for (i = 0; i < mp_irq_entries; i++)
1800 if (mp_irqs[i].mpc_dstapic == old_id)
1801 mp_irqs[i].mpc_dstapic
1802 = mp_ioapics[apic].mpc_apicid;
1805 * Read the right value from the MPC table and
1806 * write it into the ID register.
1808 apic_printk(APIC_VERBOSE, KERN_INFO
1809 "...changing IO-APIC physical APIC ID to %d ...",
1810 mp_ioapics[apic].mpc_apicid);
1812 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1813 spin_lock_irqsave(&ioapic_lock, flags);
1814 io_apic_write(apic, 0, reg_00.raw);
1815 spin_unlock_irqrestore(&ioapic_lock, flags);
1820 spin_lock_irqsave(&ioapic_lock, flags);
1821 reg_00.raw = io_apic_read(apic, 0);
1822 spin_unlock_irqrestore(&ioapic_lock, flags);
1823 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1824 printk("could not set ID!\n");
1826 apic_printk(APIC_VERBOSE, " ok.\n");
1830 static void __init setup_ioapic_ids_from_mpc(void) { }
1833 int no_timer_check __initdata;
1835 static int __init notimercheck(char *s)
1840 __setup("no_timer_check", notimercheck);
1843 * There is a nasty bug in some older SMP boards, their mptable lies
1844 * about the timer IRQ. We do the following to work around the situation:
1846 * - timer IRQ defaults to IO-APIC IRQ
1847 * - if this function detects that timer IRQs are defunct, then we fall
1848 * back to ISA timer IRQs
1850 static int __init timer_irq_works(void)
1852 unsigned long t1 = jiffies;
1853 unsigned long flags;
1858 local_save_flags(flags);
1860 /* Let ten ticks pass... */
1861 mdelay((10 * 1000) / HZ);
1862 local_irq_restore(flags);
1865 * Expect a few ticks at least, to be sure some possible
1866 * glue logic does not lock up after one or two first
1867 * ticks in a non-ExtINT mode. Also the local APIC
1868 * might have cached one ExtINT interrupt. Finally, at
1869 * least one tick may be lost due to delays.
1871 if (time_after(jiffies, t1 + 4))
1878 * In the SMP+IOAPIC case it might happen that there are an unspecified
1879 * number of pending IRQ events unhandled. These cases are very rare,
1880 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1881 * better to do it this way as thus we do not have to be aware of
1882 * 'pending' interrupts in the IRQ path, except at this point.
1885 * Edge triggered needs to resend any interrupt
1886 * that was delayed but this is now handled in the device
1893 * Starting up a edge-triggered IO-APIC interrupt is
1894 * nasty - we need to make sure that we get the edge.
1895 * If it is already asserted for some reason, we need
1896 * return 1 to indicate that is was pending.
1898 * This is not complete - we should be able to fake
1899 * an edge even if it isn't on the 8259A...
1901 * (We do this for level-triggered IRQs too - it cannot hurt.)
1903 static unsigned int startup_ioapic_irq(unsigned int irq)
1905 int was_pending = 0;
1906 unsigned long flags;
1908 spin_lock_irqsave(&ioapic_lock, flags);
1910 disable_8259A_irq(irq);
1911 if (i8259A_irq_pending(irq))
1914 __unmask_IO_APIC_irq(irq);
1915 spin_unlock_irqrestore(&ioapic_lock, flags);
1920 static void ack_ioapic_irq(unsigned int irq)
1922 move_native_irq(irq);
1926 static void ack_ioapic_quirk_irq(unsigned int irq)
1931 move_native_irq(irq);
1933 * It appears there is an erratum which affects at least version 0x11
1934 * of I/O APIC (that's the 82093AA and cores integrated into various
1935 * chipsets). Under certain conditions a level-triggered interrupt is
1936 * erroneously delivered as edge-triggered one but the respective IRR
1937 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1938 * message but it will never arrive and further interrupts are blocked
1939 * from the source. The exact reason is so far unknown, but the
1940 * phenomenon was observed when two consecutive interrupt requests
1941 * from a given source get delivered to the same CPU and the source is
1942 * temporarily disabled in between.
1944 * A workaround is to simulate an EOI message manually. We achieve it
1945 * by setting the trigger mode to edge and then to level when the edge
1946 * trigger mode gets detected in the TMR of a local APIC for a
1947 * level-triggered interrupt. We mask the source for the time of the
1948 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1949 * The idea is from Manfred Spraul. --macro
1951 i = irq_vector[irq];
1953 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1957 if (!(v & (1 << (i & 0x1f)))) {
1958 atomic_inc(&irq_mis_count);
1959 spin_lock(&ioapic_lock);
1960 __mask_and_edge_IO_APIC_irq(irq);
1961 __unmask_and_level_IO_APIC_irq(irq);
1962 spin_unlock(&ioapic_lock);
1966 static int ioapic_retrigger_irq(unsigned int irq)
1968 send_IPI_self(irq_vector[irq]);
1973 static struct irq_chip ioapic_chip __read_mostly = {
1975 .startup = startup_ioapic_irq,
1976 .mask = mask_IO_APIC_irq,
1977 .unmask = unmask_IO_APIC_irq,
1978 .ack = ack_ioapic_irq,
1979 .eoi = ack_ioapic_quirk_irq,
1981 .set_affinity = set_ioapic_affinity_irq,
1983 .retrigger = ioapic_retrigger_irq,
1987 static inline void init_IO_APIC_traps(void)
1992 * NOTE! The local APIC isn't very good at handling
1993 * multiple interrupts at the same interrupt level.
1994 * As the interrupt level is determined by taking the
1995 * vector number and shifting that right by 4, we
1996 * want to spread these out a bit so that they don't
1997 * all fall in the same interrupt level.
1999 * Also, we've got to be careful not to trash gate
2000 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2002 for (irq = 0; irq < NR_IRQS ; irq++) {
2003 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
2005 * Hmm.. We don't have an entry for this,
2006 * so default to an old-fashioned 8259
2007 * interrupt if we can..
2010 make_8259A_irq(irq);
2012 /* Strange. Oh, well.. */
2013 irq_desc[irq].chip = &no_irq_chip;
2019 * The local APIC irq-chip implementation:
2022 static void ack_apic(unsigned int irq)
2027 static void mask_lapic_irq (unsigned int irq)
2031 v = apic_read(APIC_LVT0);
2032 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2035 static void unmask_lapic_irq (unsigned int irq)
2039 v = apic_read(APIC_LVT0);
2040 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2043 static struct irq_chip lapic_chip __read_mostly = {
2044 .name = "local-APIC-edge",
2045 .mask = mask_lapic_irq,
2046 .unmask = unmask_lapic_irq,
2050 static void __init setup_nmi(void)
2053 * Dirty trick to enable the NMI watchdog ...
2054 * We put the 8259A master into AEOI mode and
2055 * unmask on all local APICs LVT0 as NMI.
2057 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2058 * is from Maciej W. Rozycki - so we do not have to EOI from
2059 * the NMI handler or the timer interrupt.
2061 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2063 enable_NMI_through_LVT0();
2065 apic_printk(APIC_VERBOSE, " done.\n");
2069 * This looks a bit hackish but it's about the only one way of sending
2070 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2071 * not support the ExtINT mode, unfortunately. We need to send these
2072 * cycles as some i82489DX-based boards have glue logic that keeps the
2073 * 8259A interrupt line asserted until INTA. --macro
2075 static inline void __init unlock_ExtINT_logic(void)
2078 struct IO_APIC_route_entry entry0, entry1;
2079 unsigned char save_control, save_freq_select;
2081 pin = find_isa_irq_pin(8, mp_INT);
2086 apic = find_isa_irq_apic(8, mp_INT);
2092 entry0 = ioapic_read_entry(apic, pin);
2093 clear_IO_APIC_pin(apic, pin);
2095 memset(&entry1, 0, sizeof(entry1));
2097 entry1.dest_mode = 0; /* physical delivery */
2098 entry1.mask = 0; /* unmask IRQ now */
2099 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2100 entry1.delivery_mode = dest_ExtINT;
2101 entry1.polarity = entry0.polarity;
2105 ioapic_write_entry(apic, pin, entry1);
2107 save_control = CMOS_READ(RTC_CONTROL);
2108 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2109 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2111 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2116 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2120 CMOS_WRITE(save_control, RTC_CONTROL);
2121 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2122 clear_IO_APIC_pin(apic, pin);
2124 ioapic_write_entry(apic, pin, entry0);
2128 * This code may look a bit paranoid, but it's supposed to cooperate with
2129 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2130 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2131 * fanatically on his truly buggy board.
2133 static inline void __init check_timer(void)
2135 int apic1, pin1, apic2, pin2;
2138 unsigned long flags;
2140 local_irq_save(flags);
2142 ver = apic_read(APIC_LVR);
2143 ver = GET_APIC_VERSION(ver);
2146 * get/set the timer IRQ vector:
2148 disable_8259A_irq(0);
2149 vector = assign_irq_vector(0);
2150 set_intr_gate(vector, interrupt[0]);
2153 * Subtle, code in do_timer_interrupt() expects an AEOI
2154 * mode for the 8259A whenever interrupts are routed
2155 * through I/O APICs. Also IRQ0 has to be enabled in
2156 * the 8259A which implies the virtual wire has to be
2157 * disabled in the local APIC. Finally timer interrupts
2158 * need to be acknowledged manually in the 8259A for
2159 * timer_interrupt() and for the i82489DX when using
2162 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2164 timer_ack = !cpu_has_tsc;
2165 timer_ack |= (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2166 if (timer_over_8254 > 0)
2167 enable_8259A_irq(0);
2169 pin1 = find_isa_irq_pin(0, mp_INT);
2170 apic1 = find_isa_irq_apic(0, mp_INT);
2171 pin2 = ioapic_i8259.pin;
2172 apic2 = ioapic_i8259.apic;
2174 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2175 vector, apic1, pin1, apic2, pin2);
2179 * Ok, does IRQ0 through the IOAPIC work?
2181 unmask_IO_APIC_irq(0);
2182 if (timer_irq_works()) {
2183 if (nmi_watchdog == NMI_IO_APIC) {
2184 disable_8259A_irq(0);
2186 enable_8259A_irq(0);
2188 if (disable_timer_pin_1 > 0)
2189 clear_IO_APIC_pin(0, pin1);
2192 clear_IO_APIC_pin(apic1, pin1);
2193 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2197 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2199 printk("\n..... (found pin %d) ...", pin2);
2201 * legacy devices should be connected to IO APIC #0
2203 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2204 if (timer_irq_works()) {
2207 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2209 add_pin_to_irq(0, apic2, pin2);
2210 if (nmi_watchdog == NMI_IO_APIC) {
2216 * Cleanup, just in case ...
2218 clear_IO_APIC_pin(apic2, pin2);
2220 printk(" failed.\n");
2222 if (nmi_watchdog == NMI_IO_APIC) {
2223 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2227 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2229 disable_8259A_irq(0);
2230 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2232 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2233 enable_8259A_irq(0);
2235 if (timer_irq_works()) {
2236 printk(" works.\n");
2239 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2240 printk(" failed.\n");
2242 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2247 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2249 unlock_ExtINT_logic();
2251 if (timer_irq_works()) {
2252 printk(" works.\n");
2255 printk(" failed :(.\n");
2256 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2257 "report. Then try booting with the 'noapic' option");
2259 local_irq_restore(flags);
2264 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2265 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2266 * Linux doesn't really care, as it's not actually used
2267 * for any interrupt handling anyway.
2269 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2271 void __init setup_IO_APIC(void)
2275 /* Reserve all the system vectors. */
2276 for (i = first_system_vector; i < NR_VECTORS; i++)
2277 set_bit(i, used_vectors);
2282 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2284 io_apic_irqs = ~PIC_IRQS;
2286 printk("ENABLING IO-APIC IRQs\n");
2289 * Set up IO-APIC IRQ routing.
2292 setup_ioapic_ids_from_mpc();
2294 setup_IO_APIC_irqs();
2295 init_IO_APIC_traps();
2301 static int __init setup_disable_8254_timer(char *s)
2303 timer_over_8254 = -1;
2306 static int __init setup_enable_8254_timer(char *s)
2308 timer_over_8254 = 2;
2312 __setup("disable_8254_timer", setup_disable_8254_timer);
2313 __setup("enable_8254_timer", setup_enable_8254_timer);
2316 * Called after all the initialization is done. If we didnt find any
2317 * APIC bugs then we can allow the modify fast path
2320 static int __init io_apic_bug_finalize(void)
2322 if(sis_apic_bug == -1)
2327 late_initcall(io_apic_bug_finalize);
2329 struct sysfs_ioapic_data {
2330 struct sys_device dev;
2331 struct IO_APIC_route_entry entry[0];
2333 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2335 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2337 struct IO_APIC_route_entry *entry;
2338 struct sysfs_ioapic_data *data;
2341 data = container_of(dev, struct sysfs_ioapic_data, dev);
2342 entry = data->entry;
2343 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2344 entry[i] = ioapic_read_entry(dev->id, i);
2349 static int ioapic_resume(struct sys_device *dev)
2351 struct IO_APIC_route_entry *entry;
2352 struct sysfs_ioapic_data *data;
2353 unsigned long flags;
2354 union IO_APIC_reg_00 reg_00;
2357 data = container_of(dev, struct sysfs_ioapic_data, dev);
2358 entry = data->entry;
2360 spin_lock_irqsave(&ioapic_lock, flags);
2361 reg_00.raw = io_apic_read(dev->id, 0);
2362 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2363 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2364 io_apic_write(dev->id, 0, reg_00.raw);
2366 spin_unlock_irqrestore(&ioapic_lock, flags);
2367 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2368 ioapic_write_entry(dev->id, i, entry[i]);
2373 static struct sysdev_class ioapic_sysdev_class = {
2375 .suspend = ioapic_suspend,
2376 .resume = ioapic_resume,
2379 static int __init ioapic_init_sysfs(void)
2381 struct sys_device * dev;
2382 int i, size, error = 0;
2384 error = sysdev_class_register(&ioapic_sysdev_class);
2388 for (i = 0; i < nr_ioapics; i++ ) {
2389 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2390 * sizeof(struct IO_APIC_route_entry);
2391 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2392 if (!mp_ioapic_data[i]) {
2393 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2396 memset(mp_ioapic_data[i], 0, size);
2397 dev = &mp_ioapic_data[i]->dev;
2399 dev->cls = &ioapic_sysdev_class;
2400 error = sysdev_register(dev);
2402 kfree(mp_ioapic_data[i]);
2403 mp_ioapic_data[i] = NULL;
2404 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2412 device_initcall(ioapic_init_sysfs);
2415 * Dynamic irq allocate and deallocation
2417 int create_irq(void)
2419 /* Allocate an unused irq */
2420 int irq, new, vector = 0;
2421 unsigned long flags;
2424 spin_lock_irqsave(&vector_lock, flags);
2425 for (new = (NR_IRQS - 1); new >= 0; new--) {
2426 if (platform_legacy_irq(new))
2428 if (irq_vector[new] != 0)
2430 vector = __assign_irq_vector(new);
2431 if (likely(vector > 0))
2435 spin_unlock_irqrestore(&vector_lock, flags);
2438 set_intr_gate(vector, interrupt[irq]);
2439 dynamic_irq_init(irq);
2444 void destroy_irq(unsigned int irq)
2446 unsigned long flags;
2448 dynamic_irq_cleanup(irq);
2450 spin_lock_irqsave(&vector_lock, flags);
2451 clear_bit(irq_vector[irq], used_vectors);
2452 irq_vector[irq] = 0;
2453 spin_unlock_irqrestore(&vector_lock, flags);
2457 * MSI message composition
2459 #ifdef CONFIG_PCI_MSI
2460 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2465 vector = assign_irq_vector(irq);
2467 dest = cpu_mask_to_apicid(TARGET_CPUS);
2469 msg->address_hi = MSI_ADDR_BASE_HI;
2472 ((INT_DEST_MODE == 0) ?
2473 MSI_ADDR_DEST_MODE_PHYSICAL:
2474 MSI_ADDR_DEST_MODE_LOGICAL) |
2475 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2476 MSI_ADDR_REDIRECTION_CPU:
2477 MSI_ADDR_REDIRECTION_LOWPRI) |
2478 MSI_ADDR_DEST_ID(dest);
2481 MSI_DATA_TRIGGER_EDGE |
2482 MSI_DATA_LEVEL_ASSERT |
2483 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2484 MSI_DATA_DELIVERY_FIXED:
2485 MSI_DATA_DELIVERY_LOWPRI) |
2486 MSI_DATA_VECTOR(vector);
2492 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2499 cpus_and(tmp, mask, cpu_online_map);
2500 if (cpus_empty(tmp))
2503 vector = assign_irq_vector(irq);
2507 dest = cpu_mask_to_apicid(mask);
2509 read_msi_msg(irq, &msg);
2511 msg.data &= ~MSI_DATA_VECTOR_MASK;
2512 msg.data |= MSI_DATA_VECTOR(vector);
2513 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2514 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2516 write_msi_msg(irq, &msg);
2517 irq_desc[irq].affinity = mask;
2519 #endif /* CONFIG_SMP */
2522 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2523 * which implement the MSI or MSI-X Capability Structure.
2525 static struct irq_chip msi_chip = {
2527 .unmask = unmask_msi_irq,
2528 .mask = mask_msi_irq,
2529 .ack = ack_ioapic_irq,
2531 .set_affinity = set_msi_irq_affinity,
2533 .retrigger = ioapic_retrigger_irq,
2536 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2544 ret = msi_compose_msg(dev, irq, &msg);
2550 set_irq_msi(irq, desc);
2551 write_msi_msg(irq, &msg);
2553 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2559 void arch_teardown_msi_irq(unsigned int irq)
2564 #endif /* CONFIG_PCI_MSI */
2567 * Hypertransport interrupt support
2569 #ifdef CONFIG_HT_IRQ
2573 static void target_ht_irq(unsigned int irq, unsigned int dest)
2575 struct ht_irq_msg msg;
2576 fetch_ht_irq_msg(irq, &msg);
2578 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2579 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2581 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2582 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2584 write_ht_irq_msg(irq, &msg);
2587 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2592 cpus_and(tmp, mask, cpu_online_map);
2593 if (cpus_empty(tmp))
2596 cpus_and(mask, tmp, CPU_MASK_ALL);
2598 dest = cpu_mask_to_apicid(mask);
2600 target_ht_irq(irq, dest);
2601 irq_desc[irq].affinity = mask;
2605 static struct irq_chip ht_irq_chip = {
2607 .mask = mask_ht_irq,
2608 .unmask = unmask_ht_irq,
2609 .ack = ack_ioapic_irq,
2611 .set_affinity = set_ht_irq_affinity,
2613 .retrigger = ioapic_retrigger_irq,
2616 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2620 vector = assign_irq_vector(irq);
2622 struct ht_irq_msg msg;
2627 cpu_set(vector >> 8, tmp);
2628 dest = cpu_mask_to_apicid(tmp);
2630 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2634 HT_IRQ_LOW_DEST_ID(dest) |
2635 HT_IRQ_LOW_VECTOR(vector) |
2636 ((INT_DEST_MODE == 0) ?
2637 HT_IRQ_LOW_DM_PHYSICAL :
2638 HT_IRQ_LOW_DM_LOGICAL) |
2639 HT_IRQ_LOW_RQEOI_EDGE |
2640 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2641 HT_IRQ_LOW_MT_FIXED :
2642 HT_IRQ_LOW_MT_ARBITRATED) |
2643 HT_IRQ_LOW_IRQ_MASKED;
2645 write_ht_irq_msg(irq, &msg);
2647 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2648 handle_edge_irq, "edge");
2652 #endif /* CONFIG_HT_IRQ */
2654 /* --------------------------------------------------------------------------
2655 ACPI-based IOAPIC Configuration
2656 -------------------------------------------------------------------------- */
2660 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2662 union IO_APIC_reg_00 reg_00;
2663 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2665 unsigned long flags;
2669 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2670 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2671 * supports up to 16 on one shared APIC bus.
2673 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2674 * advantage of new APIC bus architecture.
2677 if (physids_empty(apic_id_map))
2678 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2680 spin_lock_irqsave(&ioapic_lock, flags);
2681 reg_00.raw = io_apic_read(ioapic, 0);
2682 spin_unlock_irqrestore(&ioapic_lock, flags);
2684 if (apic_id >= get_physical_broadcast()) {
2685 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2686 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2687 apic_id = reg_00.bits.ID;
2691 * Every APIC in a system must have a unique ID or we get lots of nice
2692 * 'stuck on smp_invalidate_needed IPI wait' messages.
2694 if (check_apicid_used(apic_id_map, apic_id)) {
2696 for (i = 0; i < get_physical_broadcast(); i++) {
2697 if (!check_apicid_used(apic_id_map, i))
2701 if (i == get_physical_broadcast())
2702 panic("Max apic_id exceeded!\n");
2704 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2705 "trying %d\n", ioapic, apic_id, i);
2710 tmp = apicid_to_cpu_present(apic_id);
2711 physids_or(apic_id_map, apic_id_map, tmp);
2713 if (reg_00.bits.ID != apic_id) {
2714 reg_00.bits.ID = apic_id;
2716 spin_lock_irqsave(&ioapic_lock, flags);
2717 io_apic_write(ioapic, 0, reg_00.raw);
2718 reg_00.raw = io_apic_read(ioapic, 0);
2719 spin_unlock_irqrestore(&ioapic_lock, flags);
2722 if (reg_00.bits.ID != apic_id) {
2723 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2728 apic_printk(APIC_VERBOSE, KERN_INFO
2729 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2735 int __init io_apic_get_version (int ioapic)
2737 union IO_APIC_reg_01 reg_01;
2738 unsigned long flags;
2740 spin_lock_irqsave(&ioapic_lock, flags);
2741 reg_01.raw = io_apic_read(ioapic, 1);
2742 spin_unlock_irqrestore(&ioapic_lock, flags);
2744 return reg_01.bits.version;
2748 int __init io_apic_get_redir_entries (int ioapic)
2750 union IO_APIC_reg_01 reg_01;
2751 unsigned long flags;
2753 spin_lock_irqsave(&ioapic_lock, flags);
2754 reg_01.raw = io_apic_read(ioapic, 1);
2755 spin_unlock_irqrestore(&ioapic_lock, flags);
2757 return reg_01.bits.entries;
2761 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2763 struct IO_APIC_route_entry entry;
2765 if (!IO_APIC_IRQ(irq)) {
2766 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2772 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2773 * Note that we mask (disable) IRQs now -- these get enabled when the
2774 * corresponding device driver registers for this IRQ.
2777 memset(&entry,0,sizeof(entry));
2779 entry.delivery_mode = INT_DELIVERY_MODE;
2780 entry.dest_mode = INT_DEST_MODE;
2781 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2782 entry.trigger = edge_level;
2783 entry.polarity = active_high_low;
2787 * IRQs < 16 are already in the irq_2_pin[] map
2790 add_pin_to_irq(irq, ioapic, pin);
2792 entry.vector = assign_irq_vector(irq);
2794 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2795 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2796 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2797 edge_level, active_high_low);
2799 ioapic_register_intr(irq, entry.vector, edge_level);
2801 if (!ioapic && (irq < 16))
2802 disable_8259A_irq(irq);
2804 ioapic_write_entry(ioapic, pin, entry);
2809 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2813 if (skip_ioapic_setup)
2816 for (i = 0; i < mp_irq_entries; i++)
2817 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2818 mp_irqs[i].mpc_srcbusirq == bus_irq)
2820 if (i >= mp_irq_entries)
2823 *trigger = irq_trigger(i);
2824 *polarity = irq_polarity(i);
2828 #endif /* CONFIG_ACPI */
2830 static int __init parse_disable_timer_pin_1(char *arg)
2832 disable_timer_pin_1 = 1;
2835 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2837 static int __init parse_enable_timer_pin_1(char *arg)
2839 disable_timer_pin_1 = -1;
2842 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2844 static int __init parse_noapic(char *arg)
2846 /* disable IO-APIC */
2847 disable_ioapic_setup();
2850 early_param("noapic", parse_noapic);