arch/x86/kernel/microcode_amd.c

   1 /*
   2  *  AMD CPU Microcode Update Driver for Linux
   3  *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
   4  *
   5  *  Author: Peter Oruba <peter.oruba@amd.com>
   6  *
   7  *  Based on work by:
   8  *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
   9  *
  10  *  Maintainers:
  11  *  Andreas Herrmann <herrmann.der.user@googlemail.com>
  12  *  Borislav Petkov <bp@alien8.de>
  13  *
  14  *  This driver allows to upgrade microcode on F10h AMD
  15  *  CPUs and later.
  16  *
  17  *  Licensed under the terms of the GNU General Public
  18  *  License version 2. See file COPYING for details.
  19  */
  20
  21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22
  23 #include <linux/firmware.h>
  24 #include <linux/pci_ids.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30
  31 #include <asm/microcode.h>
  32 #include <asm/processor.h>
  33 #include <asm/msr.h>
  34 #include <asm/microcode_amd.h>
  35
  36 MODULE_DESCRIPTION("AMD Microcode Update Driver");
  37 MODULE_AUTHOR("Peter Oruba");
  38 MODULE_LICENSE("GPL v2");
  39
  40 static struct equiv_cpu_entry *equiv_cpu_table;
  41
  42 struct ucode_patch {
  43         struct list_head plist;
  44         void *data;
  45         u32 patch_id;
  46         u16 equiv_cpu;
  47 };
  48
  49 static LIST_HEAD(pcache);
  50
  51 static u16 __find_equiv_id(unsigned int cpu)
  52 {
  53         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  54         return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
  55 }
  56
  57 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
  58 {
  59         int i = 0;
  60
  61         BUG_ON(!equiv_cpu_table);
  62
  63         while (equiv_cpu_table[i].equiv_cpu != 0) {
  64                 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
  65                         return equiv_cpu_table[i].installed_cpu;
  66                 i++;
  67         }
  68         return 0;
  69 }
  70
  71 /*
  72  * a small, trivial cache of per-family ucode patches
  73  */
  74 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
  75 {
  76         struct ucode_patch *p;
  77
  78         list_for_each_entry(p, &pcache, plist)
  79                 if (p->equiv_cpu == equiv_cpu)
  80                         return p;
  81         return NULL;
  82 }
  83
  84 static void update_cache(struct ucode_patch *new_patch)
  85 {
  86         struct ucode_patch *p;
  87
  88         list_for_each_entry(p, &pcache, plist) {
  89                 if (p->equiv_cpu == new_patch->equiv_cpu) {
  90                         if (p->patch_id >= new_patch->patch_id)
  91                                 /* we already have the latest patch */
  92                                 return;
  93
  94                         list_replace(&p->plist, &new_patch->plist);
  95                         kfree(p->data);
  96                         kfree(p);
  97                         return;
  98                 }
  99         }
 100         /* no patch found, add it */
 101         list_add_tail(&new_patch->plist, &pcache);
 102 }
 103
 104 static void free_cache(void)
 105 {
 106         struct ucode_patch *p, *tmp;
 107
 108         list_for_each_entry_safe(p, tmp, &pcache, plist) {
 109                 __list_del(p->plist.prev, p->plist.next);
 110                 kfree(p->data);
 111                 kfree(p);
 112         }
 113 }
 114
 115 static struct ucode_patch *find_patch(unsigned int cpu)
 116 {
 117         u16 equiv_id;
 118
 119         equiv_id = __find_equiv_id(cpu);
 120         if (!equiv_id)
 121                 return NULL;
 122
 123         return cache_find_patch(equiv_id);
 124 }
 125
 126 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 127 {
 128         struct cpuinfo_x86 *c = &cpu_data(cpu);
 129         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
 130         struct ucode_patch *p;
 131
 132         csig->sig = cpuid_eax(0x00000001);
 133         csig->rev = c->microcode;
 134
 135         /*
 136          * a patch could have been loaded early, set uci->mc so that
 137          * mc_bp_resume() can call apply_microcode()
 138          */
 139         p = find_patch(cpu);
 140         if (p && (p->patch_id == csig->rev))
 141                 uci->mc = p->data;
 142
 143         pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
 144
 145         return 0;
 146 }
 147
 148 static unsigned int verify_patch_size(u8 family, u32 patch_size,
 149                                       unsigned int size)
 150 {
 151         u32 max_size;
 152
 153 #define F1XH_MPB_MAX_SIZE 2048
 154 #define F14H_MPB_MAX_SIZE 1824
 155 #define F15H_MPB_MAX_SIZE 4096
 156 #define F16H_MPB_MAX_SIZE 3458
 157
 158         switch (family) {
 159         case 0x14:
 160                 max_size = F14H_MPB_MAX_SIZE;
 161                 break;
 162         case 0x15:
 163                 max_size = F15H_MPB_MAX_SIZE;
 164                 break;
 165         case 0x16:
 166                 max_size = F16H_MPB_MAX_SIZE;
 167                 break;
 168         default:
 169                 max_size = F1XH_MPB_MAX_SIZE;
 170                 break;
 171         }
 172
 173         if (patch_size > min_t(u32, size, max_size)) {
 174                 pr_err("patch size mismatch\n");
 175                 return 0;
 176         }
 177
 178         return patch_size;
 179 }
 180
 181 int __apply_microcode_amd(struct microcode_amd *mc_amd)
 182 {
 183         u32 rev, dummy;
 184
 185         wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
 186
 187         /* verify patch application was successful */
 188         rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
 189         if (rev != mc_amd->hdr.patch_id)
 190                 return -1;
 191
 192         return 0;
 193 }
 194
 195 int apply_microcode_amd(int cpu)
 196 {
 197         struct cpuinfo_x86 *c = &cpu_data(cpu);
 198         struct microcode_amd *mc_amd;
 199         struct ucode_cpu_info *uci;
 200         struct ucode_patch *p;
 201         u32 rev, dummy;
 202
 203         BUG_ON(raw_smp_processor_id() != cpu);
 204
 205         uci = ucode_cpu_info + cpu;
 206
 207         p = find_patch(cpu);
 208         if (!p)
 209                 return 0;
 210
 211         mc_amd  = p->data;
 212         uci->mc = p->data;
 213
 214         rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
 215
 216         /* need to apply patch? */
 217         if (rev >= mc_amd->hdr.patch_id) {
 218                 c->microcode = rev;
 219                 return 0;
 220         }
 221
 222         if (__apply_microcode_amd(mc_amd)) {
 223                 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
 224                         cpu, mc_amd->hdr.patch_id);
 225                 return -1;
 226         }
 227         pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
 228                 mc_amd->hdr.patch_id);
 229
 230         uci->cpu_sig.rev = mc_amd->hdr.patch_id;
 231         c->microcode = mc_amd->hdr.patch_id;
 232
 233         return 0;
 234 }
 235
 236 static int install_equiv_cpu_table(const u8 *buf)
 237 {
 238         unsigned int *ibuf = (unsigned int *)buf;
 239         unsigned int type = ibuf[1];
 240         unsigned int size = ibuf[2];
 241
 242         if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
 243                 pr_err("empty section/"
 244                        "invalid type field in container file section header\n");
 245                 return -EINVAL;
 246         }
 247
 248         equiv_cpu_table = vmalloc(size);
 249         if (!equiv_cpu_table) {
 250                 pr_err("failed to allocate equivalent CPU table\n");
 251                 return -ENOMEM;
 252         }
 253
 254         memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
 255
 256         /* add header length */
 257         return size + CONTAINER_HDR_SZ;
 258 }
 259
 260 static void free_equiv_cpu_table(void)
 261 {
 262         vfree(equiv_cpu_table);
 263         equiv_cpu_table = NULL;
 264 }
 265
 266 static void cleanup(void)
 267 {
 268         free_equiv_cpu_table();
 269         free_cache();
 270 }
 271
 272 /*
 273  * We return the current size even if some of the checks failed so that
 274  * we can skip over the next patch. If we return a negative value, we
 275  * signal a grave error like a memory allocation has failed and the
 276  * driver cannot continue functioning normally. In such cases, we tear
 277  * down everything we've used up so far and exit.
 278  */
 279 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
 280 {
 281         struct microcode_header_amd *mc_hdr;
 282         struct ucode_patch *patch;
 283         unsigned int patch_size, crnt_size, ret;
 284         u32 proc_fam;
 285         u16 proc_id;
 286
 287         patch_size  = *(u32 *)(fw + 4);
 288         crnt_size   = patch_size + SECTION_HDR_SIZE;
 289         mc_hdr      = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
 290         proc_id     = mc_hdr->processor_rev_id;
 291
 292         proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
 293         if (!proc_fam) {
 294                 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
 295                 return crnt_size;
 296         }
 297
 298         /* check if patch is for the current family */
 299         proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
 300         if (proc_fam != family)
 301                 return crnt_size;
 302
 303         if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
 304                 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
 305                         mc_hdr->patch_id);
 306                 return crnt_size;
 307         }
 308
 309         ret = verify_patch_size(family, patch_size, leftover);
 310         if (!ret) {
 311                 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
 312                 return crnt_size;
 313         }
 314
 315         patch = kzalloc(sizeof(*patch), GFP_KERNEL);
 316         if (!patch) {
 317                 pr_err("Patch allocation failure.\n");
 318                 return -EINVAL;
 319         }
 320
 321         patch->data = kzalloc(patch_size, GFP_KERNEL);
 322         if (!patch->data) {
 323                 pr_err("Patch data allocation failure.\n");
 324                 kfree(patch);
 325                 return -EINVAL;
 326         }
 327
 328         /* All looks ok, copy patch... */
 329         memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
 330         INIT_LIST_HEAD(&patch->plist);
 331         patch->patch_id  = mc_hdr->patch_id;
 332         patch->equiv_cpu = proc_id;
 333
 334         /* ... and add to cache. */
 335         update_cache(patch);
 336
 337         return crnt_size;
 338 }
 339
 340 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
 341                                              size_t size)
 342 {
 343         enum ucode_state ret = UCODE_ERROR;
 344         unsigned int leftover;
 345         u8 *fw = (u8 *)data;
 346         int crnt_size = 0;
 347         int offset;
 348
 349         offset = install_equiv_cpu_table(data);
 350         if (offset < 0) {
 351                 pr_err("failed to create equivalent cpu table\n");
 352                 return ret;
 353         }
 354         fw += offset;
 355         leftover = size - offset;
 356
 357         if (*(u32 *)fw != UCODE_UCODE_TYPE) {
 358                 pr_err("invalid type field in container file section header\n");
 359                 free_equiv_cpu_table();
 360                 return ret;
 361         }
 362
 363         while (leftover) {
 364                 crnt_size = verify_and_add_patch(family, fw, leftover);
 365                 if (crnt_size < 0)
 366                         return ret;
 367
 368                 fw       += crnt_size;
 369                 leftover -= crnt_size;
 370         }
 371
 372         return UCODE_OK;
 373 }
 374
 375 enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
 376 {
 377         enum ucode_state ret;
 378
 379         /* free old equiv table */
 380         free_equiv_cpu_table();
 381
 382         ret = __load_microcode_amd(family, data, size);
 383
 384         if (ret != UCODE_OK)
 385                 cleanup();
 386
 387 #if defined(CONFIG_MICROCODE_AMD_EARLY) && defined(CONFIG_X86_32)
 388         /* save BSP's matching patch for early load */
 389         if (cpu_data(smp_processor_id()).cpu_index == boot_cpu_data.cpu_index) {
 390                 struct ucode_patch *p = find_patch(smp_processor_id());
 391                 if (p) {
 392                         memset(amd_bsp_mpb, 0, MPB_MAX_SIZE);
 393                         memcpy(amd_bsp_mpb, p->data, min_t(u32, ksize(p->data),
 394                                                            MPB_MAX_SIZE));
 395                 }
 396         }
 397 #endif
 398         return ret;
 399 }
 400
 401 /*
 402  * AMD microcode firmware naming convention, up to family 15h they are in
 403  * the legacy file:
 404  *
 405  *    amd-ucode/microcode_amd.bin
 406  *
 407  * This legacy file is always smaller than 2K in size.
 408  *
 409  * Beginning with family 15h, they are in family-specific firmware files:
 410  *
 411  *    amd-ucode/microcode_amd_fam15h.bin
 412  *    amd-ucode/microcode_amd_fam16h.bin
 413  *    ...
 414  *
 415  * These might be larger than 2K.
 416  */
 417 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
 418                                               bool refresh_fw)
 419 {
 420         char fw_name[36] = "amd-ucode/microcode_amd.bin";
 421         struct cpuinfo_x86 *c = &cpu_data(cpu);
 422         enum ucode_state ret = UCODE_NFOUND;
 423         const struct firmware *fw;
 424
 425         /* reload ucode container only on the boot cpu */
 426         if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
 427                 return UCODE_OK;
 428
 429         if (c->x86 >= 0x15)
 430                 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
 431
 432         if (request_firmware(&fw, (const char *)fw_name, device)) {
 433                 pr_err("failed to load file %s\n", fw_name);
 434                 goto out;
 435         }
 436
 437         ret = UCODE_ERROR;
 438         if (*(u32 *)fw->data != UCODE_MAGIC) {
 439                 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
 440                 goto fw_release;
 441         }
 442
 443         ret = load_microcode_amd(c->x86, fw->data, fw->size);
 444
 445  fw_release:
 446         release_firmware(fw);
 447
 448  out:
 449         return ret;
 450 }
 451
 452 static enum ucode_state
 453 request_microcode_user(int cpu, const void __user *buf, size_t size)
 454 {
 455         return UCODE_ERROR;
 456 }
 457
 458 static void microcode_fini_cpu_amd(int cpu)
 459 {
 460         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
 461
 462         uci->mc = NULL;
 463 }
 464
 465 static struct microcode_ops microcode_amd_ops = {
 466         .request_microcode_user           = request_microcode_user,
 467         .request_microcode_fw             = request_microcode_amd,
 468         .collect_cpu_info                 = collect_cpu_info_amd,
 469         .apply_microcode                  = apply_microcode_amd,
 470         .microcode_fini_cpu               = microcode_fini_cpu_amd,
 471 };
 472
 473 struct microcode_ops * __init init_amd_microcode(void)
 474 {
 475         struct cpuinfo_x86 *c = &cpu_data(0);
 476
 477         if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
 478                 pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
 479                 return NULL;
 480         }
 481
 482         return &microcode_amd_ops;
 483 }
 484
 485 void __exit exit_amd_microcode(void)
 486 {
 487         cleanup();
 488 }