2 * AMD CPU Microcode Update Driver for Linux
3 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
5 * Author: Peter Oruba <peter.oruba@amd.com>
8 * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
11 * Andreas Herrmann <herrmann.der.user@googlemail.com>
12 * Borislav Petkov <bp@alien8.de>
14 * This driver allows to upgrade microcode on F10h AMD
17 * Licensed under the terms of the GNU General Public
18 * License version 2. See file COPYING for details.
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23 #include <linux/firmware.h>
24 #include <linux/pci_ids.h>
25 #include <linux/uaccess.h>
26 #include <linux/vmalloc.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
31 #include <asm/microcode.h>
32 #include <asm/processor.h>
35 MODULE_DESCRIPTION("AMD Microcode Update Driver");
36 MODULE_AUTHOR("Peter Oruba");
37 MODULE_LICENSE("GPL v2");
39 #define UCODE_MAGIC 0x00414d44
40 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
41 #define UCODE_UCODE_TYPE 0x00000001
43 struct equiv_cpu_entry {
45 u32 fixed_errata_mask;
46 u32 fixed_errata_compare;
49 } __attribute__((packed));
51 struct microcode_header_amd {
57 u32 mc_patch_data_checksum;
66 } __attribute__((packed));
68 struct microcode_amd {
69 struct microcode_header_amd hdr;
73 #define SECTION_HDR_SIZE 8
74 #define CONTAINER_HDR_SZ 12
76 static struct equiv_cpu_entry *equiv_cpu_table;
79 struct list_head plist;
85 static LIST_HEAD(pcache);
87 static u16 find_equiv_id(unsigned int cpu)
89 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
95 while (equiv_cpu_table[i].installed_cpu != 0) {
96 if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
97 return equiv_cpu_table[i].equiv_cpu;
104 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
108 BUG_ON(!equiv_cpu_table);
110 while (equiv_cpu_table[i].equiv_cpu != 0) {
111 if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
112 return equiv_cpu_table[i].installed_cpu;
119 * a small, trivial cache of per-family ucode patches
121 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
123 struct ucode_patch *p;
125 list_for_each_entry(p, &pcache, plist)
126 if (p->equiv_cpu == equiv_cpu)
131 static void update_cache(struct ucode_patch *new_patch)
133 struct ucode_patch *p;
135 list_for_each_entry(p, &pcache, plist) {
136 if (p->equiv_cpu == new_patch->equiv_cpu) {
137 if (p->patch_id >= new_patch->patch_id)
138 /* we already have the latest patch */
141 list_replace(&p->plist, &new_patch->plist);
147 /* no patch found, add it */
148 list_add_tail(&new_patch->plist, &pcache);
151 static void free_cache(void)
153 struct ucode_patch *p, *tmp;
155 list_for_each_entry_safe(p, tmp, &pcache, plist) {
156 __list_del(p->plist.prev, p->plist.next);
162 static struct ucode_patch *find_patch(unsigned int cpu)
166 equiv_id = find_equiv_id(cpu);
170 return cache_find_patch(equiv_id);
173 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
175 struct cpuinfo_x86 *c = &cpu_data(cpu);
177 csig->sig = cpuid_eax(0x00000001);
178 csig->rev = c->microcode;
179 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
184 static unsigned int verify_patch_size(int cpu, u32 patch_size,
187 struct cpuinfo_x86 *c = &cpu_data(cpu);
190 #define F1XH_MPB_MAX_SIZE 2048
191 #define F14H_MPB_MAX_SIZE 1824
192 #define F15H_MPB_MAX_SIZE 4096
193 #define F16H_MPB_MAX_SIZE 3458
197 max_size = F14H_MPB_MAX_SIZE;
200 max_size = F15H_MPB_MAX_SIZE;
203 max_size = F16H_MPB_MAX_SIZE;
206 max_size = F1XH_MPB_MAX_SIZE;
210 if (patch_size > min_t(u32, size, max_size)) {
211 pr_err("patch size mismatch\n");
218 static int apply_microcode_amd(int cpu)
220 struct cpuinfo_x86 *c = &cpu_data(cpu);
221 struct microcode_amd *mc_amd;
222 struct ucode_cpu_info *uci;
223 struct ucode_patch *p;
226 BUG_ON(raw_smp_processor_id() != cpu);
228 uci = ucode_cpu_info + cpu;
237 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
239 /* need to apply patch? */
240 if (rev >= mc_amd->hdr.patch_id) {
245 wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
247 /* verify patch application was successful */
248 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
249 if (rev != mc_amd->hdr.patch_id) {
250 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
251 cpu, mc_amd->hdr.patch_id);
255 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
256 uci->cpu_sig.rev = rev;
262 static int install_equiv_cpu_table(const u8 *buf)
264 unsigned int *ibuf = (unsigned int *)buf;
265 unsigned int type = ibuf[1];
266 unsigned int size = ibuf[2];
268 if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
269 pr_err("empty section/"
270 "invalid type field in container file section header\n");
274 equiv_cpu_table = vmalloc(size);
275 if (!equiv_cpu_table) {
276 pr_err("failed to allocate equivalent CPU table\n");
280 memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
282 /* add header length */
283 return size + CONTAINER_HDR_SZ;
286 static void free_equiv_cpu_table(void)
288 vfree(equiv_cpu_table);
289 equiv_cpu_table = NULL;
292 static void cleanup(void)
294 free_equiv_cpu_table();
299 * We return the current size even if some of the checks failed so that
300 * we can skip over the next patch. If we return a negative value, we
301 * signal a grave error like a memory allocation has failed and the
302 * driver cannot continue functioning normally. In such cases, we tear
303 * down everything we've used up so far and exit.
305 static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
307 struct cpuinfo_x86 *c = &cpu_data(cpu);
308 struct microcode_header_amd *mc_hdr;
309 struct ucode_patch *patch;
310 unsigned int patch_size, crnt_size, ret;
314 patch_size = *(u32 *)(fw + 4);
315 crnt_size = patch_size + SECTION_HDR_SIZE;
316 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
317 proc_id = mc_hdr->processor_rev_id;
319 proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
321 pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
325 /* check if patch is for the current family */
326 proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
327 if (proc_fam != c->x86)
330 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
331 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
336 ret = verify_patch_size(cpu, patch_size, leftover);
338 pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
342 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
344 pr_err("Patch allocation failure.\n");
348 patch->data = kzalloc(patch_size, GFP_KERNEL);
350 pr_err("Patch data allocation failure.\n");
355 /* All looks ok, copy patch... */
356 memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
357 INIT_LIST_HEAD(&patch->plist);
358 patch->patch_id = mc_hdr->patch_id;
359 patch->equiv_cpu = proc_id;
361 /* ... and add to cache. */
367 static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
369 enum ucode_state ret = UCODE_ERROR;
370 unsigned int leftover;
375 offset = install_equiv_cpu_table(data);
377 pr_err("failed to create equivalent cpu table\n");
381 leftover = size - offset;
383 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
384 pr_err("invalid type field in container file section header\n");
385 free_equiv_cpu_table();
390 crnt_size = verify_and_add_patch(cpu, fw, leftover);
395 leftover -= crnt_size;
402 * AMD microcode firmware naming convention, up to family 15h they are in
405 * amd-ucode/microcode_amd.bin
407 * This legacy file is always smaller than 2K in size.
409 * Beginning with family 15h, they are in family-specific firmware files:
411 * amd-ucode/microcode_amd_fam15h.bin
412 * amd-ucode/microcode_amd_fam16h.bin
415 * These might be larger than 2K.
417 static enum ucode_state request_microcode_amd(int cpu, struct device *device,
420 char fw_name[36] = "amd-ucode/microcode_amd.bin";
421 struct cpuinfo_x86 *c = &cpu_data(cpu);
422 enum ucode_state ret = UCODE_NFOUND;
423 const struct firmware *fw;
425 /* reload ucode container only on the boot cpu */
426 if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
430 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
432 if (request_firmware(&fw, (const char *)fw_name, device)) {
433 pr_err("failed to load file %s\n", fw_name);
438 if (*(u32 *)fw->data != UCODE_MAGIC) {
439 pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
443 /* free old equiv table */
444 free_equiv_cpu_table();
446 ret = load_microcode_amd(cpu, fw->data, fw->size);
451 release_firmware(fw);
457 static enum ucode_state
458 request_microcode_user(int cpu, const void __user *buf, size_t size)
463 static void microcode_fini_cpu_amd(int cpu)
465 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
470 static struct microcode_ops microcode_amd_ops = {
471 .request_microcode_user = request_microcode_user,
472 .request_microcode_fw = request_microcode_amd,
473 .collect_cpu_info = collect_cpu_info_amd,
474 .apply_microcode = apply_microcode_amd,
475 .microcode_fini_cpu = microcode_fini_cpu_amd,
478 struct microcode_ops * __init init_amd_microcode(void)
480 struct cpuinfo_x86 *c = &cpu_data(0);
482 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
483 pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
487 return µcode_amd_ops;
490 void __exit exit_amd_microcode(void)