2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/acpi.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/bitops.h>
28 #include <asm/mpspec.h>
29 #include <asm/io_apic.h>
30 #include <asm/bios_ebda.h>
32 #include <mach_apic.h>
33 #include <mach_apicdef.h>
34 #include <mach_mpparse.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
45 int mp_bus_id_to_type [MAX_MP_BUSSES];
47 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
48 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49 static int mp_current_pci_id;
51 /* I/O APIC entries */
52 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
54 /* # of MP IRQ source entries */
55 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
57 /* MP IRQ source entries */
64 /* Make it easy to share the UP and SMP code: */
65 #ifndef CONFIG_X86_SMP
66 unsigned int num_processors;
67 unsigned disabled_cpus __cpuinitdata;
68 #ifndef CONFIG_X86_LOCAL_APIC
69 unsigned int boot_cpu_physical_apicid = -1U;
73 /* Make it easy to share the UP and SMP code: */
74 #ifndef CONFIG_X86_SMP
75 physid_mask_t phys_cpu_present_map;
79 * Intel MP BIOS table parsing routines:
84 * Checksum an MP configuration block.
87 static int __init mpf_checksum(unsigned char *mp, int len)
97 #ifdef CONFIG_X86_NUMAQ
99 * Have to match translation table entries to main table entries by counter
100 * hence the mpc_record variable .... can't see a less disgusting way of
104 static int mpc_record;
105 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __cpuinitdata;
108 static void __cpuinit generic_processor_info(int apicid, int version)
112 physid_mask_t phys_cpu;
117 if (version == 0x0) {
118 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
119 "fixing up to 0x10. (tell your hw vendor)\n",
123 apic_version[apicid] = version;
125 phys_cpu = apicid_to_cpu_present(apicid);
126 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
128 if (num_processors >= NR_CPUS) {
129 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
130 " Processor ignored.\n", NR_CPUS);
134 if (num_processors >= maxcpus) {
135 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
136 " Processor ignored.\n", maxcpus);
141 cpus_complement(tmp_map, cpu_present_map);
142 cpu = first_cpu(tmp_map);
144 if (apicid == boot_cpu_physical_apicid)
146 * x86_bios_cpu_apicid is required to have processors listed
147 * in same order as logical cpu numbers. Hence the first
148 * entry is BSP, and so on.
153 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
154 * but we need to work other dependencies like SMP_SUSPEND etc
155 * before this can be done without some confusion.
156 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
157 * - Ashok Raj <ashok.raj@intel.com>
159 if (num_processors > 8) {
160 switch (boot_cpu_data.x86_vendor) {
161 case X86_VENDOR_INTEL:
162 if (!APIC_XAPIC(version)) {
166 /* If P4 and above fall through */
172 /* are we being called early in kernel startup? */
173 if (x86_cpu_to_apicid_early_ptr) {
174 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
175 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
177 cpu_to_apicid[cpu] = apicid;
178 bios_cpu_apicid[cpu] = apicid;
180 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
181 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
184 cpu_set(cpu, cpu_possible_map);
185 cpu_set(cpu, cpu_present_map);
188 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
192 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
193 #ifdef CONFIG_X86_SMP
199 #ifdef CONFIG_X86_NUMAQ
200 apicid = mpc_apic_id(m, translation_table[mpc_record]);
202 Dprintk("Processor #%d %u:%u APIC version %d\n",
204 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
205 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
207 apicid = m->mpc_apicid;
210 if (m->mpc_featureflag&(1<<0))
211 Dprintk(" Floating point unit present.\n");
212 if (m->mpc_featureflag&(1<<7))
213 Dprintk(" Machine Exception supported.\n");
214 if (m->mpc_featureflag&(1<<8))
215 Dprintk(" 64 bit compare & exchange supported.\n");
216 if (m->mpc_featureflag&(1<<9))
217 Dprintk(" Internal APIC present.\n");
218 if (m->mpc_featureflag&(1<<11))
219 Dprintk(" SEP present.\n");
220 if (m->mpc_featureflag&(1<<12))
221 Dprintk(" MTRR present.\n");
222 if (m->mpc_featureflag&(1<<13))
223 Dprintk(" PGE present.\n");
224 if (m->mpc_featureflag&(1<<14))
225 Dprintk(" MCA present.\n");
226 if (m->mpc_featureflag&(1<<15))
227 Dprintk(" CMOV present.\n");
228 if (m->mpc_featureflag&(1<<16))
229 Dprintk(" PAT present.\n");
230 if (m->mpc_featureflag&(1<<17))
231 Dprintk(" PSE present.\n");
232 if (m->mpc_featureflag&(1<<18))
233 Dprintk(" PSN present.\n");
234 if (m->mpc_featureflag&(1<<19))
235 Dprintk(" Cache Line Flush Instruction present.\n");
237 if (m->mpc_featureflag&(1<<21))
238 Dprintk(" Debug Trace and EMON Store present.\n");
239 if (m->mpc_featureflag&(1<<22))
240 Dprintk(" ACPI Thermal Throttle Registers present.\n");
241 if (m->mpc_featureflag&(1<<23))
242 Dprintk(" MMX present.\n");
243 if (m->mpc_featureflag&(1<<24))
244 Dprintk(" FXSR present.\n");
245 if (m->mpc_featureflag&(1<<25))
246 Dprintk(" XMM present.\n");
247 if (m->mpc_featureflag&(1<<26))
248 Dprintk(" Willamette New Instructions present.\n");
249 if (m->mpc_featureflag&(1<<27))
250 Dprintk(" Self Snoop present.\n");
251 if (m->mpc_featureflag&(1<<28))
252 Dprintk(" HT present.\n");
253 if (m->mpc_featureflag&(1<<29))
254 Dprintk(" Thermal Monitor present.\n");
255 /* 30, 31 Reserved */
258 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
259 Dprintk(" Bootup CPU\n");
260 boot_cpu_physical_apicid = m->mpc_apicid;
263 generic_processor_info(apicid, m->mpc_apicver);
266 static void __init MP_bus_info (struct mpc_config_bus *m)
270 memcpy(str, m->mpc_bustype, 6);
273 #ifdef CONFIG_X86_NUMAQ
274 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
276 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
279 #if MAX_MP_BUSSES < 256
280 if (m->mpc_busid >= MAX_MP_BUSSES) {
281 printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
282 " is too large, max. supported is %d\n",
283 m->mpc_busid, str, MAX_MP_BUSSES - 1);
288 set_bit(m->mpc_busid, mp_bus_not_pci);
289 if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
290 #ifdef CONFIG_X86_NUMAQ
291 mpc_oem_pci_bus(m, translation_table[mpc_record]);
293 clear_bit(m->mpc_busid, mp_bus_not_pci);
294 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
296 #if defined(CONFIG_EISA) || defined (CONFIG_MCA)
297 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
298 } else if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
299 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
300 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
301 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
302 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
303 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
305 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
310 static int bad_ioapic(unsigned long address)
312 if (nr_ioapics >= MAX_IO_APICS) {
313 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
314 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
315 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
318 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
319 " found in table, skipping!\n");
325 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
327 if (!(m->mpc_flags & MPC_APIC_USABLE))
330 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
331 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
333 if (bad_ioapic(m->mpc_apicaddr))
336 mp_ioapics[nr_ioapics] = *m;
340 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
342 mp_irqs [mp_irq_entries] = *m;
343 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
344 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
345 m->mpc_irqtype, m->mpc_irqflag & 3,
346 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
347 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
348 if (++mp_irq_entries == MAX_IRQ_SOURCES)
349 panic("Max # of irq sources exceeded!!\n");
352 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
354 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
355 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
356 m->mpc_irqtype, m->mpc_irqflag & 3,
357 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
358 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
361 #ifdef CONFIG_X86_NUMAQ
362 static void __init MP_translation_info (struct mpc_config_translation *m)
364 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
366 if (mpc_record >= MAX_MPC_ENTRY)
367 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
369 translation_table[mpc_record] = m; /* stash this for later */
370 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
371 node_set_online(m->trans_quad);
375 * Read/parse the MPC oem tables
378 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
379 unsigned short oemsize)
381 int count = sizeof (*oemtable); /* the header size */
382 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
385 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
386 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
388 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
389 oemtable->oem_signature[0],
390 oemtable->oem_signature[1],
391 oemtable->oem_signature[2],
392 oemtable->oem_signature[3]);
395 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
397 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
400 while (count < oemtable->oem_length) {
404 struct mpc_config_translation *m=
405 (struct mpc_config_translation *)oemptr;
406 MP_translation_info(m);
407 oemptr += sizeof(*m);
414 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
421 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
424 if (strncmp(oem, "IBM NUMA", 8))
425 printk("Warning! May not be a NUMA-Q system!\n");
427 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
430 #endif /* CONFIG_X86_NUMAQ */
436 static int __init smp_read_mpc(struct mp_config_table *mpc)
440 int count=sizeof(*mpc);
441 unsigned char *mpt=((unsigned char *)mpc)+count;
443 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
444 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
445 *(u32 *)mpc->mpc_signature);
448 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
449 printk(KERN_ERR "SMP mptable: checksum error!\n");
452 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
453 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
457 if (!mpc->mpc_lapic) {
458 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
461 memcpy(oem,mpc->mpc_oem,8);
463 printk(KERN_INFO "OEM ID: %s ",oem);
465 memcpy(str,mpc->mpc_productid,12);
467 printk("Product ID: %s ",str);
469 mps_oem_check(mpc, oem, str);
471 printk("APIC at: 0x%X\n", mpc->mpc_lapic);
474 * Save the local APIC address (it might be non-default) -- but only
475 * if we're not using ACPI.
478 mp_lapic_addr = mpc->mpc_lapic;
481 * Now process the configuration blocks.
483 #ifdef CONFIG_X86_NUMAQ
486 while (count < mpc->mpc_length) {
490 struct mpc_config_processor *m=
491 (struct mpc_config_processor *)mpt;
492 /* ACPI may have already provided this data */
494 MP_processor_info(m);
501 struct mpc_config_bus *m=
502 (struct mpc_config_bus *)mpt;
510 struct mpc_config_ioapic *m=
511 (struct mpc_config_ioapic *)mpt;
519 struct mpc_config_intsrc *m=
520 (struct mpc_config_intsrc *)mpt;
529 struct mpc_config_lintsrc *m=
530 (struct mpc_config_lintsrc *)mpt;
538 count = mpc->mpc_length;
542 #ifdef CONFIG_X86_NUMAQ
546 setup_apic_routing();
548 printk(KERN_ERR "SMP mptable: no processors registered!\n");
549 return num_processors;
552 static int __init ELCR_trigger(unsigned int irq)
556 port = 0x4d0 + (irq >> 3);
557 return (inb(port) >> (irq & 7)) & 1;
560 static void __init construct_default_ioirq_mptable(int mpc_default_type)
562 struct mpc_config_intsrc intsrc;
564 int ELCR_fallback = 0;
566 intsrc.mpc_type = MP_INTSRC;
567 intsrc.mpc_irqflag = 0; /* conforming */
568 intsrc.mpc_srcbus = 0;
569 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
571 intsrc.mpc_irqtype = mp_INT;
574 * If true, we have an ISA/PCI system with no IRQ entries
575 * in the MP table. To prevent the PCI interrupts from being set up
576 * incorrectly, we try to use the ELCR. The sanity check to see if
577 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
578 * never be level sensitive, so we simply see if the ELCR agrees.
579 * If it does, we assume it's valid.
581 if (mpc_default_type == 5) {
582 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
584 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
585 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
587 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
592 for (i = 0; i < 16; i++) {
593 switch (mpc_default_type) {
595 if (i == 0 || i == 13)
596 continue; /* IRQ0 & IRQ13 not connected */
600 continue; /* IRQ2 is never connected */
605 * If the ELCR indicates a level-sensitive interrupt, we
606 * copy that information over to the MP table in the
607 * irqflag field (level sensitive, active high polarity).
610 intsrc.mpc_irqflag = 13;
612 intsrc.mpc_irqflag = 0;
615 intsrc.mpc_srcbusirq = i;
616 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
617 MP_intsrc_info(&intsrc);
620 intsrc.mpc_irqtype = mp_ExtINT;
621 intsrc.mpc_srcbusirq = 0;
622 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
623 MP_intsrc_info(&intsrc);
626 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
628 struct mpc_config_processor processor;
629 struct mpc_config_bus bus;
630 struct mpc_config_ioapic ioapic;
631 struct mpc_config_lintsrc lintsrc;
632 int linttypes[2] = { mp_ExtINT, mp_NMI };
636 * local APIC has default address
638 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
641 * 2 CPUs, numbered 0 & 1.
643 processor.mpc_type = MP_PROCESSOR;
644 /* Either an integrated APIC or a discrete 82489DX. */
645 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
646 processor.mpc_cpuflag = CPU_ENABLED;
647 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
648 (boot_cpu_data.x86_model << 4) |
649 boot_cpu_data.x86_mask;
650 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
651 processor.mpc_reserved[0] = 0;
652 processor.mpc_reserved[1] = 0;
653 for (i = 0; i < 2; i++) {
654 processor.mpc_apicid = i;
655 MP_processor_info(&processor);
658 bus.mpc_type = MP_BUS;
660 switch (mpc_default_type) {
663 printk(KERN_ERR "Unknown standard configuration %d\n",
668 memcpy(bus.mpc_bustype, "ISA ", 6);
673 memcpy(bus.mpc_bustype, "EISA ", 6);
677 memcpy(bus.mpc_bustype, "MCA ", 6);
680 if (mpc_default_type > 4) {
682 memcpy(bus.mpc_bustype, "PCI ", 6);
686 ioapic.mpc_type = MP_IOAPIC;
687 ioapic.mpc_apicid = 2;
688 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
689 ioapic.mpc_flags = MPC_APIC_USABLE;
690 ioapic.mpc_apicaddr = 0xFEC00000;
691 MP_ioapic_info(&ioapic);
694 * We set up most of the low 16 IO-APIC pins according to MPS rules.
696 construct_default_ioirq_mptable(mpc_default_type);
698 lintsrc.mpc_type = MP_LINTSRC;
699 lintsrc.mpc_irqflag = 0; /* conforming */
700 lintsrc.mpc_srcbusid = 0;
701 lintsrc.mpc_srcbusirq = 0;
702 lintsrc.mpc_destapic = MP_APIC_ALL;
703 for (i = 0; i < 2; i++) {
704 lintsrc.mpc_irqtype = linttypes[i];
705 lintsrc.mpc_destapiclint = i;
706 MP_lintsrc_info(&lintsrc);
710 static struct intel_mp_floating *mpf_found;
713 * Scan the memory blocks for an SMP configuration block.
715 void __init get_smp_config (void)
717 struct intel_mp_floating *mpf = mpf_found;
720 * ACPI supports both logical (e.g. Hyper-Threading) and physical
721 * processors, where MPS only supports physical.
723 if (acpi_lapic && acpi_ioapic) {
724 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
728 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
730 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
731 if (mpf->mpf_feature2 & (1<<7)) {
732 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
735 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
740 * Now see if we need to read further.
742 if (mpf->mpf_feature1 != 0) {
744 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
745 construct_default_ISA_mptable(mpf->mpf_feature1);
747 } else if (mpf->mpf_physptr) {
750 * Read the physical hardware table. Anything here will
751 * override the defaults.
753 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
754 smp_found_config = 0;
755 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
756 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
760 * If there are no explicit MP IRQ entries, then we are
761 * broken. We set up most of the low 16 IO-APIC pins to
762 * ISA defaults and hope it will work.
764 if (!mp_irq_entries) {
765 struct mpc_config_bus bus;
767 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
769 bus.mpc_type = MP_BUS;
771 memcpy(bus.mpc_bustype, "ISA ", 6);
774 construct_default_ioirq_mptable(0);
780 printk(KERN_INFO "Processors: %d\n", num_processors);
782 * Only use the first configuration found.
786 static int __init smp_scan_config (unsigned long base, unsigned long length)
788 unsigned long *bp = phys_to_virt(base);
789 struct intel_mp_floating *mpf;
791 printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp,length);
792 if (sizeof(*mpf) != 16)
793 printk("Error: MPF size\n");
796 mpf = (struct intel_mp_floating *)bp;
797 if ((*bp == SMP_MAGIC_IDENT) &&
798 (mpf->mpf_length == 1) &&
799 !mpf_checksum((unsigned char *)bp, 16) &&
800 ((mpf->mpf_specification == 1)
801 || (mpf->mpf_specification == 4)) ) {
803 smp_found_config = 1;
804 printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
805 mpf, virt_to_phys(mpf));
806 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
808 if (mpf->mpf_physptr) {
810 * We cannot access to MPC table to compute
811 * table size yet, as only few megabytes from
812 * the bottom is mapped now.
813 * PC-9800's MPC table places on the very last
814 * of physical memory; so that simply reserving
815 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
816 * in reserve_bootmem.
818 unsigned long size = PAGE_SIZE;
819 unsigned long end = max_low_pfn * PAGE_SIZE;
820 if (mpf->mpf_physptr + size > end)
821 size = end - mpf->mpf_physptr;
822 reserve_bootmem(mpf->mpf_physptr, size,
835 void __init find_smp_config (void)
837 unsigned int address;
840 * FIXME: Linux assumes you have 640K of base ram..
841 * this continues the error...
843 * 1) Scan the bottom 1K for a signature
844 * 2) Scan the top 1K of base RAM
845 * 3) Scan the 64K of bios
847 if (smp_scan_config(0x0,0x400) ||
848 smp_scan_config(639*0x400,0x400) ||
849 smp_scan_config(0xF0000,0x10000))
852 * If it is an SMP machine we should know now, unless the
853 * configuration is in an EISA/MCA bus machine with an
854 * extended bios data area.
856 * there is a real-mode segmented pointer pointing to the
857 * 4K EBDA area at 0x40E, calculate and scan it here.
859 * NOTE! There are Linux loaders that will corrupt the EBDA
860 * area, and as such this kind of SMP config may be less
861 * trustworthy, simply because the SMP table may have been
862 * stomped on during early boot. These loaders are buggy and
865 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
868 address = get_bios_ebda();
870 smp_scan_config(address, 0x400);
873 /* --------------------------------------------------------------------------
874 ACPI-based MP Configuration
875 -------------------------------------------------------------------------- */
879 void __init mp_register_lapic_address(u64 address)
881 mp_lapic_addr = (unsigned long) address;
883 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
885 if (boot_cpu_physical_apicid == -1U)
886 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
888 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
891 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
893 if (MAX_APICS - id <= 0) {
894 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
900 #ifdef CONFIG_X86_SMP
906 generic_processor_info(id, GET_APIC_VERSION(apic_read(APIC_LVR)));
909 #ifdef CONFIG_X86_IO_APIC
912 #define MP_MAX_IOAPIC_PIN 127
914 static struct mp_ioapic_routing {
918 u32 pin_programmed[4];
919 } mp_ioapic_routing[MAX_IO_APICS];
921 static int mp_find_ioapic (int gsi)
925 /* Find the IOAPIC that manages this GSI. */
926 for (i = 0; i < nr_ioapics; i++) {
927 if ((gsi >= mp_ioapic_routing[i].gsi_base)
928 && (gsi <= mp_ioapic_routing[i].gsi_end))
932 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
937 static u8 uniq_ioapic_id(u8 id)
939 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
940 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
941 return io_apic_get_unique_id(nr_ioapics, id);
946 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
950 if (bad_ioapic(address))
955 mp_ioapics[idx].mpc_type = MP_IOAPIC;
956 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
957 mp_ioapics[idx].mpc_apicaddr = address;
959 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
960 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
961 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
964 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
965 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
967 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
968 mp_ioapic_routing[idx].gsi_base = gsi_base;
969 mp_ioapic_routing[idx].gsi_end = gsi_base +
970 io_apic_get_redir_entries(idx);
972 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
973 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
974 mp_ioapics[idx].mpc_apicver,
975 mp_ioapics[idx].mpc_apicaddr,
976 mp_ioapic_routing[idx].gsi_base,
977 mp_ioapic_routing[idx].gsi_end);
983 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
985 struct mpc_config_intsrc intsrc;
990 * Convert 'gsi' to 'ioapic.pin'.
992 ioapic = mp_find_ioapic(gsi);
995 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
998 * TBD: This check is for faulty timer entries, where the override
999 * erroneously sets the trigger to level, resulting in a HUGE
1000 * increase of timer interrupts!
1002 if ((bus_irq == 0) && (trigger == 3))
1005 intsrc.mpc_type = MP_INTSRC;
1006 intsrc.mpc_irqtype = mp_INT;
1007 intsrc.mpc_irqflag = (trigger << 2) | polarity;
1008 intsrc.mpc_srcbus = MP_ISA_BUS;
1009 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
1010 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
1011 intsrc.mpc_dstirq = pin; /* INTIN# */
1013 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
1014 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1015 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1016 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1018 mp_irqs[mp_irq_entries] = intsrc;
1019 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1020 panic("Max # of irq sources exceeded!\n");
1025 void __init mp_config_acpi_legacy_irqs (void)
1027 struct mpc_config_intsrc intsrc;
1031 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
1033 * Fabricate the legacy ISA bus (bus #31).
1035 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1037 set_bit(MP_ISA_BUS, mp_bus_not_pci);
1038 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1041 * Older generations of ES7000 have no legacy identity mappings
1043 if (es7000_plat == 1)
1047 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1049 ioapic = mp_find_ioapic(0);
1053 intsrc.mpc_type = MP_INTSRC;
1054 intsrc.mpc_irqflag = 0; /* Conforming */
1055 intsrc.mpc_srcbus = MP_ISA_BUS;
1056 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1059 * Use the default configuration for the IRQs 0-15. Unless
1060 * overridden by (MADT) interrupt source override entries.
1062 for (i = 0; i < 16; i++) {
1065 for (idx = 0; idx < mp_irq_entries; idx++) {
1066 struct mpc_config_intsrc *irq = mp_irqs + idx;
1068 /* Do we already have a mapping for this ISA IRQ? */
1069 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1072 /* Do we already have a mapping for this IOAPIC pin */
1073 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1074 (irq->mpc_dstirq == i))
1078 if (idx != mp_irq_entries) {
1079 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1080 continue; /* IRQ already used */
1083 intsrc.mpc_irqtype = mp_INT;
1084 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1085 intsrc.mpc_dstirq = i;
1087 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1088 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1089 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1090 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1093 mp_irqs[mp_irq_entries] = intsrc;
1094 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1095 panic("Max # of irq sources exceeded!\n");
1099 #define MAX_GSI_NUM 4096
1100 #define IRQ_COMPRESSION_START 64
1102 int mp_register_gsi(u32 gsi, int triggering, int polarity)
1107 static int pci_irq = IRQ_COMPRESSION_START;
1109 * Mapping between Global System Interrupts, which
1110 * represent all possible interrupts, and IRQs
1111 * assigned to actual devices.
1113 static int gsi_to_irq[MAX_GSI_NUM];
1115 /* Don't set up the ACPI SCI because it's already set up */
1116 if (acpi_gbl_FADT.sci_interrupt == gsi)
1119 ioapic = mp_find_ioapic(gsi);
1121 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1125 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1127 if (ioapic_renumber_irq)
1128 gsi = ioapic_renumber_irq(ioapic, gsi);
1131 * Avoid pin reprogramming. PRTs typically include entries
1132 * with redundant pin->gsi mappings (but unique PCI devices);
1133 * we only program the IOAPIC on the first.
1135 bit = ioapic_pin % 32;
1136 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1138 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1139 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1143 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1144 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1145 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1146 return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
1149 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1152 * For GSI >= 64, use IRQ compression
1154 if ((gsi >= IRQ_COMPRESSION_START)
1155 && (triggering == ACPI_LEVEL_SENSITIVE)) {
1157 * For PCI devices assign IRQs in order, avoiding gaps
1158 * due to unused I/O APIC pins.
1161 if (gsi < MAX_GSI_NUM) {
1163 * Retain the VIA chipset work-around (gsi > 15), but
1164 * avoid a problem where the 8254 timer (IRQ0) is setup
1165 * via an override (so it's not on pin 0 of the ioapic),
1166 * and at the same time, the pin 0 interrupt is a PCI
1167 * type. The gsi > 15 test could cause these two pins
1168 * to be shared as IRQ0, and they are not shareable.
1169 * So test for this condition, and if necessary, avoid
1170 * the pin collision.
1174 * Don't assign IRQ used by ACPI SCI
1176 if (gsi == acpi_gbl_FADT.sci_interrupt)
1178 gsi_to_irq[irq] = gsi;
1180 printk(KERN_ERR "GSI %u is too high\n", gsi);
1185 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1186 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1187 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1191 #endif /* CONFIG_X86_IO_APIC */
1192 #endif /* CONFIG_ACPI */