arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/crash_dump.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <linux/scatterlist.h>
  39 #include <linux/iommu-helper.h>
  40
  41 #include <asm/iommu.h>
  42 #include <asm/calgary.h>
  43 #include <asm/tce.h>
  44 #include <asm/pci-direct.h>
  45 #include <asm/system.h>
  46 #include <asm/dma.h>
  47 #include <asm/rio.h>
  48 #include <asm/bios_ebda.h>
  49
  50 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  51 int use_calgary __read_mostly = 1;
  52 #else
  53 int use_calgary __read_mostly = 0;
  54 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  55
  56 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  57 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  58
  59 /* register offsets inside the host bridge space */
  60 #define CALGARY_CONFIG_REG      0x0108
  61 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  62 #define PHB_PLSSR_OFFSET        0x0120
  63 #define PHB_CONFIG_RW_OFFSET    0x0160
  64 #define PHB_IOBASE_BAR_LOW      0x0170
  65 #define PHB_IOBASE_BAR_HIGH     0x0180
  66 #define PHB_MEM_1_LOW           0x0190
  67 #define PHB_MEM_1_HIGH          0x01A0
  68 #define PHB_IO_ADDR_SIZE        0x01B0
  69 #define PHB_MEM_1_SIZE          0x01C0
  70 #define PHB_MEM_ST_OFFSET       0x01D0
  71 #define PHB_AER_OFFSET          0x0200
  72 #define PHB_CONFIG_0_HIGH       0x0220
  73 #define PHB_CONFIG_0_LOW        0x0230
  74 #define PHB_CONFIG_0_END        0x0240
  75 #define PHB_MEM_2_LOW           0x02B0
  76 #define PHB_MEM_2_HIGH          0x02C0
  77 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  78 #define PHB_MEM_2_SIZE_LOW      0x02E0
  79 #define PHB_DOSHOLE_OFFSET      0x08E0
  80
  81 /* CalIOC2 specific */
  82 #define PHB_SAVIOR_L2           0x0DB0
  83 #define PHB_PAGE_MIG_CTRL       0x0DA8
  84 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  85 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  86
  87 /* PHB_CONFIG_RW */
  88 #define PHB_TCE_ENABLE          0x20000000
  89 #define PHB_SLOT_DISABLE        0x1C000000
  90 #define PHB_DAC_DISABLE         0x01000000
  91 #define PHB_MEM2_ENABLE         0x00400000
  92 #define PHB_MCSR_ENABLE         0x00100000
  93 /* TAR (Table Address Register) */
  94 #define TAR_SW_BITS             0x0000ffffffff800fUL
  95 #define TAR_VALID               0x0000000000000008UL
  96 /* CSR (Channel/DMA Status Register) */
  97 #define CSR_AGENT_MASK          0xffe0ffff
  98 /* CCR (Calgary Configuration Register) */
  99 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 100 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 101 #define PMR_SOFTSTOP            0x80000000
 102 #define PMR_SOFTSTOPFAULT       0x40000000
 103 #define PMR_HARDSTOP            0x20000000
 104
 105 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 106 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 107 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 108 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 109 #define PHBS_PER_CALGARY        4
 110
 111 /* register offsets in Calgary's internal register space */
 112 static const unsigned long tar_offsets[] = {
 113         0x0580 /* TAR0 */,
 114         0x0588 /* TAR1 */,
 115         0x0590 /* TAR2 */,
 116         0x0598 /* TAR3 */
 117 };
 118
 119 static const unsigned long split_queue_offsets[] = {
 120         0x4870 /* SPLIT QUEUE 0 */,
 121         0x5870 /* SPLIT QUEUE 1 */,
 122         0x6870 /* SPLIT QUEUE 2 */,
 123         0x7870 /* SPLIT QUEUE 3 */
 124 };
 125
 126 static const unsigned long phb_offsets[] = {
 127         0x8000 /* PHB0 */,
 128         0x9000 /* PHB1 */,
 129         0xA000 /* PHB2 */,
 130         0xB000 /* PHB3 */
 131 };
 132
 133 /* PHB debug registers */
 134
 135 static const unsigned long phb_debug_offsets[] = {
 136         0x4000  /* PHB 0 DEBUG */,
 137         0x5000  /* PHB 1 DEBUG */,
 138         0x6000  /* PHB 2 DEBUG */,
 139         0x7000  /* PHB 3 DEBUG */
 140 };
 141
 142 /*
 143  * STUFF register for each debug PHB,
 144  * byte 1 = start bus number, byte 2 = end bus number
 145  */
 146
 147 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 148
 149 #define EMERGENCY_PAGES 32 /* = 128KB */
 150
 151 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 152 static int translate_empty_slots __read_mostly = 0;
 153 static int calgary_detected __read_mostly = 0;
 154
 155 static struct rio_table_hdr     *rio_table_hdr __initdata;
 156 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 157 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 158
 159 struct calgary_bus_info {
 160         void *tce_space;
 161         unsigned char translation_disabled;
 162         signed char phbid;
 163         void __iomem *bbar;
 164 };
 165
 166 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 167 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 168 static void calgary_dump_error_regs(struct iommu_table *tbl);
 169 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 170 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 171 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 172 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
 173 static void get_tce_space_from_tar(void);
 174
 175 static struct cal_chipset_ops calgary_chip_ops = {
 176         .handle_quirks = calgary_handle_quirks,
 177         .tce_cache_blast = calgary_tce_cache_blast,
 178         .dump_error_regs = calgary_dump_error_regs
 179 };
 180
 181 static struct cal_chipset_ops calioc2_chip_ops = {
 182         .handle_quirks = calioc2_handle_quirks,
 183         .tce_cache_blast = calioc2_tce_cache_blast,
 184         .dump_error_regs = calioc2_dump_error_regs
 185 };
 186
 187 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 188
 189 /* enable this to stress test the chip's TCE cache */
 190 #ifdef CONFIG_IOMMU_DEBUG
 191 static int debugging = 1;
 192
 193 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 194         int expected, unsigned long start, unsigned long end)
 195 {
 196         unsigned long idx = start;
 197
 198         BUG_ON(start >= end);
 199
 200         while (idx < end) {
 201                 if (!!test_bit(idx, bitmap) != expected)
 202                         return idx;
 203                 ++idx;
 204         }
 205
 206         /* all bits have the expected value */
 207         return ~0UL;
 208 }
 209 #else /* debugging is disabled */
 210 static int debugging;
 211
 212 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 213         int expected, unsigned long start, unsigned long end)
 214 {
 215         return ~0UL;
 216 }
 217
 218 #endif /* CONFIG_IOMMU_DEBUG */
 219
 220 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 221 {
 222         unsigned int npages;
 223
 224         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 225         npages >>= PAGE_SHIFT;
 226
 227         return npages;
 228 }
 229
 230 static inline int translation_enabled(struct iommu_table *tbl)
 231 {
 232         /* only PHBs with translation enabled have an IOMMU table */
 233         return (tbl != NULL);
 234 }
 235
 236 static void iommu_range_reserve(struct iommu_table *tbl,
 237         unsigned long start_addr, unsigned int npages)
 238 {
 239         unsigned long index;
 240         unsigned long end;
 241         unsigned long badbit;
 242         unsigned long flags;
 243
 244         index = start_addr >> PAGE_SHIFT;
 245
 246         /* bail out if we're asked to reserve a region we don't cover */
 247         if (index >= tbl->it_size)
 248                 return;
 249
 250         end = index + npages;
 251         if (end > tbl->it_size) /* don't go off the table */
 252                 end = tbl->it_size;
 253
 254         spin_lock_irqsave(&tbl->it_lock, flags);
 255
 256         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 257         if (badbit != ~0UL) {
 258                 if (printk_ratelimit())
 259                         printk(KERN_ERR "Calgary: entry already allocated at "
 260                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 261                                badbit, tbl, start_addr, npages);
 262         }
 263
 264         set_bit_string(tbl->it_map, index, npages);
 265
 266         spin_unlock_irqrestore(&tbl->it_lock, flags);
 267 }
 268
 269 static unsigned long iommu_range_alloc(struct device *dev,
 270                                        struct iommu_table *tbl,
 271                                        unsigned int npages)
 272 {
 273         unsigned long flags;
 274         unsigned long offset;
 275         unsigned long boundary_size;
 276
 277         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 278                               PAGE_SIZE) >> PAGE_SHIFT;
 279
 280         BUG_ON(npages == 0);
 281
 282         spin_lock_irqsave(&tbl->it_lock, flags);
 283
 284         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 285                                   npages, 0, boundary_size, 0);
 286         if (offset == ~0UL) {
 287                 tbl->chip_ops->tce_cache_blast(tbl);
 288
 289                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 290                                           npages, 0, boundary_size, 0);
 291                 if (offset == ~0UL) {
 292                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 293                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 294                         if (panic_on_overflow)
 295                                 panic("Calgary: fix the allocator.\n");
 296                         else
 297                                 return bad_dma_address;
 298                 }
 299         }
 300
 301         tbl->it_hint = offset + npages;
 302         BUG_ON(tbl->it_hint > tbl->it_size);
 303
 304         spin_unlock_irqrestore(&tbl->it_lock, flags);
 305
 306         return offset;
 307 }
 308
 309 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 310                               void *vaddr, unsigned int npages, int direction)
 311 {
 312         unsigned long entry;
 313         dma_addr_t ret = bad_dma_address;
 314
 315         entry = iommu_range_alloc(dev, tbl, npages);
 316
 317         if (unlikely(entry == bad_dma_address))
 318                 goto error;
 319
 320         /* set the return dma address */
 321         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 322
 323         /* put the TCEs in the HW table */
 324         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 325                   direction);
 326
 327         return ret;
 328
 329 error:
 330         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 331                "iommu %p\n", npages, tbl);
 332         return bad_dma_address;
 333 }
 334
 335 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 336         unsigned int npages)
 337 {
 338         unsigned long entry;
 339         unsigned long badbit;
 340         unsigned long badend;
 341         unsigned long flags;
 342
 343         /* were we called with bad_dma_address? */
 344         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 345         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 346                 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
 347                        "address 0x%Lx\n", dma_addr);
 348                 return;
 349         }
 350
 351         entry = dma_addr >> PAGE_SHIFT;
 352
 353         BUG_ON(entry + npages > tbl->it_size);
 354
 355         tce_free(tbl, entry, npages);
 356
 357         spin_lock_irqsave(&tbl->it_lock, flags);
 358
 359         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 360         if (badbit != ~0UL) {
 361                 if (printk_ratelimit())
 362                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 363                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 364                                badbit, tbl, dma_addr, entry, npages);
 365         }
 366
 367         iommu_area_free(tbl->it_map, entry, npages);
 368
 369         spin_unlock_irqrestore(&tbl->it_lock, flags);
 370 }
 371
 372 static inline struct iommu_table *find_iommu_table(struct device *dev)
 373 {
 374         struct pci_dev *pdev;
 375         struct pci_bus *pbus;
 376         struct iommu_table *tbl;
 377
 378         pdev = to_pci_dev(dev);
 379
 380         /* search up the device tree for an iommu */
 381         pbus = pdev->bus;
 382         do {
 383                 tbl = pci_iommu(pbus);
 384                 if (tbl && tbl->it_busno == pbus->number)
 385                         break;
 386                 tbl = NULL;
 387                 pbus = pbus->parent;
 388         } while (pbus);
 389
 390         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 391
 392         return tbl;
 393 }
 394
 395 static void calgary_unmap_sg(struct device *dev,
 396         struct scatterlist *sglist, int nelems, int direction)
 397 {
 398         struct iommu_table *tbl = find_iommu_table(dev);
 399         struct scatterlist *s;
 400         int i;
 401
 402         if (!translation_enabled(tbl))
 403                 return;
 404
 405         for_each_sg(sglist, s, nelems, i) {
 406                 unsigned int npages;
 407                 dma_addr_t dma = s->dma_address;
 408                 unsigned int dmalen = s->dma_length;
 409
 410                 if (dmalen == 0)
 411                         break;
 412
 413                 npages = num_dma_pages(dma, dmalen);
 414                 iommu_free(tbl, dma, npages);
 415         }
 416 }
 417
 418 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 419         int nelems, int direction)
 420 {
 421         struct iommu_table *tbl = find_iommu_table(dev);
 422         struct scatterlist *s;
 423         unsigned long vaddr;
 424         unsigned int npages;
 425         unsigned long entry;
 426         int i;
 427
 428         for_each_sg(sg, s, nelems, i) {
 429                 BUG_ON(!sg_page(s));
 430
 431                 vaddr = (unsigned long) sg_virt(s);
 432                 npages = num_dma_pages(vaddr, s->length);
 433
 434                 entry = iommu_range_alloc(dev, tbl, npages);
 435                 if (entry == bad_dma_address) {
 436                         /* makes sure unmap knows to stop */
 437                         s->dma_length = 0;
 438                         goto error;
 439                 }
 440
 441                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 442
 443                 /* insert into HW table */
 444                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 445                           direction);
 446
 447                 s->dma_length = s->length;
 448         }
 449
 450         return nelems;
 451 error:
 452         calgary_unmap_sg(dev, sg, nelems, direction);
 453         for_each_sg(sg, s, nelems, i) {
 454                 sg->dma_address = bad_dma_address;
 455                 sg->dma_length = 0;
 456         }
 457         return 0;
 458 }
 459
 460 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
 461         size_t size, int direction)
 462 {
 463         void *vaddr = phys_to_virt(paddr);
 464         unsigned long uaddr;
 465         unsigned int npages;
 466         struct iommu_table *tbl = find_iommu_table(dev);
 467
 468         uaddr = (unsigned long)vaddr;
 469         npages = num_dma_pages(uaddr, size);
 470
 471         return iommu_alloc(dev, tbl, vaddr, npages, direction);
 472 }
 473
 474 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 475         size_t size, int direction)
 476 {
 477         struct iommu_table *tbl = find_iommu_table(dev);
 478         unsigned int npages;
 479
 480         npages = num_dma_pages(dma_handle, size);
 481         iommu_free(tbl, dma_handle, npages);
 482 }
 483
 484 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 485         dma_addr_t *dma_handle, gfp_t flag)
 486 {
 487         void *ret = NULL;
 488         dma_addr_t mapping;
 489         unsigned int npages, order;
 490         struct iommu_table *tbl = find_iommu_table(dev);
 491
 492         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 493         npages = size >> PAGE_SHIFT;
 494         order = get_order(size);
 495
 496         /* alloc enough pages (and possibly more) */
 497         ret = (void *)__get_free_pages(flag, order);
 498         if (!ret)
 499                 goto error;
 500         memset(ret, 0, size);
 501
 502         /* set up tces to cover the allocated range */
 503         mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 504         if (mapping == bad_dma_address)
 505                 goto free;
 506         *dma_handle = mapping;
 507         return ret;
 508 free:
 509         free_pages((unsigned long)ret, get_order(size));
 510         ret = NULL;
 511 error:
 512         return ret;
 513 }
 514
 515 static struct dma_mapping_ops calgary_dma_ops = {
 516         .alloc_coherent = calgary_alloc_coherent,
 517         .map_single = calgary_map_single,
 518         .unmap_single = calgary_unmap_single,
 519         .map_sg = calgary_map_sg,
 520         .unmap_sg = calgary_unmap_sg,
 521 };
 522
 523 static inline void __iomem * busno_to_bbar(unsigned char num)
 524 {
 525         return bus_info[num].bbar;
 526 }
 527
 528 static inline int busno_to_phbid(unsigned char num)
 529 {
 530         return bus_info[num].phbid;
 531 }
 532
 533 static inline unsigned long split_queue_offset(unsigned char num)
 534 {
 535         size_t idx = busno_to_phbid(num);
 536
 537         return split_queue_offsets[idx];
 538 }
 539
 540 static inline unsigned long tar_offset(unsigned char num)
 541 {
 542         size_t idx = busno_to_phbid(num);
 543
 544         return tar_offsets[idx];
 545 }
 546
 547 static inline unsigned long phb_offset(unsigned char num)
 548 {
 549         size_t idx = busno_to_phbid(num);
 550
 551         return phb_offsets[idx];
 552 }
 553
 554 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 555 {
 556         unsigned long target = ((unsigned long)bar) | offset;
 557         return (void __iomem*)target;
 558 }
 559
 560 static inline int is_calioc2(unsigned short device)
 561 {
 562         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 563 }
 564
 565 static inline int is_calgary(unsigned short device)
 566 {
 567         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 568 }
 569
 570 static inline int is_cal_pci_dev(unsigned short device)
 571 {
 572         return (is_calgary(device) || is_calioc2(device));
 573 }
 574
 575 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 576 {
 577         u64 val;
 578         u32 aer;
 579         int i = 0;
 580         void __iomem *bbar = tbl->bbar;
 581         void __iomem *target;
 582
 583         /* disable arbitration on the bus */
 584         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 585         aer = readl(target);
 586         writel(0, target);
 587
 588         /* read plssr to ensure it got there */
 589         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 590         val = readl(target);
 591
 592         /* poll split queues until all DMA activity is done */
 593         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 594         do {
 595                 val = readq(target);
 596                 i++;
 597         } while ((val & 0xff) != 0xff && i < 100);
 598         if (i == 100)
 599                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 600                        "continuing anyway\n");
 601
 602         /* invalidate TCE cache */
 603         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 604         writeq(tbl->tar_val, target);
 605
 606         /* enable arbitration */
 607         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 608         writel(aer, target);
 609         (void)readl(target); /* flush */
 610 }
 611
 612 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 613 {
 614         void __iomem *bbar = tbl->bbar;
 615         void __iomem *target;
 616         u64 val64;
 617         u32 val;
 618         int i = 0;
 619         int count = 1;
 620         unsigned char bus = tbl->it_busno;
 621
 622 begin:
 623         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 624                "sequence - count %d\n", bus, count);
 625
 626         /* 1. using the Page Migration Control reg set SoftStop */
 627         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 628         val = be32_to_cpu(readl(target));
 629         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 630         val |= PMR_SOFTSTOP;
 631         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 632         writel(cpu_to_be32(val), target);
 633
 634         /* 2. poll split queues until all DMA activity is done */
 635         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 636         target = calgary_reg(bbar, split_queue_offset(bus));
 637         do {
 638                 val64 = readq(target);
 639                 i++;
 640         } while ((val64 & 0xff) != 0xff && i < 100);
 641         if (i == 100)
 642                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 643                        "continuing anyway\n");
 644
 645         /* 3. poll Page Migration DEBUG for SoftStopFault */
 646         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 647         val = be32_to_cpu(readl(target));
 648         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 649
 650         /* 4. if SoftStopFault - goto (1) */
 651         if (val & PMR_SOFTSTOPFAULT) {
 652                 if (++count < 100)
 653                         goto begin;
 654                 else {
 655                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 656                                "aborting TCE cache flush sequence!\n");
 657                         return; /* pray for the best */
 658                 }
 659         }
 660
 661         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 662         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 663         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 664         val = be32_to_cpu(readl(target));
 665         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 666         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 667         val = be32_to_cpu(readl(target));
 668         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 669
 670         /* 6. invalidate TCE cache */
 671         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 672         target = calgary_reg(bbar, tar_offset(bus));
 673         writeq(tbl->tar_val, target);
 674
 675         /* 7. Re-read PMCR */
 676         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 677         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 678         val = be32_to_cpu(readl(target));
 679         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 680
 681         /* 8. Remove HardStop */
 682         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 683         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 684         val = 0;
 685         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 686         writel(cpu_to_be32(val), target);
 687         val = be32_to_cpu(readl(target));
 688         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 689 }
 690
 691 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 692         u64 limit)
 693 {
 694         unsigned int numpages;
 695
 696         limit = limit | 0xfffff;
 697         limit++;
 698
 699         numpages = ((limit - start) >> PAGE_SHIFT);
 700         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 701 }
 702
 703 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 704 {
 705         void __iomem *target;
 706         u64 low, high, sizelow;
 707         u64 start, limit;
 708         struct iommu_table *tbl = pci_iommu(dev->bus);
 709         unsigned char busnum = dev->bus->number;
 710         void __iomem *bbar = tbl->bbar;
 711
 712         /* peripheral MEM_1 region */
 713         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 714         low = be32_to_cpu(readl(target));
 715         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 716         high = be32_to_cpu(readl(target));
 717         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 718         sizelow = be32_to_cpu(readl(target));
 719
 720         start = (high << 32) | low;
 721         limit = sizelow;
 722
 723         calgary_reserve_mem_region(dev, start, limit);
 724 }
 725
 726 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 727 {
 728         void __iomem *target;
 729         u32 val32;
 730         u64 low, high, sizelow, sizehigh;
 731         u64 start, limit;
 732         struct iommu_table *tbl = pci_iommu(dev->bus);
 733         unsigned char busnum = dev->bus->number;
 734         void __iomem *bbar = tbl->bbar;
 735
 736         /* is it enabled? */
 737         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 738         val32 = be32_to_cpu(readl(target));
 739         if (!(val32 & PHB_MEM2_ENABLE))
 740                 return;
 741
 742         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 743         low = be32_to_cpu(readl(target));
 744         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 745         high = be32_to_cpu(readl(target));
 746         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 747         sizelow = be32_to_cpu(readl(target));
 748         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 749         sizehigh = be32_to_cpu(readl(target));
 750
 751         start = (high << 32) | low;
 752         limit = (sizehigh << 32) | sizelow;
 753
 754         calgary_reserve_mem_region(dev, start, limit);
 755 }
 756
 757 /*
 758  * some regions of the IO address space do not get translated, so we
 759  * must not give devices IO addresses in those regions. The regions
 760  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 761  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 762  * later.
 763  */
 764 static void __init calgary_reserve_regions(struct pci_dev *dev)
 765 {
 766         unsigned int npages;
 767         u64 start;
 768         struct iommu_table *tbl = pci_iommu(dev->bus);
 769
 770         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 771         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 772
 773         /* avoid the BIOS/VGA first 640KB-1MB region */
 774         /* for CalIOC2 - avoid the entire first MB */
 775         if (is_calgary(dev->device)) {
 776                 start = (640 * 1024);
 777                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 778         } else { /* calioc2 */
 779                 start = 0;
 780                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 781         }
 782         iommu_range_reserve(tbl, start, npages);
 783
 784         /* reserve the two PCI peripheral memory regions in IO space */
 785         calgary_reserve_peripheral_mem_1(dev);
 786         calgary_reserve_peripheral_mem_2(dev);
 787 }
 788
 789 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 790 {
 791         u64 val64;
 792         u64 table_phys;
 793         void __iomem *target;
 794         int ret;
 795         struct iommu_table *tbl;
 796
 797         /* build TCE tables for each PHB */
 798         ret = build_tce_table(dev, bbar);
 799         if (ret)
 800                 return ret;
 801
 802         tbl = pci_iommu(dev->bus);
 803         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 804
 805         if (is_kdump_kernel())
 806                 calgary_init_bitmap_from_tce_table(tbl);
 807         else
 808                 tce_free(tbl, 0, tbl->it_size);
 809
 810         if (is_calgary(dev->device))
 811                 tbl->chip_ops = &calgary_chip_ops;
 812         else if (is_calioc2(dev->device))
 813                 tbl->chip_ops = &calioc2_chip_ops;
 814         else
 815                 BUG();
 816
 817         calgary_reserve_regions(dev);
 818
 819         /* set TARs for each PHB */
 820         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 821         val64 = be64_to_cpu(readq(target));
 822
 823         /* zero out all TAR bits under sw control */
 824         val64 &= ~TAR_SW_BITS;
 825         table_phys = (u64)__pa(tbl->it_base);
 826
 827         val64 |= table_phys;
 828
 829         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 830         val64 |= (u64) specified_table_size;
 831
 832         tbl->tar_val = cpu_to_be64(val64);
 833
 834         writeq(tbl->tar_val, target);
 835         readq(target); /* flush */
 836
 837         return 0;
 838 }
 839
 840 static void __init calgary_free_bus(struct pci_dev *dev)
 841 {
 842         u64 val64;
 843         struct iommu_table *tbl = pci_iommu(dev->bus);
 844         void __iomem *target;
 845         unsigned int bitmapsz;
 846
 847         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 848         val64 = be64_to_cpu(readq(target));
 849         val64 &= ~TAR_SW_BITS;
 850         writeq(cpu_to_be64(val64), target);
 851         readq(target); /* flush */
 852
 853         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 854         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 855         tbl->it_map = NULL;
 856
 857         kfree(tbl);
 858
 859         set_pci_iommu(dev->bus, NULL);
 860
 861         /* Can't free bootmem allocated memory after system is up :-( */
 862         bus_info[dev->bus->number].tce_space = NULL;
 863 }
 864
 865 static void calgary_dump_error_regs(struct iommu_table *tbl)
 866 {
 867         void __iomem *bbar = tbl->bbar;
 868         void __iomem *target;
 869         u32 csr, plssr;
 870
 871         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 872         csr = be32_to_cpu(readl(target));
 873
 874         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 875         plssr = be32_to_cpu(readl(target));
 876
 877         /* If no error, the agent ID in the CSR is not valid */
 878         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 879                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 880 }
 881
 882 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 883 {
 884         void __iomem *bbar = tbl->bbar;
 885         u32 csr, csmr, plssr, mck, rcstat;
 886         void __iomem *target;
 887         unsigned long phboff = phb_offset(tbl->it_busno);
 888         unsigned long erroff;
 889         u32 errregs[7];
 890         int i;
 891
 892         /* dump CSR */
 893         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 894         csr = be32_to_cpu(readl(target));
 895         /* dump PLSSR */
 896         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 897         plssr = be32_to_cpu(readl(target));
 898         /* dump CSMR */
 899         target = calgary_reg(bbar, phboff | 0x290);
 900         csmr = be32_to_cpu(readl(target));
 901         /* dump mck */
 902         target = calgary_reg(bbar, phboff | 0x800);
 903         mck = be32_to_cpu(readl(target));
 904
 905         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 906                tbl->it_busno);
 907
 908         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 909                csr, plssr, csmr, mck);
 910
 911         /* dump rest of error regs */
 912         printk(KERN_EMERG "Calgary: ");
 913         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 914                 /* err regs are at 0x810 - 0x870 */
 915                 erroff = (0x810 + (i * 0x10));
 916                 target = calgary_reg(bbar, phboff | erroff);
 917                 errregs[i] = be32_to_cpu(readl(target));
 918                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 919         }
 920         printk("\n");
 921
 922         /* root complex status */
 923         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 924         rcstat = be32_to_cpu(readl(target));
 925         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 926                PHB_ROOT_COMPLEX_STATUS);
 927 }
 928
 929 static void calgary_watchdog(unsigned long data)
 930 {
 931         struct pci_dev *dev = (struct pci_dev *)data;
 932         struct iommu_table *tbl = pci_iommu(dev->bus);
 933         void __iomem *bbar = tbl->bbar;
 934         u32 val32;
 935         void __iomem *target;
 936
 937         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 938         val32 = be32_to_cpu(readl(target));
 939
 940         /* If no error, the agent ID in the CSR is not valid */
 941         if (val32 & CSR_AGENT_MASK) {
 942                 tbl->chip_ops->dump_error_regs(tbl);
 943
 944                 /* reset error */
 945                 writel(0, target);
 946
 947                 /* Disable bus that caused the error */
 948                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 949                                      PHB_CONFIG_RW_OFFSET);
 950                 val32 = be32_to_cpu(readl(target));
 951                 val32 |= PHB_SLOT_DISABLE;
 952                 writel(cpu_to_be32(val32), target);
 953                 readl(target); /* flush */
 954         } else {
 955                 /* Reset the timer */
 956                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 957         }
 958 }
 959
 960 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 961         unsigned char busnum, unsigned long timeout)
 962 {
 963         u64 val64;
 964         void __iomem *target;
 965         unsigned int phb_shift = ~0; /* silence gcc */
 966         u64 mask;
 967
 968         switch (busno_to_phbid(busnum)) {
 969         case 0: phb_shift = (63 - 19);
 970                 break;
 971         case 1: phb_shift = (63 - 23);
 972                 break;
 973         case 2: phb_shift = (63 - 27);
 974                 break;
 975         case 3: phb_shift = (63 - 35);
 976                 break;
 977         default:
 978                 BUG_ON(busno_to_phbid(busnum));
 979         }
 980
 981         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 982         val64 = be64_to_cpu(readq(target));
 983
 984         /* zero out this PHB's timer bits */
 985         mask = ~(0xFUL << phb_shift);
 986         val64 &= mask;
 987         val64 |= (timeout << phb_shift);
 988         writeq(cpu_to_be64(val64), target);
 989         readq(target); /* flush */
 990 }
 991
 992 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
 993 {
 994         unsigned char busnum = dev->bus->number;
 995         void __iomem *bbar = tbl->bbar;
 996         void __iomem *target;
 997         u32 val;
 998
 999         /*
1000          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1001          */
1002         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1003         val = cpu_to_be32(readl(target));
1004         val |= 0x00800000;
1005         writel(cpu_to_be32(val), target);
1006 }
1007
1008 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1009 {
1010         unsigned char busnum = dev->bus->number;
1011
1012         /*
1013          * Give split completion a longer timeout on bus 1 for aic94xx
1014          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1015          */
1016         if (is_calgary(dev->device) && (busnum == 1))
1017                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1018                                                      CCR_2SEC_TIMEOUT);
1019 }
1020
1021 static void __init calgary_enable_translation(struct pci_dev *dev)
1022 {
1023         u32 val32;
1024         unsigned char busnum;
1025         void __iomem *target;
1026         void __iomem *bbar;
1027         struct iommu_table *tbl;
1028
1029         busnum = dev->bus->number;
1030         tbl = pci_iommu(dev->bus);
1031         bbar = tbl->bbar;
1032
1033         /* enable TCE in PHB Config Register */
1034         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1035         val32 = be32_to_cpu(readl(target));
1036         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1037
1038         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1039                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1040                "Calgary" : "CalIOC2", busnum);
1041         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1042                "bus.\n");
1043
1044         writel(cpu_to_be32(val32), target);
1045         readl(target); /* flush */
1046
1047         init_timer(&tbl->watchdog_timer);
1048         tbl->watchdog_timer.function = &calgary_watchdog;
1049         tbl->watchdog_timer.data = (unsigned long)dev;
1050         mod_timer(&tbl->watchdog_timer, jiffies);
1051 }
1052
1053 static void __init calgary_disable_translation(struct pci_dev *dev)
1054 {
1055         u32 val32;
1056         unsigned char busnum;
1057         void __iomem *target;
1058         void __iomem *bbar;
1059         struct iommu_table *tbl;
1060
1061         busnum = dev->bus->number;
1062         tbl = pci_iommu(dev->bus);
1063         bbar = tbl->bbar;
1064
1065         /* disable TCE in PHB Config Register */
1066         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1067         val32 = be32_to_cpu(readl(target));
1068         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1069
1070         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1071         writel(cpu_to_be32(val32), target);
1072         readl(target); /* flush */
1073
1074         del_timer_sync(&tbl->watchdog_timer);
1075 }
1076
1077 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1078 {
1079         pci_dev_get(dev);
1080         set_pci_iommu(dev->bus, NULL);
1081
1082         /* is the device behind a bridge? */
1083         if (dev->bus->parent)
1084                 dev->bus->parent->self = dev;
1085         else
1086                 dev->bus->self = dev;
1087 }
1088
1089 static int __init calgary_init_one(struct pci_dev *dev)
1090 {
1091         void __iomem *bbar;
1092         struct iommu_table *tbl;
1093         int ret;
1094
1095         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1096
1097         bbar = busno_to_bbar(dev->bus->number);
1098         ret = calgary_setup_tar(dev, bbar);
1099         if (ret)
1100                 goto done;
1101
1102         pci_dev_get(dev);
1103
1104         if (dev->bus->parent) {
1105                 if (dev->bus->parent->self)
1106                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1107                                "bus->parent->self!\n", dev);
1108                 dev->bus->parent->self = dev;
1109         } else
1110                 dev->bus->self = dev;
1111
1112         tbl = pci_iommu(dev->bus);
1113         tbl->chip_ops->handle_quirks(tbl, dev);
1114
1115         calgary_enable_translation(dev);
1116
1117         return 0;
1118
1119 done:
1120         return ret;
1121 }
1122
1123 static int __init calgary_locate_bbars(void)
1124 {
1125         int ret;
1126         int rioidx, phb, bus;
1127         void __iomem *bbar;
1128         void __iomem *target;
1129         unsigned long offset;
1130         u8 start_bus, end_bus;
1131         u32 val;
1132
1133         ret = -ENODATA;
1134         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1135                 struct rio_detail *rio = rio_devs[rioidx];
1136
1137                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1138                         continue;
1139
1140                 /* map entire 1MB of Calgary config space */
1141                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1142                 if (!bbar)
1143                         goto error;
1144
1145                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1146                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1147                         target = calgary_reg(bbar, offset);
1148
1149                         val = be32_to_cpu(readl(target));
1150
1151                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1152                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1153
1154                         if (end_bus) {
1155                                 for (bus = start_bus; bus <= end_bus; bus++) {
1156                                         bus_info[bus].bbar = bbar;
1157                                         bus_info[bus].phbid = phb;
1158                                 }
1159                         } else {
1160                                 bus_info[start_bus].bbar = bbar;
1161                                 bus_info[start_bus].phbid = phb;
1162                         }
1163                 }
1164         }
1165
1166         return 0;
1167
1168 error:
1169         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1170         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1171                 if (bus_info[bus].bbar)
1172                         iounmap(bus_info[bus].bbar);
1173
1174         return ret;
1175 }
1176
1177 static int __init calgary_init(void)
1178 {
1179         int ret;
1180         struct pci_dev *dev = NULL;
1181         struct calgary_bus_info *info;
1182
1183         ret = calgary_locate_bbars();
1184         if (ret)
1185                 return ret;
1186
1187         /* Purely for kdump kernel case */
1188         if (is_kdump_kernel())
1189                 get_tce_space_from_tar();
1190
1191         do {
1192                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1193                 if (!dev)
1194                         break;
1195                 if (!is_cal_pci_dev(dev->device))
1196                         continue;
1197
1198                 info = &bus_info[dev->bus->number];
1199                 if (info->translation_disabled) {
1200                         calgary_init_one_nontraslated(dev);
1201                         continue;
1202                 }
1203
1204                 if (!info->tce_space && !translate_empty_slots)
1205                         continue;
1206
1207                 ret = calgary_init_one(dev);
1208                 if (ret)
1209                         goto error;
1210         } while (1);
1211
1212         dev = NULL;
1213         for_each_pci_dev(dev) {
1214                 struct iommu_table *tbl;
1215
1216                 tbl = find_iommu_table(&dev->dev);
1217
1218                 if (translation_enabled(tbl))
1219                         dev->dev.archdata.dma_ops = &calgary_dma_ops;
1220         }
1221
1222         return ret;
1223
1224 error:
1225         do {
1226                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1227                 if (!dev)
1228                         break;
1229                 if (!is_cal_pci_dev(dev->device))
1230                         continue;
1231
1232                 info = &bus_info[dev->bus->number];
1233                 if (info->translation_disabled) {
1234                         pci_dev_put(dev);
1235                         continue;
1236                 }
1237                 if (!info->tce_space && !translate_empty_slots)
1238                         continue;
1239
1240                 calgary_disable_translation(dev);
1241                 calgary_free_bus(dev);
1242                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1243                 dev->dev.archdata.dma_ops = NULL;
1244         } while (1);
1245
1246         return ret;
1247 }
1248
1249 static inline int __init determine_tce_table_size(u64 ram)
1250 {
1251         int ret;
1252
1253         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1254                 return specified_table_size;
1255
1256         /*
1257          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1258          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1259          * larger table size has twice as many entries, so shift the
1260          * max ram address by 13 to divide by 8K and then look at the
1261          * order of the result to choose between 0-7.
1262          */
1263         ret = get_order(ram >> 13);
1264         if (ret > TCE_TABLE_SIZE_8M)
1265                 ret = TCE_TABLE_SIZE_8M;
1266
1267         return ret;
1268 }
1269
1270 static int __init build_detail_arrays(void)
1271 {
1272         unsigned long ptr;
1273         unsigned numnodes, i;
1274         int scal_detail_size, rio_detail_size;
1275
1276         numnodes = rio_table_hdr->num_scal_dev;
1277         if (numnodes > MAX_NUMNODES){
1278                 printk(KERN_WARNING
1279                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1280                         "but system has %d nodes.\n",
1281                         MAX_NUMNODES, numnodes);
1282                 return -ENODEV;
1283         }
1284
1285         switch (rio_table_hdr->version){
1286         case 2:
1287                 scal_detail_size = 11;
1288                 rio_detail_size = 13;
1289                 break;
1290         case 3:
1291                 scal_detail_size = 12;
1292                 rio_detail_size = 15;
1293                 break;
1294         default:
1295                 printk(KERN_WARNING
1296                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1297                        rio_table_hdr->version);
1298                 return -EPROTO;
1299         }
1300
1301         ptr = ((unsigned long)rio_table_hdr) + 3;
1302         for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
1303                 scal_devs[i] = (struct scal_detail *)ptr;
1304
1305         for (i = 0; i < rio_table_hdr->num_rio_dev;
1306                     i++, ptr += rio_detail_size)
1307                 rio_devs[i] = (struct rio_detail *)ptr;
1308
1309         return 0;
1310 }
1311
1312 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1313 {
1314         int dev;
1315         u32 val;
1316
1317         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1318                 /*
1319                  * FIXME: properly scan for devices accross the
1320                  * PCI-to-PCI bridge on every CalIOC2 port.
1321                  */
1322                 return 1;
1323         }
1324
1325         for (dev = 1; dev < 8; dev++) {
1326                 val = read_pci_config(bus, dev, 0, 0);
1327                 if (val != 0xffffffff)
1328                         break;
1329         }
1330         return (val != 0xffffffff);
1331 }
1332
1333 /*
1334  * calgary_init_bitmap_from_tce_table():
1335  * Funtion for kdump case. In the second/kdump kernel initialize
1336  * the bitmap based on the tce table entries obtained from first kernel
1337  */
1338 static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1339 {
1340         u64 *tp;
1341         unsigned int index;
1342         tp = ((u64 *)tbl->it_base);
1343         for (index = 0 ; index < tbl->it_size; index++) {
1344                 if (*tp != 0x0)
1345                         set_bit(index, tbl->it_map);
1346                 tp++;
1347         }
1348 }
1349
1350 /*
1351  * get_tce_space_from_tar():
1352  * Function for kdump case. Get the tce tables from first kernel
1353  * by reading the contents of the base adress register of calgary iommu
1354  */
1355 static void __init get_tce_space_from_tar(void)
1356 {
1357         int bus;
1358         void __iomem *target;
1359         unsigned long tce_space;
1360
1361         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1362                 struct calgary_bus_info *info = &bus_info[bus];
1363                 unsigned short pci_device;
1364                 u32 val;
1365
1366                 val = read_pci_config(bus, 0, 0, 0);
1367                 pci_device = (val & 0xFFFF0000) >> 16;
1368
1369                 if (!is_cal_pci_dev(pci_device))
1370                         continue;
1371                 if (info->translation_disabled)
1372                         continue;
1373
1374                 if (calgary_bus_has_devices(bus, pci_device) ||
1375                                                 translate_empty_slots) {
1376                         target = calgary_reg(bus_info[bus].bbar,
1377                                                 tar_offset(bus));
1378                         tce_space = be64_to_cpu(readq(target));
1379                         tce_space = tce_space & TAR_SW_BITS;
1380
1381                         tce_space = tce_space & (~specified_table_size);
1382                         info->tce_space = (u64 *)__va(tce_space);
1383                 }
1384         }
1385         return;
1386 }
1387
1388 void __init detect_calgary(void)
1389 {
1390         int bus;
1391         void *tbl;
1392         int calgary_found = 0;
1393         unsigned long ptr;
1394         unsigned int offset, prev_offset;
1395         int ret;
1396
1397         /*
1398          * if the user specified iommu=off or iommu=soft or we found
1399          * another HW IOMMU already, bail out.
1400          */
1401         if (swiotlb || no_iommu || iommu_detected)
1402                 return;
1403
1404         if (!use_calgary)
1405                 return;
1406
1407         if (!early_pci_allowed())
1408                 return;
1409
1410         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1411
1412         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1413
1414         rio_table_hdr = NULL;
1415         prev_offset = 0;
1416         offset = 0x180;
1417         /*
1418          * The next offset is stored in the 1st word.
1419          * Only parse up until the offset increases:
1420          */
1421         while (offset > prev_offset) {
1422                 /* The block id is stored in the 2nd word */
1423                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1424                         /* set the pointer past the offset & block id */
1425                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1426                         break;
1427                 }
1428                 prev_offset = offset;
1429                 offset = *((unsigned short *)(ptr + offset));
1430         }
1431         if (!rio_table_hdr) {
1432                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1433                        "in EBDA - bailing!\n");
1434                 return;
1435         }
1436
1437         ret = build_detail_arrays();
1438         if (ret) {
1439                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1440                 return;
1441         }
1442
1443         specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1444                                         saved_max_pfn : max_pfn) * PAGE_SIZE);
1445
1446         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1447                 struct calgary_bus_info *info = &bus_info[bus];
1448                 unsigned short pci_device;
1449                 u32 val;
1450
1451                 val = read_pci_config(bus, 0, 0, 0);
1452                 pci_device = (val & 0xFFFF0000) >> 16;
1453
1454                 if (!is_cal_pci_dev(pci_device))
1455                         continue;
1456
1457                 if (info->translation_disabled)
1458                         continue;
1459
1460                 if (calgary_bus_has_devices(bus, pci_device) ||
1461                     translate_empty_slots) {
1462                         /*
1463                          * If it is kdump kernel, find and use tce tables
1464                          * from first kernel, else allocate tce tables here
1465                          */
1466                         if (!is_kdump_kernel()) {
1467                                 tbl = alloc_tce_table();
1468                                 if (!tbl)
1469                                         goto cleanup;
1470                                 info->tce_space = tbl;
1471                         }
1472                         calgary_found = 1;
1473                 }
1474         }
1475
1476         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1477                calgary_found ? "found" : "not found");
1478
1479         if (calgary_found) {
1480                 iommu_detected = 1;
1481                 calgary_detected = 1;
1482                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1483                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1484                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1485                        debugging ? "enabled" : "disabled");
1486
1487                 /* swiotlb for devices that aren't behind the Calgary. */
1488                 if (max_pfn > MAX_DMA32_PFN)
1489                         swiotlb = 1;
1490         }
1491         return;
1492
1493 cleanup:
1494         for (--bus; bus >= 0; --bus) {
1495                 struct calgary_bus_info *info = &bus_info[bus];
1496
1497                 if (info->tce_space)
1498                         free_tce_table(info->tce_space);
1499         }
1500 }
1501
1502 int __init calgary_iommu_init(void)
1503 {
1504         int ret;
1505
1506         if (no_iommu || (swiotlb && !calgary_detected))
1507                 return -ENODEV;
1508
1509         if (!calgary_detected)
1510                 return -ENODEV;
1511
1512         /* ok, we're trying to use Calgary - let's roll */
1513         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1514
1515         ret = calgary_init();
1516         if (ret) {
1517                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1518                        "falling back to no_iommu\n", ret);
1519                 return ret;
1520         }
1521
1522         force_iommu = 1;
1523         bad_dma_address = 0x0;
1524         /* dma_ops is set to swiotlb or nommu */
1525         if (!dma_ops)
1526                 dma_ops = &nommu_dma_ops;
1527
1528         return 0;
1529 }
1530
1531 static int __init calgary_parse_options(char *p)
1532 {
1533         unsigned int bridge;
1534         size_t len;
1535         char* endp;
1536
1537         while (*p) {
1538                 if (!strncmp(p, "64k", 3))
1539                         specified_table_size = TCE_TABLE_SIZE_64K;
1540                 else if (!strncmp(p, "128k", 4))
1541                         specified_table_size = TCE_TABLE_SIZE_128K;
1542                 else if (!strncmp(p, "256k", 4))
1543                         specified_table_size = TCE_TABLE_SIZE_256K;
1544                 else if (!strncmp(p, "512k", 4))
1545                         specified_table_size = TCE_TABLE_SIZE_512K;
1546                 else if (!strncmp(p, "1M", 2))
1547                         specified_table_size = TCE_TABLE_SIZE_1M;
1548                 else if (!strncmp(p, "2M", 2))
1549                         specified_table_size = TCE_TABLE_SIZE_2M;
1550                 else if (!strncmp(p, "4M", 2))
1551                         specified_table_size = TCE_TABLE_SIZE_4M;
1552                 else if (!strncmp(p, "8M", 2))
1553                         specified_table_size = TCE_TABLE_SIZE_8M;
1554
1555                 len = strlen("translate_empty_slots");
1556                 if (!strncmp(p, "translate_empty_slots", len))
1557                         translate_empty_slots = 1;
1558
1559                 len = strlen("disable");
1560                 if (!strncmp(p, "disable", len)) {
1561                         p += len;
1562                         if (*p == '=')
1563                                 ++p;
1564                         if (*p == '\0')
1565                                 break;
1566                         bridge = simple_strtol(p, &endp, 0);
1567                         if (p == endp)
1568                                 break;
1569
1570                         if (bridge < MAX_PHB_BUS_NUM) {
1571                                 printk(KERN_INFO "Calgary: disabling "
1572                                        "translation for PHB %#x\n", bridge);
1573                                 bus_info[bridge].translation_disabled = 1;
1574                         }
1575                 }
1576
1577                 p = strpbrk(p, ",");
1578                 if (!p)
1579                         break;
1580
1581                 p++; /* skip ',' */
1582         }
1583         return 1;
1584 }
1585 __setup("calgary=", calgary_parse_options);
1586
1587 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1588 {
1589         struct iommu_table *tbl;
1590         unsigned int npages;
1591         int i;
1592
1593         tbl = pci_iommu(dev->bus);
1594
1595         for (i = 0; i < 4; i++) {
1596                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1597
1598                 /* Don't give out TCEs that map MEM resources */
1599                 if (!(r->flags & IORESOURCE_MEM))
1600                         continue;
1601
1602                 /* 0-based? we reserve the whole 1st MB anyway */
1603                 if (!r->start)
1604                         continue;
1605
1606                 /* cover the whole region */
1607                 npages = (r->end - r->start) >> PAGE_SHIFT;
1608                 npages++;
1609
1610                 iommu_range_reserve(tbl, r->start, npages);
1611         }
1612 }
1613
1614 static int __init calgary_fixup_tce_spaces(void)
1615 {
1616         struct pci_dev *dev = NULL;
1617         struct calgary_bus_info *info;
1618
1619         if (no_iommu || swiotlb || !calgary_detected)
1620                 return -ENODEV;
1621
1622         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1623
1624         do {
1625                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1626                 if (!dev)
1627                         break;
1628                 if (!is_cal_pci_dev(dev->device))
1629                         continue;
1630
1631                 info = &bus_info[dev->bus->number];
1632                 if (info->translation_disabled)
1633                         continue;
1634
1635                 if (!info->tce_space)
1636                         continue;
1637
1638                 calgary_fixup_one_tce_space(dev);
1639
1640         } while (1);
1641
1642         return 0;
1643 }
1644
1645 /*
1646  * We need to be call after pcibios_assign_resources (fs_initcall level)
1647  * and before device_initcall.
1648  */
1649 rootfs_initcall(calgary_fixup_tce_spaces);