2 * Dynamic DMA mapping support for AMD Hammer.
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
8 * See Documentation/DMA-mapping.txt for the interface specification.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/string.h>
20 #include <linux/spinlock.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/topology.h>
24 #include <linux/interrupt.h>
25 #include <linux/bitops.h>
26 #include <linux/kdebug.h>
27 #include <linux/scatterlist.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/pgtable.h>
34 #include <asm/proto.h>
35 #include <asm/iommu.h>
37 #include <asm/cacheflush.h>
38 #include <asm/swiotlb.h>
42 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
43 static unsigned long iommu_size; /* size of remapping area bytes */
44 static unsigned long iommu_pages; /* .. and in pages */
46 static u32 *iommu_gatt_base; /* Remapping table */
49 * If this is disabled the IOMMU will use an optimized flushing strategy
50 * of only flushing when an mapping is reused. With it true the GART is
51 * flushed for every mapping. Problem is that doing the lazy flush seems
52 * to trigger bugs with some popular PCI cards, in particular 3ware (but
53 * has been also also seen with Qlogic at least).
55 int iommu_fullflush = 1;
57 /* Allocation bitmap for the remapping area: */
58 static DEFINE_SPINLOCK(iommu_bitmap_lock);
59 /* Guarded by iommu_bitmap_lock: */
60 static unsigned long *iommu_gart_bitmap;
62 static u32 gart_unmapped_entry;
65 #define GPTE_COHERENT 2
66 #define GPTE_ENCODE(x) \
67 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
68 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
70 #define EMERGENCY_PAGES 32 /* = 128KB */
73 #define AGPEXTERN extern
78 /* backdoor interface to AGP driver */
79 AGPEXTERN int agp_memory_reserved;
80 AGPEXTERN __u32 *agp_gatt_table;
82 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
83 static int need_flush; /* global flush state. set for each gart wrap */
85 static unsigned long alloc_iommu(struct device *dev, int size)
87 unsigned long offset, flags;
88 unsigned long boundary_size;
89 unsigned long base_index;
91 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
92 PAGE_SIZE) >> PAGE_SHIFT;
93 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
94 PAGE_SIZE) >> PAGE_SHIFT;
96 spin_lock_irqsave(&iommu_bitmap_lock, flags);
97 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
98 size, base_index, boundary_size, 0);
101 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
102 size, base_index, boundary_size, 0);
105 next_bit = offset+size;
106 if (next_bit >= iommu_pages) {
113 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
118 static void free_iommu(unsigned long offset, int size)
122 spin_lock_irqsave(&iommu_bitmap_lock, flags);
123 iommu_area_free(iommu_gart_bitmap, offset, size);
124 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
128 * Use global flush state to avoid races with multiple flushers.
130 static void flush_gart(void)
134 spin_lock_irqsave(&iommu_bitmap_lock, flags);
139 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
142 #ifdef CONFIG_IOMMU_LEAK
144 #define SET_LEAK(x) \
146 if (iommu_leak_tab) \
147 iommu_leak_tab[x] = __builtin_return_address(0);\
150 #define CLEAR_LEAK(x) \
152 if (iommu_leak_tab) \
153 iommu_leak_tab[x] = NULL; \
156 /* Debugging aid for drivers that don't free their IOMMU tables */
157 static void **iommu_leak_tab;
158 static int leak_trace;
159 static int iommu_leak_pages = 20;
161 static void dump_leak(void)
166 if (dump || !iommu_leak_tab)
169 show_stack(NULL, NULL);
171 /* Very crude. dump some from the end of the table too */
172 printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
174 for (i = 0; i < iommu_leak_pages; i += 2) {
175 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
176 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0);
177 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
179 printk(KERN_DEBUG "\n");
183 # define CLEAR_LEAK(x)
186 static void iommu_full(struct device *dev, size_t size, int dir)
189 * Ran out of IOMMU space for this operation. This is very bad.
190 * Unfortunately the drivers cannot handle this operation properly.
191 * Return some non mapped prereserved space in the aperture and
192 * let the Northbridge deal with it. This will result in garbage
193 * in the IO operation. When the size exceeds the prereserved space
194 * memory corruption will occur or random memory will be DMAed
195 * out. Hopefully no network devices use single mappings that big.
198 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
200 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
201 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
202 panic("PCI-DMA: Memory would be corrupted\n");
203 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
205 "PCI-DMA: Random memory would be DMAed\n");
207 #ifdef CONFIG_IOMMU_LEAK
213 need_iommu(struct device *dev, unsigned long addr, size_t size)
215 u64 mask = *dev->dma_mask;
216 int high = addr + size > mask;
226 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
228 u64 mask = *dev->dma_mask;
229 int high = addr + size > mask;
235 /* Map a single continuous physical area into the IOMMU.
236 * Caller needs to check if the iommu is needed and flush.
238 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
239 size_t size, int dir)
241 unsigned long npages = iommu_num_pages(phys_mem, size);
242 unsigned long iommu_page = alloc_iommu(dev, npages);
245 if (iommu_page == -1) {
246 if (!nonforced_iommu(dev, phys_mem, size))
248 if (panic_on_overflow)
249 panic("dma_map_area overflow %lu bytes\n", size);
250 iommu_full(dev, size, dir);
251 return bad_dma_address;
254 for (i = 0; i < npages; i++) {
255 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
256 SET_LEAK(iommu_page + i);
257 phys_mem += PAGE_SIZE;
259 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
263 gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir)
265 dma_addr_t map = dma_map_area(dev, paddr, size, dir);
272 /* Map a single area into the IOMMU */
274 gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
279 dev = &x86_dma_fallback_dev;
281 if (!need_iommu(dev, paddr, size))
284 bus = gart_map_simple(dev, paddr, size, dir);
290 * Free a DMA mapping.
292 static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
293 size_t size, int direction)
295 unsigned long iommu_page;
299 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
300 dma_addr >= iommu_bus_base + iommu_size)
303 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
304 npages = iommu_num_pages(dma_addr, size);
305 for (i = 0; i < npages; i++) {
306 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
307 CLEAR_LEAK(iommu_page + i);
309 free_iommu(iommu_page, npages);
313 * Wrapper for pci_unmap_single working with scatterlists.
316 gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
318 struct scatterlist *s;
321 for_each_sg(sg, s, nents, i) {
322 if (!s->dma_length || !s->length)
324 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
328 /* Fallback for dma_map_sg in case of overflow */
329 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
332 struct scatterlist *s;
335 #ifdef CONFIG_IOMMU_DEBUG
336 printk(KERN_DEBUG "dma_map_sg overflow\n");
339 for_each_sg(sg, s, nents, i) {
340 unsigned long addr = sg_phys(s);
342 if (nonforced_iommu(dev, addr, s->length)) {
343 addr = dma_map_area(dev, addr, s->length, dir);
344 if (addr == bad_dma_address) {
346 gart_unmap_sg(dev, sg, i, dir);
348 sg[0].dma_length = 0;
352 s->dma_address = addr;
353 s->dma_length = s->length;
360 /* Map multiple scatterlist entries continuous into the first. */
361 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
362 int nelems, struct scatterlist *sout,
365 unsigned long iommu_start = alloc_iommu(dev, pages);
366 unsigned long iommu_page = iommu_start;
367 struct scatterlist *s;
370 if (iommu_start == -1)
373 for_each_sg(start, s, nelems, i) {
374 unsigned long pages, addr;
375 unsigned long phys_addr = s->dma_address;
377 BUG_ON(s != start && s->offset);
379 sout->dma_address = iommu_bus_base;
380 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
381 sout->dma_length = s->length;
383 sout->dma_length += s->length;
387 pages = iommu_num_pages(s->offset, s->length);
389 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
390 SET_LEAK(iommu_page);
395 BUG_ON(iommu_page - iommu_start != pages);
401 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
402 struct scatterlist *sout, unsigned long pages, int need)
406 sout->dma_address = start->dma_address;
407 sout->dma_length = start->length;
410 return __dma_map_cont(dev, start, nelems, sout, pages);
414 * DMA map all entries in a scatterlist.
415 * Merge chunks that have page aligned sizes into a continuous mapping.
418 gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
420 struct scatterlist *s, *ps, *start_sg, *sgmap;
421 int need = 0, nextneed, i, out, start;
422 unsigned long pages = 0;
423 unsigned int seg_size;
424 unsigned int max_seg_size;
430 dev = &x86_dma_fallback_dev;
434 start_sg = sgmap = sg;
436 max_seg_size = dma_get_max_seg_size(dev);
437 ps = NULL; /* shut up gcc */
438 for_each_sg(sg, s, nents, i) {
439 dma_addr_t addr = sg_phys(s);
441 s->dma_address = addr;
442 BUG_ON(s->length == 0);
444 nextneed = need_iommu(dev, addr, s->length);
446 /* Handle the previous not yet processed entries */
449 * Can only merge when the last chunk ends on a
450 * page boundary and the new one doesn't have an
453 if (!iommu_merge || !nextneed || !need || s->offset ||
454 (s->length + seg_size > max_seg_size) ||
455 (ps->offset + ps->length) % PAGE_SIZE) {
456 if (dma_map_cont(dev, start_sg, i - start,
457 sgmap, pages, need) < 0)
461 sgmap = sg_next(sgmap);
468 seg_size += s->length;
470 pages += iommu_num_pages(s->offset, s->length);
473 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
478 sgmap = sg_next(sgmap);
479 sgmap->dma_length = 0;
485 gart_unmap_sg(dev, sg, out, dir);
487 /* When it was forced or merged try again in a dumb way */
488 if (force_iommu || iommu_merge) {
489 out = dma_map_sg_nonforce(dev, sg, nents, dir);
493 if (panic_on_overflow)
494 panic("dma_map_sg: overflow on %lu pages\n", pages);
496 iommu_full(dev, pages << PAGE_SHIFT, dir);
497 for_each_sg(sg, s, nents, i)
498 s->dma_address = bad_dma_address;
502 /* allocate and map a coherent mapping */
504 gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
509 vaddr = (void *)__get_free_pages(flag | __GFP_ZERO, get_order(size));
513 *dma_addr = gart_map_single(dev, __pa(vaddr), size, DMA_BIDIRECTIONAL);
514 if (*dma_addr != bad_dma_address)
517 free_pages((unsigned long)vaddr, get_order(size));
522 /* free a coherent mapping */
524 gart_free_coherent(struct device *dev, size_t size, void *vaddr,
527 gart_unmap_single(dev, dma_addr, size, DMA_BIDIRECTIONAL);
528 free_pages((unsigned long)vaddr, get_order(size));
533 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
538 iommu_size = aper_size;
543 a = aper + iommu_size;
544 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
546 if (iommu_size < 64*1024*1024) {
548 "PCI-DMA: Warning: Small IOMMU %luMB."
549 " Consider increasing the AGP aperture in BIOS\n",
556 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
558 unsigned aper_size = 0, aper_base_32, aper_order;
561 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
562 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
563 aper_order = (aper_order >> 1) & 7;
565 aper_base = aper_base_32 & 0x7fff;
568 aper_size = (32 * 1024 * 1024) << aper_order;
569 if (aper_base + aper_size > 0x100000000UL || !aper_size)
576 static void enable_gart_translations(void)
580 for (i = 0; i < num_k8_northbridges; i++) {
581 struct pci_dev *dev = k8_northbridges[i];
583 enable_gart_translation(dev, __pa(agp_gatt_table));
588 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
589 * resume in the same way as they are handled in gart_iommu_hole_init().
591 static bool fix_up_north_bridges;
592 static u32 aperture_order;
593 static u32 aperture_alloc;
595 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
597 fix_up_north_bridges = true;
598 aperture_order = aper_order;
599 aperture_alloc = aper_alloc;
602 static int gart_resume(struct sys_device *dev)
604 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
606 if (fix_up_north_bridges) {
609 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
611 for (i = 0; i < num_k8_northbridges; i++) {
612 struct pci_dev *dev = k8_northbridges[i];
615 * Don't enable translations just yet. That is the next
616 * step. Restore the pre-suspend aperture settings.
618 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
619 aperture_order << 1);
620 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
621 aperture_alloc >> 25);
625 enable_gart_translations();
630 static int gart_suspend(struct sys_device *dev, pm_message_t state)
635 static struct sysdev_class gart_sysdev_class = {
637 .suspend = gart_suspend,
638 .resume = gart_resume,
642 static struct sys_device device_gart = {
644 .cls = &gart_sysdev_class,
648 * Private Northbridge GATT initialization in case we cannot use the
649 * AGP driver for some reason.
651 static __init int init_k8_gatt(struct agp_kern_info *info)
653 unsigned aper_size, gatt_size, new_aper_size;
654 unsigned aper_base, new_aper_base;
658 unsigned long start_pfn, end_pfn;
660 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
661 aper_size = aper_base = info->aper_size = 0;
663 for (i = 0; i < num_k8_northbridges; i++) {
664 dev = k8_northbridges[i];
665 new_aper_base = read_aperture(dev, &new_aper_size);
670 aper_size = new_aper_size;
671 aper_base = new_aper_base;
673 if (aper_size != new_aper_size || aper_base != new_aper_base)
678 info->aper_base = aper_base;
679 info->aper_size = aper_size >> 20;
681 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
682 gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
684 panic("Cannot allocate GATT table");
685 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
686 panic("Could not set GART PTEs to uncacheable pages");
688 memset(gatt, 0, gatt_size);
689 agp_gatt_table = gatt;
691 enable_gart_translations();
693 error = sysdev_class_register(&gart_sysdev_class);
695 error = sysdev_register(&device_gart);
697 panic("Could not register gart_sysdev -- would corrupt data on next suspend");
701 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
702 aper_base, aper_size>>10);
704 /* need to map that range */
705 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
706 if (end_pfn > max_low_pfn_mapped) {
707 start_pfn = (aper_base>>PAGE_SHIFT);
708 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
713 /* Should not happen anymore */
714 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
715 KERN_WARNING "falling back to iommu=soft.\n");
719 extern int agp_amd64_init(void);
721 static struct dma_mapping_ops gart_dma_ops = {
722 .map_single = gart_map_single,
723 .unmap_single = gart_unmap_single,
724 .sync_single_for_cpu = NULL,
725 .sync_single_for_device = NULL,
726 .sync_single_range_for_cpu = NULL,
727 .sync_single_range_for_device = NULL,
728 .sync_sg_for_cpu = NULL,
729 .sync_sg_for_device = NULL,
730 .map_sg = gart_map_sg,
731 .unmap_sg = gart_unmap_sg,
732 .alloc_coherent = gart_alloc_coherent,
733 .free_coherent = gart_free_coherent,
736 void gart_iommu_shutdown(void)
741 if (no_agp && (dma_ops != &gart_dma_ops))
744 for (i = 0; i < num_k8_northbridges; i++) {
747 dev = k8_northbridges[i];
748 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
752 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
756 void __init gart_iommu_init(void)
758 struct agp_kern_info info;
759 unsigned long iommu_start;
760 unsigned long aper_size;
761 unsigned long scratch;
764 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
765 printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
769 #ifndef CONFIG_AGP_AMD64
772 /* Makefile puts PCI initialization via subsys_initcall first. */
773 /* Add other K8 AGP bridge drivers here */
775 (agp_amd64_init() < 0) ||
776 (agp_copy_info(agp_bridge, &info) < 0);
782 /* Did we detect a different HW IOMMU? */
783 if (iommu_detected && !gart_iommu_aperture)
787 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
788 !gart_iommu_aperture ||
789 (no_agp && init_k8_gatt(&info) < 0)) {
790 if (max_pfn > MAX_DMA32_PFN) {
791 printk(KERN_WARNING "More than 4GB of memory "
792 "but GART IOMMU not available.\n"
793 KERN_WARNING "falling back to iommu=soft.\n");
798 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
799 aper_size = info.aper_size * 1024 * 1024;
800 iommu_size = check_iommu_size(info.aper_base, aper_size);
801 iommu_pages = iommu_size >> PAGE_SHIFT;
803 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
804 get_order(iommu_pages/8));
805 if (!iommu_gart_bitmap)
806 panic("Cannot allocate iommu bitmap\n");
807 memset(iommu_gart_bitmap, 0, iommu_pages/8);
809 #ifdef CONFIG_IOMMU_LEAK
811 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
812 get_order(iommu_pages*sizeof(void *)));
814 memset(iommu_leak_tab, 0, iommu_pages * 8);
817 "PCI-DMA: Cannot allocate leak trace area\n");
822 * Out of IOMMU space handling.
823 * Reserve some invalid pages at the beginning of the GART.
825 set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
827 agp_memory_reserved = iommu_size;
829 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
832 iommu_start = aper_size - iommu_size;
833 iommu_bus_base = info.aper_base + iommu_start;
834 bad_dma_address = iommu_bus_base;
835 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
838 * Unmap the IOMMU part of the GART. The alias of the page is
839 * always mapped with cache enabled and there is no full cache
840 * coherency across the GART remapping. The unmapping avoids
841 * automatic prefetches from the CPU allocating cache lines in
842 * there. All CPU accesses are done via the direct mapping to
843 * the backing memory. The GART address is only used by PCI
846 set_memory_np((unsigned long)__va(iommu_bus_base),
847 iommu_size >> PAGE_SHIFT);
849 * Tricky. The GART table remaps the physical memory range,
850 * so the CPU wont notice potential aliases and if the memory
851 * is remapped to UC later on, we might surprise the PCI devices
852 * with a stray writeout of a cacheline. So play it sure and
853 * do an explicit, full-scale wbinvd() _after_ having marked all
854 * the pages as Not-Present:
859 * Try to workaround a bug (thanks to BenH):
860 * Set unmapped entries to a scratch page instead of 0.
861 * Any prefetches that hit unmapped entries won't get an bus abort
862 * then. (P2P bridge may be prefetching on DMA reads).
864 scratch = get_zeroed_page(GFP_KERNEL);
866 panic("Cannot allocate iommu scratch page");
867 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
868 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
869 iommu_gatt_base[i] = gart_unmapped_entry;
872 dma_ops = &gart_dma_ops;
875 void __init gart_parse_options(char *p)
879 #ifdef CONFIG_IOMMU_LEAK
880 if (!strncmp(p, "leak", 4)) {
884 if (isdigit(*p) && get_option(&p, &arg))
885 iommu_leak_pages = arg;
888 if (isdigit(*p) && get_option(&p, &arg))
890 if (!strncmp(p, "fullflush", 8))
892 if (!strncmp(p, "nofullflush", 11))
894 if (!strncmp(p, "noagp", 5))
896 if (!strncmp(p, "noaperture", 10))
898 /* duplicated from pci-dma.c */
899 if (!strncmp(p, "force", 5))
900 gart_iommu_aperture_allowed = 1;
901 if (!strncmp(p, "allowed", 7))
902 gart_iommu_aperture_allowed = 1;
903 if (!strncmp(p, "memaper", 7)) {
904 fallback_aper_force = 1;
908 if (get_option(&p, &arg))
909 fallback_aper_order = arg;