arch/x86/kernel/pmc_atom.c

   1 /*
   2  * Intel Atom SOC Power Management Controller Driver
   3  * Copyright (c) 2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/device.h>
  22 #include <linux/debugfs.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/io.h>
  25
  26 #include <asm/pmc_atom.h>
  27
  28 struct pmc_dev {
  29         u32 base_addr;
  30         void __iomem *regmap;
  31 #ifdef CONFIG_DEBUG_FS
  32         struct dentry *dbgfs_dir;
  33 #endif /* CONFIG_DEBUG_FS */
  34 };
  35
  36 static struct pmc_dev pmc_device;
  37 static u32 acpi_base_addr;
  38
  39 struct pmc_dev_map {
  40         const char *name;
  41         u32 bit_mask;
  42 };
  43
  44 static const struct pmc_dev_map dev_map[] = {
  45         {"0  - LPSS1_F0_DMA",           BIT_LPSS1_F0_DMA},
  46         {"1  - LPSS1_F1_PWM1",          BIT_LPSS1_F1_PWM1},
  47         {"2  - LPSS1_F2_PWM2",          BIT_LPSS1_F2_PWM2},
  48         {"3  - LPSS1_F3_HSUART1",       BIT_LPSS1_F3_HSUART1},
  49         {"4  - LPSS1_F4_HSUART2",       BIT_LPSS1_F4_HSUART2},
  50         {"5  - LPSS1_F5_SPI",           BIT_LPSS1_F5_SPI},
  51         {"6  - LPSS1_F6_Reserved",      BIT_LPSS1_F6_XXX},
  52         {"7  - LPSS1_F7_Reserved",      BIT_LPSS1_F7_XXX},
  53         {"8  - SCC_EMMC",               BIT_SCC_EMMC},
  54         {"9  - SCC_SDIO",               BIT_SCC_SDIO},
  55         {"10 - SCC_SDCARD",             BIT_SCC_SDCARD},
  56         {"11 - SCC_MIPI",               BIT_SCC_MIPI},
  57         {"12 - HDA",                    BIT_HDA},
  58         {"13 - LPE",                    BIT_LPE},
  59         {"14 - OTG",                    BIT_OTG},
  60         {"15 - USH",                    BIT_USH},
  61         {"16 - GBE",                    BIT_GBE},
  62         {"17 - SATA",                   BIT_SATA},
  63         {"18 - USB_EHCI",               BIT_USB_EHCI},
  64         {"19 - SEC",                    BIT_SEC},
  65         {"20 - PCIE_PORT0",             BIT_PCIE_PORT0},
  66         {"21 - PCIE_PORT1",             BIT_PCIE_PORT1},
  67         {"22 - PCIE_PORT2",             BIT_PCIE_PORT2},
  68         {"23 - PCIE_PORT3",             BIT_PCIE_PORT3},
  69         {"24 - LPSS2_F0_DMA",           BIT_LPSS2_F0_DMA},
  70         {"25 - LPSS2_F1_I2C1",          BIT_LPSS2_F1_I2C1},
  71         {"26 - LPSS2_F2_I2C2",          BIT_LPSS2_F2_I2C2},
  72         {"27 - LPSS2_F3_I2C3",          BIT_LPSS2_F3_I2C3},
  73         {"28 - LPSS2_F3_I2C4",          BIT_LPSS2_F4_I2C4},
  74         {"29 - LPSS2_F5_I2C5",          BIT_LPSS2_F5_I2C5},
  75         {"30 - LPSS2_F6_I2C6",          BIT_LPSS2_F6_I2C6},
  76         {"31 - LPSS2_F7_I2C7",          BIT_LPSS2_F7_I2C7},
  77         {"32 - SMB",                    BIT_SMB},
  78         {"33 - OTG_SS_PHY",             BIT_OTG_SS_PHY},
  79         {"34 - USH_SS_PHY",             BIT_USH_SS_PHY},
  80         {"35 - DFX",                    BIT_DFX},
  81 };
  82
  83 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
  84 {
  85         return readl(pmc->regmap + reg_offset);
  86 }
  87
  88 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
  89 {
  90         writel(val, pmc->regmap + reg_offset);
  91 }
  92
  93 static void pmc_power_off(void)
  94 {
  95         u16     pm1_cnt_port;
  96         u32     pm1_cnt_value;
  97
  98         pr_info("Preparing to enter system sleep state S5\n");
  99
 100         pm1_cnt_port = acpi_base_addr + PM1_CNT;
 101
 102         pm1_cnt_value = inl(pm1_cnt_port);
 103         pm1_cnt_value &= SLEEP_TYPE_MASK;
 104         pm1_cnt_value |= SLEEP_TYPE_S5;
 105         pm1_cnt_value |= SLEEP_ENABLE;
 106
 107         outl(pm1_cnt_value, pm1_cnt_port);
 108 }
 109
 110 static void pmc_hw_reg_setup(struct pmc_dev *pmc)
 111 {
 112         /*
 113          * Disable PMC S0IX_WAKE_EN events coming from:
 114          * - LPC clock run
 115          * - GPIO_SUS ored dedicated IRQs
 116          * - GPIO_SCORE ored dedicated IRQs
 117          * - GPIO_SUS shared IRQ
 118          * - GPIO_SCORE shared IRQ
 119          */
 120         pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
 121 }
 122
 123 #ifdef CONFIG_DEBUG_FS
 124 static int pmc_dev_state_show(struct seq_file *s, void *unused)
 125 {
 126         struct pmc_dev *pmc = s->private;
 127         u32 func_dis, func_dis_2, func_dis_index;
 128         u32 d3_sts_0, d3_sts_1, d3_sts_index;
 129         int dev_num, dev_index, reg_index;
 130
 131         func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
 132         func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
 133         d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
 134         d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
 135
 136         dev_num = ARRAY_SIZE(dev_map);
 137
 138         for (dev_index = 0; dev_index < dev_num; dev_index++) {
 139                 reg_index = dev_index / PMC_REG_BIT_WIDTH;
 140                 if (reg_index) {
 141                         func_dis_index = func_dis_2;
 142                         d3_sts_index = d3_sts_1;
 143                 } else {
 144                         func_dis_index = func_dis;
 145                         d3_sts_index = d3_sts_0;
 146                 }
 147
 148                 seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
 149                         dev_map[dev_index].name,
 150                         dev_map[dev_index].bit_mask & func_dis_index ?
 151                         "Disabled" : "Enabled ",
 152                         dev_map[dev_index].bit_mask & d3_sts_index ?
 153                         "D3" : "D0");
 154         }
 155         return 0;
 156 }
 157
 158 static int pmc_dev_state_open(struct inode *inode, struct file *file)
 159 {
 160         return single_open(file, pmc_dev_state_show, inode->i_private);
 161 }
 162
 163 static const struct file_operations pmc_dev_state_ops = {
 164         .open           = pmc_dev_state_open,
 165         .read           = seq_read,
 166         .llseek         = seq_lseek,
 167         .release        = single_release,
 168 };
 169
 170 static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
 171 {
 172         struct pmc_dev *pmc = s->private;
 173         u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
 174
 175         s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
 176         s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
 177         s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
 178         s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
 179         s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
 180
 181         seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
 182         seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
 183         seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
 184         seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
 185         seq_printf(s, "S0   Residency:\t%lldus\n", s0_tmr);
 186         return 0;
 187 }
 188
 189 static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
 190 {
 191         return single_open(file, pmc_sleep_tmr_show, inode->i_private);
 192 }
 193
 194 static const struct file_operations pmc_sleep_tmr_ops = {
 195         .open           = pmc_sleep_tmr_open,
 196         .read           = seq_read,
 197         .llseek         = seq_lseek,
 198         .release        = single_release,
 199 };
 200
 201 static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
 202 {
 203         debugfs_remove_recursive(pmc->dbgfs_dir);
 204 }
 205
 206 static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
 207 {
 208         struct dentry *dir, *f;
 209
 210         dir = debugfs_create_dir("pmc_atom", NULL);
 211         if (!dir)
 212                 return -ENOMEM;
 213
 214         pmc->dbgfs_dir = dir;
 215
 216         f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
 217                                 dir, pmc, &pmc_dev_state_ops);
 218         if (!f) {
 219                 dev_err(&pdev->dev, "dev_states register failed\n");
 220                 goto err;
 221         }
 222         f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
 223                                 dir, pmc, &pmc_sleep_tmr_ops);
 224         if (!f) {
 225                 dev_err(&pdev->dev, "sleep_state register failed\n");
 226                 goto err;
 227         }
 228
 229         return 0;
 230 err:
 231         pmc_dbgfs_unregister(pmc);
 232         return -ENODEV;
 233 }
 234 #else
 235 static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
 236 {
 237         return 0;
 238 }
 239 #endif /* CONFIG_DEBUG_FS */
 240
 241 static int pmc_setup_dev(struct pci_dev *pdev)
 242 {
 243         struct pmc_dev *pmc = &pmc_device;
 244         int ret;
 245
 246         /* Obtain ACPI base address */
 247         pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
 248         acpi_base_addr &= ACPI_BASE_ADDR_MASK;
 249
 250         /* Install power off function */
 251         if (acpi_base_addr != 0 && pm_power_off == NULL)
 252                 pm_power_off = pmc_power_off;
 253
 254         pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
 255         pmc->base_addr &= PMC_BASE_ADDR_MASK;
 256
 257         pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
 258         if (!pmc->regmap) {
 259                 dev_err(&pdev->dev, "error: ioremap failed\n");
 260                 return -ENOMEM;
 261         }
 262
 263         /* PMC hardware registers setup */
 264         pmc_hw_reg_setup(pmc);
 265
 266         ret = pmc_dbgfs_register(pmc, pdev);
 267         if (ret) {
 268                 iounmap(pmc->regmap);
 269         }
 270
 271         return ret;
 272 }
 273
 274 /*
 275  * Data for PCI driver interface
 276  *
 277  * This data only exists for exporting the supported
 278  * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 279  * register a pci_driver, because lpc_ich will register
 280  * a driver on the same PCI id.
 281  */
 282 static const struct pci_device_id pmc_pci_ids[] = {
 283         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
 284         { 0, },
 285 };
 286
 287 MODULE_DEVICE_TABLE(pci, pmc_pci_ids);
 288
 289 static int __init pmc_atom_init(void)
 290 {
 291         struct pci_dev *pdev = NULL;
 292         const struct pci_device_id *ent;
 293
 294         /* We look for our device - PCU PMC
 295          * we assume that there is max. one device.
 296          *
 297          * We can't use plain pci_driver mechanism,
 298          * as the device is really a multiple function device,
 299          * main driver that binds to the pci_device is lpc_ich
 300          * and have to find & bind to the device this way.
 301          */
 302         for_each_pci_dev(pdev) {
 303                 ent = pci_match_id(pmc_pci_ids, pdev);
 304                 if (ent)
 305                         return pmc_setup_dev(pdev);
 306         }
 307         /* Device not found. */
 308         return -ENODEV;
 309 }
 310
 311 module_init(pmc_atom_init);
 312 /* no module_exit, this driver shouldn't be unloaded */
 313
 314 MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
 315 MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
 316 MODULE_LICENSE("GPL v2");