1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/events/power.h>
13 #include <asm/system.h>
15 #include <asm/syscalls.h>
17 #include <asm/uaccess.h>
20 #include <asm/debugreg.h>
21 #include <asm/hw_breakpoint.h>
23 unsigned long idle_halt;
24 EXPORT_SYMBOL(idle_halt);
25 unsigned long idle_nomwait;
26 EXPORT_SYMBOL(idle_nomwait);
28 struct kmem_cache *task_xstate_cachep;
30 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
33 if (src->thread.xstate) {
34 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
36 if (!dst->thread.xstate)
38 WARN_ON((unsigned long)dst->thread.xstate & 15);
39 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
44 void free_thread_xstate(struct task_struct *tsk)
46 if (tsk->thread.xstate) {
47 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
48 tsk->thread.xstate = NULL;
50 if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
51 flush_thread_hw_breakpoint(tsk);
53 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
56 void free_thread_info(struct thread_info *ti)
58 free_thread_xstate(ti->task);
59 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
62 void arch_task_cache_init(void)
65 kmem_cache_create("task_xstate", xstate_size,
66 __alignof__(union thread_xstate),
67 SLAB_PANIC | SLAB_NOTRACK, NULL);
71 * Free current thread data structures etc..
73 void exit_thread(void)
75 struct task_struct *me = current;
76 struct thread_struct *t = &me->thread;
77 unsigned long *bp = t->io_bitmap_ptr;
80 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
82 t->io_bitmap_ptr = NULL;
83 clear_thread_flag(TIF_IO_BITMAP);
85 * Careful, clear this in the TSS too:
87 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
94 void flush_thread(void)
96 struct task_struct *tsk = current;
99 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
100 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
101 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
102 clear_tsk_thread_flag(tsk, TIF_IA32);
104 set_tsk_thread_flag(tsk, TIF_IA32);
105 current_thread_info()->status |= TS_COMPAT;
110 clear_tsk_thread_flag(tsk, TIF_DEBUG);
112 if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
113 flush_thread_hw_breakpoint(tsk);
114 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
116 * Forget coprocessor state..
118 tsk->fpu_counter = 0;
123 static void hard_disable_TSC(void)
125 write_cr4(read_cr4() | X86_CR4_TSD);
128 void disable_TSC(void)
131 if (!test_and_set_thread_flag(TIF_NOTSC))
133 * Must flip the CPU state synchronously with
134 * TIF_NOTSC in the current running context.
140 static void hard_enable_TSC(void)
142 write_cr4(read_cr4() & ~X86_CR4_TSD);
145 static void enable_TSC(void)
148 if (test_and_clear_thread_flag(TIF_NOTSC))
150 * Must flip the CPU state synchronously with
151 * TIF_NOTSC in the current running context.
157 int get_tsc_mode(unsigned long adr)
161 if (test_thread_flag(TIF_NOTSC))
162 val = PR_TSC_SIGSEGV;
166 return put_user(val, (unsigned int __user *)adr);
169 int set_tsc_mode(unsigned int val)
171 if (val == PR_TSC_SIGSEGV)
173 else if (val == PR_TSC_ENABLE)
181 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
182 struct tss_struct *tss)
184 struct thread_struct *prev, *next;
186 prev = &prev_p->thread;
187 next = &next_p->thread;
189 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
190 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
191 ds_switch_to(prev_p, next_p);
192 else if (next->debugctlmsr != prev->debugctlmsr)
193 update_debugctlmsr(next->debugctlmsr);
195 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
196 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
197 /* prev and next are different */
198 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
204 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
206 * Copy the relevant range of the IO bitmap.
207 * Normally this is 128 bytes or less:
209 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
210 max(prev->io_bitmap_max, next->io_bitmap_max));
211 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
213 * Clear any possible leftover bits:
215 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
219 int sys_fork(struct pt_regs *regs)
221 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
225 * This is trivial, and on the face of it looks like it
226 * could equally well be done in user mode.
228 * Not so, for quite unobvious reasons - register pressure.
229 * In user mode vfork() cannot have a stack frame, and if
230 * done by calling the "clone()" system call directly, you
231 * do not have enough call-clobbered registers to hold all
232 * the information you need.
234 int sys_vfork(struct pt_regs *regs)
236 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
242 * Idle related variables and functions
244 unsigned long boot_option_idle_override = 0;
245 EXPORT_SYMBOL(boot_option_idle_override);
248 * Powermanagement idle function, if any..
250 void (*pm_idle)(void);
251 EXPORT_SYMBOL(pm_idle);
255 * This halt magic was a workaround for ancient floppy DMA
256 * wreckage. It should be safe to remove.
258 static int hlt_counter;
259 void disable_hlt(void)
263 EXPORT_SYMBOL(disable_hlt);
265 void enable_hlt(void)
269 EXPORT_SYMBOL(enable_hlt);
271 static inline int hlt_use_halt(void)
273 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
276 static inline int hlt_use_halt(void)
283 * We use this if we don't have any better
286 void default_idle(void)
288 if (hlt_use_halt()) {
289 trace_power_start(POWER_CSTATE, 1);
290 current_thread_info()->status &= ~TS_POLLING;
292 * TS_POLLING-cleared state must be visible before we
298 safe_halt(); /* enables interrupts racelessly */
301 current_thread_info()->status |= TS_POLLING;
304 /* loop is done by the caller */
308 #ifdef CONFIG_APM_MODULE
309 EXPORT_SYMBOL(default_idle);
312 void stop_this_cpu(void *dummy)
318 set_cpu_online(smp_processor_id(), false);
319 disable_local_APIC();
322 if (hlt_works(smp_processor_id()))
327 static void do_nothing(void *unused)
332 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
333 * pm_idle and update to new pm_idle value. Required while changing pm_idle
334 * handler on SMP systems.
336 * Caller must have changed pm_idle to the new value before the call. Old
337 * pm_idle value will not be used by any CPU after the return of this function.
339 void cpu_idle_wait(void)
342 /* kick all the CPUs so that they exit out of pm_idle */
343 smp_call_function(do_nothing, NULL, 1);
345 EXPORT_SYMBOL_GPL(cpu_idle_wait);
348 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
349 * which can obviate IPI to trigger checking of need_resched.
350 * We execute MONITOR against need_resched and enter optimized wait state
351 * through MWAIT. Whenever someone changes need_resched, we would be woken
352 * up from MWAIT (without an IPI).
354 * New with Core Duo processors, MWAIT can take some hints based on CPU
357 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
359 trace_power_start(POWER_CSTATE, (ax>>4)+1);
360 if (!need_resched()) {
361 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
362 clflush((void *)¤t_thread_info()->flags);
364 __monitor((void *)¤t_thread_info()->flags, 0, 0);
371 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
372 static void mwait_idle(void)
374 if (!need_resched()) {
375 trace_power_start(POWER_CSTATE, 1);
376 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
377 clflush((void *)¤t_thread_info()->flags);
379 __monitor((void *)¤t_thread_info()->flags, 0, 0);
390 * On SMP it's slightly faster (but much more power-consuming!)
391 * to poll the ->work.need_resched flag instead of waiting for the
392 * cross-CPU IPI to arrive. Use this option with caution.
394 static void poll_idle(void)
396 trace_power_start(POWER_CSTATE, 0);
398 while (!need_resched())
404 * mwait selection logic:
406 * It depends on the CPU. For AMD CPUs that support MWAIT this is
407 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
408 * then depend on a clock divisor and current Pstate of the core. If
409 * all cores of a processor are in halt state (C1) the processor can
410 * enter the C1E (C1 enhanced) state. If mwait is used this will never
413 * idle=mwait overrides this decision and forces the usage of mwait.
415 static int __cpuinitdata force_mwait;
417 #define MWAIT_INFO 0x05
418 #define MWAIT_ECX_EXTENDED_INFO 0x01
419 #define MWAIT_EDX_C1 0xf0
421 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
423 u32 eax, ebx, ecx, edx;
428 if (c->cpuid_level < MWAIT_INFO)
431 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
432 /* Check, whether EDX has extended info about MWAIT */
433 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
437 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
440 return (edx & MWAIT_EDX_C1);
444 * Check for AMD CPUs, which have potentially C1E support
446 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
448 if (c->x86_vendor != X86_VENDOR_AMD)
454 /* Family 0x0f models < rev F do not have C1E */
455 if (c->x86 == 0x0f && c->x86_model < 0x40)
461 static cpumask_var_t c1e_mask;
462 static int c1e_detected;
464 void c1e_remove_cpu(int cpu)
466 if (c1e_mask != NULL)
467 cpumask_clear_cpu(cpu, c1e_mask);
471 * C1E aware idle routine. We check for C1E active in the interrupt
472 * pending message MSR. If we detect C1E, then we handle it the same
473 * way as C3 power states (local apic timer and TSC stop)
475 static void c1e_idle(void)
483 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
484 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
486 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
487 mark_tsc_unstable("TSC halt in AMD C1E");
488 printk(KERN_INFO "System has AMD C1E enabled\n");
489 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
494 int cpu = smp_processor_id();
496 if (!cpumask_test_cpu(cpu, c1e_mask)) {
497 cpumask_set_cpu(cpu, c1e_mask);
499 * Force broadcast so ACPI can not interfere.
501 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
503 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
506 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
511 * The switch back from broadcast mode needs to be
512 * called with interrupts disabled.
515 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
521 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
524 if (pm_idle == poll_idle && smp_num_siblings > 1) {
525 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
526 " performance may degrade.\n");
532 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
534 * One CPU supports mwait => All CPUs supports mwait
536 printk(KERN_INFO "using mwait in idle threads.\n");
537 pm_idle = mwait_idle;
538 } else if (check_c1e_idle(c)) {
539 printk(KERN_INFO "using C1E aware idle routine\n");
542 pm_idle = default_idle;
545 void __init init_c1e_mask(void)
547 /* If we're using c1e_idle, we need to allocate c1e_mask. */
548 if (pm_idle == c1e_idle)
549 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
552 static int __init idle_setup(char *str)
557 if (!strcmp(str, "poll")) {
558 printk("using polling idle threads.\n");
560 } else if (!strcmp(str, "mwait"))
562 else if (!strcmp(str, "halt")) {
564 * When the boot option of idle=halt is added, halt is
565 * forced to be used for CPU idle. In such case CPU C2/C3
566 * won't be used again.
567 * To continue to load the CPU idle driver, don't touch
568 * the boot_option_idle_override.
570 pm_idle = default_idle;
573 } else if (!strcmp(str, "nomwait")) {
575 * If the boot option of "idle=nomwait" is added,
576 * it means that mwait will be disabled for CPU C2/C3
577 * states. In such case it won't touch the variable
578 * of boot_option_idle_override.
585 boot_option_idle_override = 1;
588 early_param("idle", idle_setup);
590 unsigned long arch_align_stack(unsigned long sp)
592 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
593 sp -= get_random_int() % 8192;
597 unsigned long arch_randomize_brk(struct mm_struct *mm)
599 unsigned long range_end = mm->brk + 0x02000000;
600 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;