1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <linux/user-return-notifier.h>
13 #include <trace/events/power.h>
14 #include <linux/hw_breakpoint.h>
15 #include <asm/system.h>
17 #include <asm/syscalls.h>
19 #include <asm/uaccess.h>
22 #include <asm/debugreg.h>
24 unsigned long idle_halt;
25 EXPORT_SYMBOL(idle_halt);
26 unsigned long idle_nomwait;
27 EXPORT_SYMBOL(idle_nomwait);
29 struct kmem_cache *task_xstate_cachep;
31 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
34 if (src->thread.xstate) {
35 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
37 if (!dst->thread.xstate)
39 WARN_ON((unsigned long)dst->thread.xstate & 15);
40 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
45 void free_thread_xstate(struct task_struct *tsk)
47 if (tsk->thread.xstate) {
48 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
49 tsk->thread.xstate = NULL;
52 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
55 void free_thread_info(struct thread_info *ti)
57 free_thread_xstate(ti->task);
58 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
61 void arch_task_cache_init(void)
64 kmem_cache_create("task_xstate", xstate_size,
65 __alignof__(union thread_xstate),
66 SLAB_PANIC | SLAB_NOTRACK, NULL);
70 * Free current thread data structures etc..
72 void exit_thread(void)
74 struct task_struct *me = current;
75 struct thread_struct *t = &me->thread;
76 unsigned long *bp = t->io_bitmap_ptr;
79 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
81 t->io_bitmap_ptr = NULL;
82 clear_thread_flag(TIF_IO_BITMAP);
84 * Careful, clear this in the TSS too:
86 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
93 void flush_thread(void)
95 struct task_struct *tsk = current;
98 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
99 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
100 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
101 clear_tsk_thread_flag(tsk, TIF_IA32);
103 set_tsk_thread_flag(tsk, TIF_IA32);
104 current_thread_info()->status |= TS_COMPAT;
109 flush_ptrace_hw_breakpoint(tsk);
110 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
112 * Forget coprocessor state..
114 tsk->fpu_counter = 0;
119 static void hard_disable_TSC(void)
121 write_cr4(read_cr4() | X86_CR4_TSD);
124 void disable_TSC(void)
127 if (!test_and_set_thread_flag(TIF_NOTSC))
129 * Must flip the CPU state synchronously with
130 * TIF_NOTSC in the current running context.
136 static void hard_enable_TSC(void)
138 write_cr4(read_cr4() & ~X86_CR4_TSD);
141 static void enable_TSC(void)
144 if (test_and_clear_thread_flag(TIF_NOTSC))
146 * Must flip the CPU state synchronously with
147 * TIF_NOTSC in the current running context.
153 int get_tsc_mode(unsigned long adr)
157 if (test_thread_flag(TIF_NOTSC))
158 val = PR_TSC_SIGSEGV;
162 return put_user(val, (unsigned int __user *)adr);
165 int set_tsc_mode(unsigned int val)
167 if (val == PR_TSC_SIGSEGV)
169 else if (val == PR_TSC_ENABLE)
177 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
178 struct tss_struct *tss)
180 struct thread_struct *prev, *next;
182 prev = &prev_p->thread;
183 next = &next_p->thread;
185 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
186 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
187 ds_switch_to(prev_p, next_p);
188 else if (next->debugctlmsr != prev->debugctlmsr)
189 update_debugctlmsr(next->debugctlmsr);
191 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
192 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
193 /* prev and next are different */
194 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
200 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
202 * Copy the relevant range of the IO bitmap.
203 * Normally this is 128 bytes or less:
205 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
206 max(prev->io_bitmap_max, next->io_bitmap_max));
207 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
209 * Clear any possible leftover bits:
211 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
213 propagate_user_return_notify(prev_p, next_p);
216 int sys_fork(struct pt_regs *regs)
218 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
222 * This is trivial, and on the face of it looks like it
223 * could equally well be done in user mode.
225 * Not so, for quite unobvious reasons - register pressure.
226 * In user mode vfork() cannot have a stack frame, and if
227 * done by calling the "clone()" system call directly, you
228 * do not have enough call-clobbered registers to hold all
229 * the information you need.
231 int sys_vfork(struct pt_regs *regs)
233 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
238 sys_clone(unsigned long clone_flags, unsigned long newsp,
239 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
243 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
248 * sys_execve() executes a new program.
250 long sys_execve(char __user *name, char __user * __user *argv,
251 char __user * __user *envp, struct pt_regs *regs)
256 filename = getname(name);
257 error = PTR_ERR(filename);
258 if (IS_ERR(filename))
260 error = do_execve(filename, argv, envp, regs);
264 /* Make sure we don't return using sysenter.. */
265 set_thread_flag(TIF_IRET);
274 * Idle related variables and functions
276 unsigned long boot_option_idle_override = 0;
277 EXPORT_SYMBOL(boot_option_idle_override);
280 * Powermanagement idle function, if any..
282 void (*pm_idle)(void);
283 EXPORT_SYMBOL(pm_idle);
287 * This halt magic was a workaround for ancient floppy DMA
288 * wreckage. It should be safe to remove.
290 static int hlt_counter;
291 void disable_hlt(void)
295 EXPORT_SYMBOL(disable_hlt);
297 void enable_hlt(void)
301 EXPORT_SYMBOL(enable_hlt);
303 static inline int hlt_use_halt(void)
305 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
308 static inline int hlt_use_halt(void)
315 * We use this if we don't have any better
318 void default_idle(void)
320 if (hlt_use_halt()) {
321 trace_power_start(POWER_CSTATE, 1);
322 current_thread_info()->status &= ~TS_POLLING;
324 * TS_POLLING-cleared state must be visible before we
330 safe_halt(); /* enables interrupts racelessly */
333 current_thread_info()->status |= TS_POLLING;
336 /* loop is done by the caller */
340 #ifdef CONFIG_APM_MODULE
341 EXPORT_SYMBOL(default_idle);
344 void stop_this_cpu(void *dummy)
350 set_cpu_online(smp_processor_id(), false);
351 disable_local_APIC();
354 if (hlt_works(smp_processor_id()))
359 static void do_nothing(void *unused)
364 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
365 * pm_idle and update to new pm_idle value. Required while changing pm_idle
366 * handler on SMP systems.
368 * Caller must have changed pm_idle to the new value before the call. Old
369 * pm_idle value will not be used by any CPU after the return of this function.
371 void cpu_idle_wait(void)
374 /* kick all the CPUs so that they exit out of pm_idle */
375 smp_call_function(do_nothing, NULL, 1);
377 EXPORT_SYMBOL_GPL(cpu_idle_wait);
380 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
381 * which can obviate IPI to trigger checking of need_resched.
382 * We execute MONITOR against need_resched and enter optimized wait state
383 * through MWAIT. Whenever someone changes need_resched, we would be woken
384 * up from MWAIT (without an IPI).
386 * New with Core Duo processors, MWAIT can take some hints based on CPU
389 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
391 trace_power_start(POWER_CSTATE, (ax>>4)+1);
392 if (!need_resched()) {
393 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
394 clflush((void *)¤t_thread_info()->flags);
396 __monitor((void *)¤t_thread_info()->flags, 0, 0);
403 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
404 static void mwait_idle(void)
406 if (!need_resched()) {
407 trace_power_start(POWER_CSTATE, 1);
408 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
409 clflush((void *)¤t_thread_info()->flags);
411 __monitor((void *)¤t_thread_info()->flags, 0, 0);
422 * On SMP it's slightly faster (but much more power-consuming!)
423 * to poll the ->work.need_resched flag instead of waiting for the
424 * cross-CPU IPI to arrive. Use this option with caution.
426 static void poll_idle(void)
428 trace_power_start(POWER_CSTATE, 0);
430 while (!need_resched())
436 * mwait selection logic:
438 * It depends on the CPU. For AMD CPUs that support MWAIT this is
439 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
440 * then depend on a clock divisor and current Pstate of the core. If
441 * all cores of a processor are in halt state (C1) the processor can
442 * enter the C1E (C1 enhanced) state. If mwait is used this will never
445 * idle=mwait overrides this decision and forces the usage of mwait.
447 static int __cpuinitdata force_mwait;
449 #define MWAIT_INFO 0x05
450 #define MWAIT_ECX_EXTENDED_INFO 0x01
451 #define MWAIT_EDX_C1 0xf0
453 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
455 u32 eax, ebx, ecx, edx;
460 if (c->cpuid_level < MWAIT_INFO)
463 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
464 /* Check, whether EDX has extended info about MWAIT */
465 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
469 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
472 return (edx & MWAIT_EDX_C1);
476 * Check for AMD CPUs, which have potentially C1E support
478 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
480 if (c->x86_vendor != X86_VENDOR_AMD)
486 /* Family 0x0f models < rev F do not have C1E */
487 if (c->x86 == 0x0f && c->x86_model < 0x40)
493 static cpumask_var_t c1e_mask;
494 static int c1e_detected;
496 void c1e_remove_cpu(int cpu)
498 if (c1e_mask != NULL)
499 cpumask_clear_cpu(cpu, c1e_mask);
503 * C1E aware idle routine. We check for C1E active in the interrupt
504 * pending message MSR. If we detect C1E, then we handle it the same
505 * way as C3 power states (local apic timer and TSC stop)
507 static void c1e_idle(void)
515 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
516 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
518 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
519 mark_tsc_unstable("TSC halt in AMD C1E");
520 printk(KERN_INFO "System has AMD C1E enabled\n");
521 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
526 int cpu = smp_processor_id();
528 if (!cpumask_test_cpu(cpu, c1e_mask)) {
529 cpumask_set_cpu(cpu, c1e_mask);
531 * Force broadcast so ACPI can not interfere.
533 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
535 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
538 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
543 * The switch back from broadcast mode needs to be
544 * called with interrupts disabled.
547 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
553 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
556 if (pm_idle == poll_idle && smp_num_siblings > 1) {
557 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
558 " performance may degrade.\n");
564 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
566 * One CPU supports mwait => All CPUs supports mwait
568 printk(KERN_INFO "using mwait in idle threads.\n");
569 pm_idle = mwait_idle;
570 } else if (check_c1e_idle(c)) {
571 printk(KERN_INFO "using C1E aware idle routine\n");
574 pm_idle = default_idle;
577 void __init init_c1e_mask(void)
579 /* If we're using c1e_idle, we need to allocate c1e_mask. */
580 if (pm_idle == c1e_idle)
581 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
584 static int __init idle_setup(char *str)
589 if (!strcmp(str, "poll")) {
590 printk("using polling idle threads.\n");
592 } else if (!strcmp(str, "mwait"))
594 else if (!strcmp(str, "halt")) {
596 * When the boot option of idle=halt is added, halt is
597 * forced to be used for CPU idle. In such case CPU C2/C3
598 * won't be used again.
599 * To continue to load the CPU idle driver, don't touch
600 * the boot_option_idle_override.
602 pm_idle = default_idle;
605 } else if (!strcmp(str, "nomwait")) {
607 * If the boot option of "idle=nomwait" is added,
608 * it means that mwait will be disabled for CPU C2/C3
609 * states. In such case it won't touch the variable
610 * of boot_option_idle_override.
617 boot_option_idle_override = 1;
620 early_param("idle", idle_setup);
622 unsigned long arch_align_stack(unsigned long sp)
624 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
625 sp -= get_random_int() % 8192;
629 unsigned long arch_randomize_brk(struct mm_struct *mm)
631 unsigned long range_end = mm->brk + 0x02000000;
632 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;