1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/errno.h>
4 #include <linux/kernel.h>
7 #include <linux/prctl.h>
8 #include <linux/slab.h>
9 #include <linux/sched.h>
10 #include <linux/sched/idle.h>
11 #include <linux/sched/debug.h>
12 #include <linux/sched/task.h>
13 #include <linux/sched/task_stack.h>
14 #include <linux/init.h>
15 #include <linux/export.h>
17 #include <linux/tick.h>
18 #include <linux/random.h>
19 #include <linux/user-return-notifier.h>
20 #include <linux/dmi.h>
21 #include <linux/utsname.h>
22 #include <linux/stackprotector.h>
23 #include <linux/tick.h>
24 #include <linux/cpuidle.h>
25 #include <trace/events/power.h>
26 #include <linux/hw_breakpoint.h>
29 #include <asm/syscalls.h>
30 #include <linux/uaccess.h>
31 #include <asm/mwait.h>
32 #include <asm/fpu/internal.h>
33 #include <asm/debugreg.h>
35 #include <asm/tlbflush.h>
38 #include <asm/switch_to.h>
42 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
43 * no more per-task TSS's. The TSS size is kept cacheline-aligned
44 * so they are allowed to end up in the .data..cacheline_aligned
45 * section. Since TSS's are completely CPU-local, we want them
46 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
48 __visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
50 .sp0 = TOP_OF_INIT_STACK,
54 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
59 * Note that the .io_bitmap member must be extra-big. This is because
60 * the CPU will access an additional byte beyond the end of the IO
61 * permission bitmap. The extra byte must be all 1 bits, and must
62 * be within the limit.
64 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
67 .SYSENTER_stack_canary = STACK_END_MAGIC,
70 EXPORT_PER_CPU_SYMBOL(cpu_tss);
72 DEFINE_PER_CPU(bool, __tss_limit_invalid);
73 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
76 * this gets called so that we can store lazy state into memory and copy the
77 * current task into the new thread.
79 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
81 memcpy(dst, src, arch_task_struct_size);
83 dst->thread.vm86 = NULL;
86 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
90 * Free current thread data structures etc..
92 void exit_thread(struct task_struct *tsk)
94 struct thread_struct *t = &tsk->thread;
95 unsigned long *bp = t->io_bitmap_ptr;
96 struct fpu *fpu = &t->fpu;
99 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
101 t->io_bitmap_ptr = NULL;
102 clear_thread_flag(TIF_IO_BITMAP);
104 * Careful, clear this in the TSS too:
106 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
107 t->io_bitmap_max = 0;
117 void flush_thread(void)
119 struct task_struct *tsk = current;
121 flush_ptrace_hw_breakpoint(tsk);
122 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
124 fpu__clear(&tsk->thread.fpu);
127 static void hard_disable_TSC(void)
129 cr4_set_bits(X86_CR4_TSD);
132 void disable_TSC(void)
135 if (!test_and_set_thread_flag(TIF_NOTSC))
137 * Must flip the CPU state synchronously with
138 * TIF_NOTSC in the current running context.
144 static void hard_enable_TSC(void)
146 cr4_clear_bits(X86_CR4_TSD);
149 static void enable_TSC(void)
152 if (test_and_clear_thread_flag(TIF_NOTSC))
154 * Must flip the CPU state synchronously with
155 * TIF_NOTSC in the current running context.
161 int get_tsc_mode(unsigned long adr)
165 if (test_thread_flag(TIF_NOTSC))
166 val = PR_TSC_SIGSEGV;
170 return put_user(val, (unsigned int __user *)adr);
173 int set_tsc_mode(unsigned int val)
175 if (val == PR_TSC_SIGSEGV)
177 else if (val == PR_TSC_ENABLE)
185 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
186 struct tss_struct *tss)
188 struct thread_struct *prev, *next;
190 prev = &prev_p->thread;
191 next = &next_p->thread;
193 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
194 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
195 unsigned long debugctl = get_debugctlmsr();
197 debugctl &= ~DEBUGCTLMSR_BTF;
198 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
199 debugctl |= DEBUGCTLMSR_BTF;
201 update_debugctlmsr(debugctl);
204 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
205 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
206 /* prev and next are different */
207 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
213 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
215 * Copy the relevant range of the IO bitmap.
216 * Normally this is 128 bytes or less:
218 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
219 max(prev->io_bitmap_max, next->io_bitmap_max));
222 * Make sure that the TSS limit is correct for the CPU
223 * to notice the IO bitmap.
226 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
228 * Clear any possible leftover bits:
230 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
232 propagate_user_return_notify(prev_p, next_p);
236 * Idle related variables and functions
238 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
239 EXPORT_SYMBOL(boot_option_idle_override);
241 static void (*x86_idle)(void);
244 static inline void play_dead(void)
250 void arch_cpu_idle_enter(void)
252 tsc_verify_tsc_adjust(false);
256 void arch_cpu_idle_dead(void)
262 * Called from the generic idle code.
264 void arch_cpu_idle(void)
270 * We use this if we don't have any better idle routine..
272 void __cpuidle default_idle(void)
274 trace_cpu_idle_rcuidle(1, smp_processor_id());
276 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
278 #ifdef CONFIG_APM_MODULE
279 EXPORT_SYMBOL(default_idle);
283 bool xen_set_default_idle(void)
285 bool ret = !!x86_idle;
287 x86_idle = default_idle;
292 void stop_this_cpu(void *dummy)
298 set_cpu_online(smp_processor_id(), false);
299 disable_local_APIC();
300 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
307 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
308 * states (local apic timer and TSC stop).
310 static void amd_e400_idle(void)
313 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
314 * gets set after static_cpu_has() places have been converted via
317 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
322 tick_broadcast_enter();
327 * The switch back from broadcast mode needs to be called with
328 * interrupts disabled.
331 tick_broadcast_exit();
336 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
337 * We can't rely on cpuidle installing MWAIT, because it will not load
338 * on systems that support only C1 -- so the boot default must be MWAIT.
340 * Some AMD machines are the opposite, they depend on using HALT.
342 * So for default C1, which is used during boot until cpuidle loads,
343 * use MWAIT-C1 on Intel HW that has it, else use HALT.
345 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
347 if (c->x86_vendor != X86_VENDOR_INTEL)
350 if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
357 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
358 * with interrupts enabled and no flags, which is backwards compatible with the
359 * original MWAIT implementation.
361 static __cpuidle void mwait_idle(void)
363 if (!current_set_polling_and_test()) {
364 trace_cpu_idle_rcuidle(1, smp_processor_id());
365 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
367 clflush((void *)¤t_thread_info()->flags);
371 __monitor((void *)¤t_thread_info()->flags, 0, 0);
376 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
380 __current_clr_polling();
383 void select_idle_routine(const struct cpuinfo_x86 *c)
386 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
387 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
389 if (x86_idle || boot_option_idle_override == IDLE_POLL)
392 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
393 pr_info("using AMD E400 aware idle routine\n");
394 x86_idle = amd_e400_idle;
395 } else if (prefer_mwait_c1_over_halt(c)) {
396 pr_info("using mwait in idle threads\n");
397 x86_idle = mwait_idle;
399 x86_idle = default_idle;
402 void amd_e400_c1e_apic_setup(void)
404 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
405 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
407 tick_broadcast_force();
412 void __init arch_post_acpi_subsys_init(void)
416 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
420 * AMD E400 detection needs to happen after ACPI has been enabled. If
421 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
422 * MSR_K8_INT_PENDING_MSG.
424 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
425 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
428 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
430 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
431 mark_tsc_unstable("TSC halt in AMD C1E");
432 pr_info("System has AMD C1E enabled\n");
435 static int __init idle_setup(char *str)
440 if (!strcmp(str, "poll")) {
441 pr_info("using polling idle threads\n");
442 boot_option_idle_override = IDLE_POLL;
443 cpu_idle_poll_ctrl(true);
444 } else if (!strcmp(str, "halt")) {
446 * When the boot option of idle=halt is added, halt is
447 * forced to be used for CPU idle. In such case CPU C2/C3
448 * won't be used again.
449 * To continue to load the CPU idle driver, don't touch
450 * the boot_option_idle_override.
452 x86_idle = default_idle;
453 boot_option_idle_override = IDLE_HALT;
454 } else if (!strcmp(str, "nomwait")) {
456 * If the boot option of "idle=nomwait" is added,
457 * it means that mwait will be disabled for CPU C2/C3
458 * states. In such case it won't touch the variable
459 * of boot_option_idle_override.
461 boot_option_idle_override = IDLE_NOMWAIT;
467 early_param("idle", idle_setup);
469 unsigned long arch_align_stack(unsigned long sp)
471 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
472 sp -= get_random_int() % 8192;
476 unsigned long arch_randomize_brk(struct mm_struct *mm)
478 return randomize_page(mm->brk, 0x02000000);
482 * Return saved PC of a blocked thread.
483 * What is this good for? it will be always the scheduler or ret_from_fork.
485 unsigned long thread_saved_pc(struct task_struct *tsk)
487 struct inactive_task_frame *frame =
488 (struct inactive_task_frame *) READ_ONCE(tsk->thread.sp);
489 return READ_ONCE_NOCHECK(frame->ret_addr);
493 * Called from fs/proc with a reference on @p to find the function
494 * which called into schedule(). This needs to be done carefully
495 * because the task might wake up and we might look at a stack
498 unsigned long get_wchan(struct task_struct *p)
500 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
503 if (!p || p == current || p->state == TASK_RUNNING)
506 if (!try_get_task_stack(p))
509 start = (unsigned long)task_stack_page(p);
514 * Layout of the stack page:
516 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
518 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
520 * ----------- bottom = start
522 * The tasks stack pointer points at the location where the
523 * framepointer is stored. The data on the stack is:
524 * ... IP FP ... IP FP
526 * We need to read FP and IP, so we need to adjust the upper
527 * bound by another unsigned long.
529 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
530 top -= 2 * sizeof(unsigned long);
533 sp = READ_ONCE(p->thread.sp);
534 if (sp < bottom || sp > top)
537 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
539 if (fp < bottom || fp > top)
541 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
542 if (!in_sched_functions(ip)) {
546 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
547 } while (count++ < 16 && p->state != TASK_RUNNING);