1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/power.h>
13 #include <asm/system.h>
15 #include <asm/syscalls.h>
17 #include <asm/uaccess.h>
20 #include <asm/debugreg.h>
21 #include <asm/hw_breakpoint.h>
23 unsigned long idle_halt;
24 EXPORT_SYMBOL(idle_halt);
25 unsigned long idle_nomwait;
26 EXPORT_SYMBOL(idle_nomwait);
28 struct kmem_cache *task_xstate_cachep;
30 DEFINE_TRACE(power_start);
31 DEFINE_TRACE(power_end);
33 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
36 if (src->thread.xstate) {
37 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
39 if (!dst->thread.xstate)
41 WARN_ON((unsigned long)dst->thread.xstate & 15);
42 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
47 void free_thread_xstate(struct task_struct *tsk)
49 if (tsk->thread.xstate) {
50 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
51 tsk->thread.xstate = NULL;
53 if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
54 flush_thread_hw_breakpoint(tsk);
56 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
59 void free_thread_info(struct thread_info *ti)
61 free_thread_xstate(ti->task);
62 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
65 void arch_task_cache_init(void)
68 kmem_cache_create("task_xstate", xstate_size,
69 __alignof__(union thread_xstate),
70 SLAB_PANIC | SLAB_NOTRACK, NULL);
74 * Free current thread data structures etc..
76 void exit_thread(void)
78 struct task_struct *me = current;
79 struct thread_struct *t = &me->thread;
80 unsigned long *bp = t->io_bitmap_ptr;
83 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
85 t->io_bitmap_ptr = NULL;
86 clear_thread_flag(TIF_IO_BITMAP);
88 * Careful, clear this in the TSS too:
90 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
97 void flush_thread(void)
99 struct task_struct *tsk = current;
102 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
103 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
104 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
105 clear_tsk_thread_flag(tsk, TIF_IA32);
107 set_tsk_thread_flag(tsk, TIF_IA32);
108 current_thread_info()->status |= TS_COMPAT;
113 clear_tsk_thread_flag(tsk, TIF_DEBUG);
115 if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
116 flush_thread_hw_breakpoint(tsk);
117 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
119 * Forget coprocessor state..
121 tsk->fpu_counter = 0;
126 static void hard_disable_TSC(void)
128 write_cr4(read_cr4() | X86_CR4_TSD);
131 void disable_TSC(void)
134 if (!test_and_set_thread_flag(TIF_NOTSC))
136 * Must flip the CPU state synchronously with
137 * TIF_NOTSC in the current running context.
143 static void hard_enable_TSC(void)
145 write_cr4(read_cr4() & ~X86_CR4_TSD);
148 static void enable_TSC(void)
151 if (test_and_clear_thread_flag(TIF_NOTSC))
153 * Must flip the CPU state synchronously with
154 * TIF_NOTSC in the current running context.
160 int get_tsc_mode(unsigned long adr)
164 if (test_thread_flag(TIF_NOTSC))
165 val = PR_TSC_SIGSEGV;
169 return put_user(val, (unsigned int __user *)adr);
172 int set_tsc_mode(unsigned int val)
174 if (val == PR_TSC_SIGSEGV)
176 else if (val == PR_TSC_ENABLE)
184 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
185 struct tss_struct *tss)
187 struct thread_struct *prev, *next;
189 prev = &prev_p->thread;
190 next = &next_p->thread;
192 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
193 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
194 ds_switch_to(prev_p, next_p);
195 else if (next->debugctlmsr != prev->debugctlmsr)
196 update_debugctlmsr(next->debugctlmsr);
198 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
199 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
200 /* prev and next are different */
201 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
207 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
209 * Copy the relevant range of the IO bitmap.
210 * Normally this is 128 bytes or less:
212 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
213 max(prev->io_bitmap_max, next->io_bitmap_max));
214 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
216 * Clear any possible leftover bits:
218 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
222 int sys_fork(struct pt_regs *regs)
224 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
228 * This is trivial, and on the face of it looks like it
229 * could equally well be done in user mode.
231 * Not so, for quite unobvious reasons - register pressure.
232 * In user mode vfork() cannot have a stack frame, and if
233 * done by calling the "clone()" system call directly, you
234 * do not have enough call-clobbered registers to hold all
235 * the information you need.
237 int sys_vfork(struct pt_regs *regs)
239 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
245 * Idle related variables and functions
247 unsigned long boot_option_idle_override = 0;
248 EXPORT_SYMBOL(boot_option_idle_override);
251 * Powermanagement idle function, if any..
253 void (*pm_idle)(void);
254 EXPORT_SYMBOL(pm_idle);
258 * This halt magic was a workaround for ancient floppy DMA
259 * wreckage. It should be safe to remove.
261 static int hlt_counter;
262 void disable_hlt(void)
266 EXPORT_SYMBOL(disable_hlt);
268 void enable_hlt(void)
272 EXPORT_SYMBOL(enable_hlt);
274 static inline int hlt_use_halt(void)
276 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
279 static inline int hlt_use_halt(void)
286 * We use this if we don't have any better
289 void default_idle(void)
291 if (hlt_use_halt()) {
292 struct power_trace it;
294 trace_power_start(&it, POWER_CSTATE, 1);
295 current_thread_info()->status &= ~TS_POLLING;
297 * TS_POLLING-cleared state must be visible before we
303 safe_halt(); /* enables interrupts racelessly */
306 current_thread_info()->status |= TS_POLLING;
307 trace_power_end(&it);
310 /* loop is done by the caller */
314 #ifdef CONFIG_APM_MODULE
315 EXPORT_SYMBOL(default_idle);
318 void stop_this_cpu(void *dummy)
324 set_cpu_online(smp_processor_id(), false);
325 disable_local_APIC();
328 if (hlt_works(smp_processor_id()))
333 static void do_nothing(void *unused)
338 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
339 * pm_idle and update to new pm_idle value. Required while changing pm_idle
340 * handler on SMP systems.
342 * Caller must have changed pm_idle to the new value before the call. Old
343 * pm_idle value will not be used by any CPU after the return of this function.
345 void cpu_idle_wait(void)
348 /* kick all the CPUs so that they exit out of pm_idle */
349 smp_call_function(do_nothing, NULL, 1);
351 EXPORT_SYMBOL_GPL(cpu_idle_wait);
354 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
355 * which can obviate IPI to trigger checking of need_resched.
356 * We execute MONITOR against need_resched and enter optimized wait state
357 * through MWAIT. Whenever someone changes need_resched, we would be woken
358 * up from MWAIT (without an IPI).
360 * New with Core Duo processors, MWAIT can take some hints based on CPU
363 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
365 struct power_trace it;
367 trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
368 if (!need_resched()) {
369 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
370 clflush((void *)¤t_thread_info()->flags);
372 __monitor((void *)¤t_thread_info()->flags, 0, 0);
377 trace_power_end(&it);
380 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
381 static void mwait_idle(void)
383 struct power_trace it;
384 if (!need_resched()) {
385 trace_power_start(&it, POWER_CSTATE, 1);
386 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
387 clflush((void *)¤t_thread_info()->flags);
389 __monitor((void *)¤t_thread_info()->flags, 0, 0);
395 trace_power_end(&it);
401 * On SMP it's slightly faster (but much more power-consuming!)
402 * to poll the ->work.need_resched flag instead of waiting for the
403 * cross-CPU IPI to arrive. Use this option with caution.
405 static void poll_idle(void)
407 struct power_trace it;
409 trace_power_start(&it, POWER_CSTATE, 0);
411 while (!need_resched())
413 trace_power_end(&it);
417 * mwait selection logic:
419 * It depends on the CPU. For AMD CPUs that support MWAIT this is
420 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
421 * then depend on a clock divisor and current Pstate of the core. If
422 * all cores of a processor are in halt state (C1) the processor can
423 * enter the C1E (C1 enhanced) state. If mwait is used this will never
426 * idle=mwait overrides this decision and forces the usage of mwait.
428 static int __cpuinitdata force_mwait;
430 #define MWAIT_INFO 0x05
431 #define MWAIT_ECX_EXTENDED_INFO 0x01
432 #define MWAIT_EDX_C1 0xf0
434 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
436 u32 eax, ebx, ecx, edx;
441 if (c->cpuid_level < MWAIT_INFO)
444 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
445 /* Check, whether EDX has extended info about MWAIT */
446 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
450 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
453 return (edx & MWAIT_EDX_C1);
457 * Check for AMD CPUs, which have potentially C1E support
459 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
461 if (c->x86_vendor != X86_VENDOR_AMD)
467 /* Family 0x0f models < rev F do not have C1E */
468 if (c->x86 == 0x0f && c->x86_model < 0x40)
474 static cpumask_var_t c1e_mask;
475 static int c1e_detected;
477 void c1e_remove_cpu(int cpu)
479 if (c1e_mask != NULL)
480 cpumask_clear_cpu(cpu, c1e_mask);
484 * C1E aware idle routine. We check for C1E active in the interrupt
485 * pending message MSR. If we detect C1E, then we handle it the same
486 * way as C3 power states (local apic timer and TSC stop)
488 static void c1e_idle(void)
496 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
497 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
499 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
500 mark_tsc_unstable("TSC halt in AMD C1E");
501 printk(KERN_INFO "System has AMD C1E enabled\n");
502 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
507 int cpu = smp_processor_id();
509 if (!cpumask_test_cpu(cpu, c1e_mask)) {
510 cpumask_set_cpu(cpu, c1e_mask);
512 * Force broadcast so ACPI can not interfere. Needs
513 * to run with interrupts enabled as it uses
517 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
519 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
523 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
528 * The switch back from broadcast mode needs to be
529 * called with interrupts disabled.
532 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
538 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
541 if (pm_idle == poll_idle && smp_num_siblings > 1) {
542 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
543 " performance may degrade.\n");
549 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
551 * One CPU supports mwait => All CPUs supports mwait
553 printk(KERN_INFO "using mwait in idle threads.\n");
554 pm_idle = mwait_idle;
555 } else if (check_c1e_idle(c)) {
556 printk(KERN_INFO "using C1E aware idle routine\n");
559 pm_idle = default_idle;
562 void __init init_c1e_mask(void)
564 /* If we're using c1e_idle, we need to allocate c1e_mask. */
565 if (pm_idle == c1e_idle) {
566 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
567 cpumask_clear(c1e_mask);
571 static int __init idle_setup(char *str)
576 if (!strcmp(str, "poll")) {
577 printk("using polling idle threads.\n");
579 } else if (!strcmp(str, "mwait"))
581 else if (!strcmp(str, "halt")) {
583 * When the boot option of idle=halt is added, halt is
584 * forced to be used for CPU idle. In such case CPU C2/C3
585 * won't be used again.
586 * To continue to load the CPU idle driver, don't touch
587 * the boot_option_idle_override.
589 pm_idle = default_idle;
592 } else if (!strcmp(str, "nomwait")) {
594 * If the boot option of "idle=nomwait" is added,
595 * it means that mwait will be disabled for CPU C2/C3
596 * states. In such case it won't touch the variable
597 * of boot_option_idle_override.
604 boot_option_idle_override = 1;
607 early_param("idle", idle_setup);
609 unsigned long arch_align_stack(unsigned long sp)
611 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
612 sp -= get_random_int() % 8192;
616 unsigned long arch_randomize_brk(struct mm_struct *mm)
618 unsigned long range_end = mm->brk + 0x02000000;
619 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;