1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/ftrace.h>
12 #include <asm/system.h>
15 #include <asm/uaccess.h>
18 unsigned long idle_halt;
19 EXPORT_SYMBOL(idle_halt);
20 unsigned long idle_nomwait;
21 EXPORT_SYMBOL(idle_nomwait);
23 struct kmem_cache *task_xstate_cachep;
25 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
28 if (src->thread.xstate) {
29 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
31 if (!dst->thread.xstate)
33 WARN_ON((unsigned long)dst->thread.xstate & 15);
34 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
39 void free_thread_xstate(struct task_struct *tsk)
41 if (tsk->thread.xstate) {
42 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
43 tsk->thread.xstate = NULL;
47 void free_thread_info(struct thread_info *ti)
49 free_thread_xstate(ti->task);
50 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
53 void arch_task_cache_init(void)
56 kmem_cache_create("task_xstate", xstate_size,
57 __alignof__(union thread_xstate),
62 * Free current thread data structures etc..
64 void exit_thread(void)
66 struct task_struct *me = current;
67 struct thread_struct *t = &me->thread;
68 unsigned long *bp = t->io_bitmap_ptr;
71 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
73 t->io_bitmap_ptr = NULL;
74 clear_thread_flag(TIF_IO_BITMAP);
76 * Careful, clear this in the TSS too:
78 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
84 ds_exit_thread(current);
87 void flush_thread(void)
89 struct task_struct *tsk = current;
92 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
93 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
94 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
95 clear_tsk_thread_flag(tsk, TIF_IA32);
97 set_tsk_thread_flag(tsk, TIF_IA32);
98 current_thread_info()->status |= TS_COMPAT;
103 clear_tsk_thread_flag(tsk, TIF_DEBUG);
105 tsk->thread.debugreg0 = 0;
106 tsk->thread.debugreg1 = 0;
107 tsk->thread.debugreg2 = 0;
108 tsk->thread.debugreg3 = 0;
109 tsk->thread.debugreg6 = 0;
110 tsk->thread.debugreg7 = 0;
111 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
113 * Forget coprocessor state..
115 tsk->fpu_counter = 0;
120 static void hard_disable_TSC(void)
122 write_cr4(read_cr4() | X86_CR4_TSD);
125 void disable_TSC(void)
128 if (!test_and_set_thread_flag(TIF_NOTSC))
130 * Must flip the CPU state synchronously with
131 * TIF_NOTSC in the current running context.
137 static void hard_enable_TSC(void)
139 write_cr4(read_cr4() & ~X86_CR4_TSD);
142 static void enable_TSC(void)
145 if (test_and_clear_thread_flag(TIF_NOTSC))
147 * Must flip the CPU state synchronously with
148 * TIF_NOTSC in the current running context.
154 int get_tsc_mode(unsigned long adr)
158 if (test_thread_flag(TIF_NOTSC))
159 val = PR_TSC_SIGSEGV;
163 return put_user(val, (unsigned int __user *)adr);
166 int set_tsc_mode(unsigned int val)
168 if (val == PR_TSC_SIGSEGV)
170 else if (val == PR_TSC_ENABLE)
178 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
179 struct tss_struct *tss)
181 struct thread_struct *prev, *next;
183 prev = &prev_p->thread;
184 next = &next_p->thread;
186 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
187 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
188 ds_switch_to(prev_p, next_p);
189 else if (next->debugctlmsr != prev->debugctlmsr)
190 update_debugctlmsr(next->debugctlmsr);
192 if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
193 set_debugreg(next->debugreg0, 0);
194 set_debugreg(next->debugreg1, 1);
195 set_debugreg(next->debugreg2, 2);
196 set_debugreg(next->debugreg3, 3);
198 set_debugreg(next->debugreg6, 6);
199 set_debugreg(next->debugreg7, 7);
202 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
203 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
204 /* prev and next are different */
205 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
211 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
213 * Copy the relevant range of the IO bitmap.
214 * Normally this is 128 bytes or less:
216 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
217 max(prev->io_bitmap_max, next->io_bitmap_max));
218 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
220 * Clear any possible leftover bits:
222 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
226 int sys_fork(struct pt_regs *regs)
228 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
232 * This is trivial, and on the face of it looks like it
233 * could equally well be done in user mode.
235 * Not so, for quite unobvious reasons - register pressure.
236 * In user mode vfork() cannot have a stack frame, and if
237 * done by calling the "clone()" system call directly, you
238 * do not have enough call-clobbered registers to hold all
239 * the information you need.
241 int sys_vfork(struct pt_regs *regs)
243 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
249 * Idle related variables and functions
251 unsigned long boot_option_idle_override = 0;
252 EXPORT_SYMBOL(boot_option_idle_override);
255 * Powermanagement idle function, if any..
257 void (*pm_idle)(void);
258 EXPORT_SYMBOL(pm_idle);
262 * This halt magic was a workaround for ancient floppy DMA
263 * wreckage. It should be safe to remove.
265 static int hlt_counter;
266 void disable_hlt(void)
270 EXPORT_SYMBOL(disable_hlt);
272 void enable_hlt(void)
276 EXPORT_SYMBOL(enable_hlt);
278 static inline int hlt_use_halt(void)
280 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
283 static inline int hlt_use_halt(void)
290 * We use this if we don't have any better
293 void default_idle(void)
295 if (hlt_use_halt()) {
296 struct power_trace it;
298 trace_power_start(&it, POWER_CSTATE, 1);
299 current_thread_info()->status &= ~TS_POLLING;
301 * TS_POLLING-cleared state must be visible before we
307 safe_halt(); /* enables interrupts racelessly */
310 current_thread_info()->status |= TS_POLLING;
311 trace_power_end(&it);
314 /* loop is done by the caller */
318 #ifdef CONFIG_APM_MODULE
319 EXPORT_SYMBOL(default_idle);
322 void stop_this_cpu(void *dummy)
328 cpu_clear(smp_processor_id(), cpu_online_map);
329 disable_local_APIC();
332 if (hlt_works(smp_processor_id()))
337 static void do_nothing(void *unused)
342 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
343 * pm_idle and update to new pm_idle value. Required while changing pm_idle
344 * handler on SMP systems.
346 * Caller must have changed pm_idle to the new value before the call. Old
347 * pm_idle value will not be used by any CPU after the return of this function.
349 void cpu_idle_wait(void)
352 /* kick all the CPUs so that they exit out of pm_idle */
353 smp_call_function(do_nothing, NULL, 1);
355 EXPORT_SYMBOL_GPL(cpu_idle_wait);
358 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
359 * which can obviate IPI to trigger checking of need_resched.
360 * We execute MONITOR against need_resched and enter optimized wait state
361 * through MWAIT. Whenever someone changes need_resched, we would be woken
362 * up from MWAIT (without an IPI).
364 * New with Core Duo processors, MWAIT can take some hints based on CPU
367 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
369 struct power_trace it;
371 trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
372 if (!need_resched()) {
373 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
374 clflush((void *)¤t_thread_info()->flags);
376 __monitor((void *)¤t_thread_info()->flags, 0, 0);
381 trace_power_end(&it);
384 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
385 static void mwait_idle(void)
387 struct power_trace it;
388 if (!need_resched()) {
389 trace_power_start(&it, POWER_CSTATE, 1);
390 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
391 clflush((void *)¤t_thread_info()->flags);
393 __monitor((void *)¤t_thread_info()->flags, 0, 0);
399 trace_power_end(&it);
405 * On SMP it's slightly faster (but much more power-consuming!)
406 * to poll the ->work.need_resched flag instead of waiting for the
407 * cross-CPU IPI to arrive. Use this option with caution.
409 static void poll_idle(void)
411 struct power_trace it;
413 trace_power_start(&it, POWER_CSTATE, 0);
415 while (!need_resched())
417 trace_power_end(&it);
421 * mwait selection logic:
423 * It depends on the CPU. For AMD CPUs that support MWAIT this is
424 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
425 * then depend on a clock divisor and current Pstate of the core. If
426 * all cores of a processor are in halt state (C1) the processor can
427 * enter the C1E (C1 enhanced) state. If mwait is used this will never
430 * idle=mwait overrides this decision and forces the usage of mwait.
432 static int __cpuinitdata force_mwait;
434 #define MWAIT_INFO 0x05
435 #define MWAIT_ECX_EXTENDED_INFO 0x01
436 #define MWAIT_EDX_C1 0xf0
438 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
440 u32 eax, ebx, ecx, edx;
445 if (c->cpuid_level < MWAIT_INFO)
448 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
449 /* Check, whether EDX has extended info about MWAIT */
450 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
454 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
457 return (edx & MWAIT_EDX_C1);
461 * Check for AMD CPUs, which have potentially C1E support
463 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
465 if (c->x86_vendor != X86_VENDOR_AMD)
471 /* Family 0x0f models < rev F do not have C1E */
472 if (c->x86 == 0x0f && c->x86_model < 0x40)
478 static cpumask_t c1e_mask = CPU_MASK_NONE;
479 static int c1e_detected;
481 void c1e_remove_cpu(int cpu)
483 cpu_clear(cpu, c1e_mask);
487 * C1E aware idle routine. We check for C1E active in the interrupt
488 * pending message MSR. If we detect C1E, then we handle it the same
489 * way as C3 power states (local apic timer and TSC stop)
491 static void c1e_idle(void)
499 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
500 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
502 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
503 mark_tsc_unstable("TSC halt in AMD C1E");
504 printk(KERN_INFO "System has AMD C1E enabled\n");
505 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
510 int cpu = smp_processor_id();
512 if (!cpu_isset(cpu, c1e_mask)) {
513 cpu_set(cpu, c1e_mask);
515 * Force broadcast so ACPI can not interfere. Needs
516 * to run with interrupts enabled as it uses
520 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
522 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
526 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
531 * The switch back from broadcast mode needs to be
532 * called with interrupts disabled.
535 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
541 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
544 if (pm_idle == poll_idle && smp_num_siblings > 1) {
545 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
546 " performance may degrade.\n");
552 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
554 * One CPU supports mwait => All CPUs supports mwait
556 printk(KERN_INFO "using mwait in idle threads.\n");
557 pm_idle = mwait_idle;
558 } else if (check_c1e_idle(c)) {
559 printk(KERN_INFO "using C1E aware idle routine\n");
562 pm_idle = default_idle;
565 static int __init idle_setup(char *str)
570 if (!strcmp(str, "poll")) {
571 printk("using polling idle threads.\n");
573 } else if (!strcmp(str, "mwait"))
575 else if (!strcmp(str, "halt")) {
577 * When the boot option of idle=halt is added, halt is
578 * forced to be used for CPU idle. In such case CPU C2/C3
579 * won't be used again.
580 * To continue to load the CPU idle driver, don't touch
581 * the boot_option_idle_override.
583 pm_idle = default_idle;
586 } else if (!strcmp(str, "nomwait")) {
588 * If the boot option of "idle=nomwait" is added,
589 * it means that mwait will be disabled for CPU C2/C3
590 * states. In such case it won't touch the variable
591 * of boot_option_idle_override.
598 boot_option_idle_override = 1;
601 early_param("idle", idle_setup);