arch/x86/kernel/process.c

   1 #include <linux/errno.h>
   2 #include <linux/kernel.h>
   3 #include <linux/mm.h>
   4 #include <linux/smp.h>
   5 #include <linux/prctl.h>
   6 #include <linux/slab.h>
   7 #include <linux/sched.h>
   8 #include <linux/module.h>
   9 #include <linux/pm.h>
  10 #include <linux/clockchips.h>
  11 #include <trace/power.h>
  12 #include <asm/system.h>
  13 #include <asm/apic.h>
  14 #include <asm/idle.h>
  15 #include <asm/uaccess.h>
  16 #include <asm/i387.h>
  17
  18 unsigned long idle_halt;
  19 EXPORT_SYMBOL(idle_halt);
  20 unsigned long idle_nomwait;
  21 EXPORT_SYMBOL(idle_nomwait);
  22
  23 struct kmem_cache *task_xstate_cachep;
  24
  25 DEFINE_TRACE(power_start);
  26 DEFINE_TRACE(power_end);
  27
  28 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  29 {
  30         *dst = *src;
  31         if (src->thread.xstate) {
  32                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
  33                                                       GFP_KERNEL);
  34                 if (!dst->thread.xstate)
  35                         return -ENOMEM;
  36                 WARN_ON((unsigned long)dst->thread.xstate & 15);
  37                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
  38         }
  39         return 0;
  40 }
  41
  42 void free_thread_xstate(struct task_struct *tsk)
  43 {
  44         if (tsk->thread.xstate) {
  45                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
  46                 tsk->thread.xstate = NULL;
  47         }
  48 }
  49
  50 void free_thread_info(struct thread_info *ti)
  51 {
  52         free_thread_xstate(ti->task);
  53         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
  54 }
  55
  56 void arch_task_cache_init(void)
  57 {
  58         task_xstate_cachep =
  59                 kmem_cache_create("task_xstate", xstate_size,
  60                                   __alignof__(union thread_xstate),
  61                                   SLAB_PANIC, NULL);
  62 }
  63
  64 /*
  65  * Free current thread data structures etc..
  66  */
  67 void exit_thread(void)
  68 {
  69         struct task_struct *me = current;
  70         struct thread_struct *t = &me->thread;
  71
  72         if (me->thread.io_bitmap_ptr) {
  73                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
  74
  75                 kfree(t->io_bitmap_ptr);
  76                 t->io_bitmap_ptr = NULL;
  77                 clear_thread_flag(TIF_IO_BITMAP);
  78                 /*
  79                  * Careful, clear this in the TSS too:
  80                  */
  81                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
  82                 t->io_bitmap_max = 0;
  83                 put_cpu();
  84         }
  85
  86         ds_exit_thread(current);
  87 }
  88
  89 void flush_thread(void)
  90 {
  91         struct task_struct *tsk = current;
  92
  93 #ifdef CONFIG_X86_64
  94         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
  95                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
  96                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
  97                         clear_tsk_thread_flag(tsk, TIF_IA32);
  98                 } else {
  99                         set_tsk_thread_flag(tsk, TIF_IA32);
 100                         current_thread_info()->status |= TS_COMPAT;
 101                 }
 102         }
 103 #endif
 104
 105         clear_tsk_thread_flag(tsk, TIF_DEBUG);
 106
 107         tsk->thread.debugreg0 = 0;
 108         tsk->thread.debugreg1 = 0;
 109         tsk->thread.debugreg2 = 0;
 110         tsk->thread.debugreg3 = 0;
 111         tsk->thread.debugreg6 = 0;
 112         tsk->thread.debugreg7 = 0;
 113         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 114         /*
 115          * Forget coprocessor state..
 116          */
 117         tsk->fpu_counter = 0;
 118         clear_fpu(tsk);
 119         clear_used_math();
 120 }
 121
 122 static void hard_disable_TSC(void)
 123 {
 124         write_cr4(read_cr4() | X86_CR4_TSD);
 125 }
 126
 127 void disable_TSC(void)
 128 {
 129         preempt_disable();
 130         if (!test_and_set_thread_flag(TIF_NOTSC))
 131                 /*
 132                  * Must flip the CPU state synchronously with
 133                  * TIF_NOTSC in the current running context.
 134                  */
 135                 hard_disable_TSC();
 136         preempt_enable();
 137 }
 138
 139 static void hard_enable_TSC(void)
 140 {
 141         write_cr4(read_cr4() & ~X86_CR4_TSD);
 142 }
 143
 144 static void enable_TSC(void)
 145 {
 146         preempt_disable();
 147         if (test_and_clear_thread_flag(TIF_NOTSC))
 148                 /*
 149                  * Must flip the CPU state synchronously with
 150                  * TIF_NOTSC in the current running context.
 151                  */
 152                 hard_enable_TSC();
 153         preempt_enable();
 154 }
 155
 156 int get_tsc_mode(unsigned long adr)
 157 {
 158         unsigned int val;
 159
 160         if (test_thread_flag(TIF_NOTSC))
 161                 val = PR_TSC_SIGSEGV;
 162         else
 163                 val = PR_TSC_ENABLE;
 164
 165         return put_user(val, (unsigned int __user *)adr);
 166 }
 167
 168 int set_tsc_mode(unsigned int val)
 169 {
 170         if (val == PR_TSC_SIGSEGV)
 171                 disable_TSC();
 172         else if (val == PR_TSC_ENABLE)
 173                 enable_TSC();
 174         else
 175                 return -EINVAL;
 176
 177         return 0;
 178 }
 179
 180 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 181                       struct tss_struct *tss)
 182 {
 183         struct thread_struct *prev, *next;
 184
 185         prev = &prev_p->thread;
 186         next = &next_p->thread;
 187
 188         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
 189             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
 190                 ds_switch_to(prev_p, next_p);
 191         else if (next->debugctlmsr != prev->debugctlmsr)
 192                 update_debugctlmsr(next->debugctlmsr);
 193
 194         if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
 195                 set_debugreg(next->debugreg0, 0);
 196                 set_debugreg(next->debugreg1, 1);
 197                 set_debugreg(next->debugreg2, 2);
 198                 set_debugreg(next->debugreg3, 3);
 199                 /* no 4 and 5 */
 200                 set_debugreg(next->debugreg6, 6);
 201                 set_debugreg(next->debugreg7, 7);
 202         }
 203
 204         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 205             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 206                 /* prev and next are different */
 207                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 208                         hard_disable_TSC();
 209                 else
 210                         hard_enable_TSC();
 211         }
 212
 213         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 214                 /*
 215                  * Copy the relevant range of the IO bitmap.
 216                  * Normally this is 128 bytes or less:
 217                  */
 218                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 219                        max(prev->io_bitmap_max, next->io_bitmap_max));
 220         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 221                 /*
 222                  * Clear any possible leftover bits:
 223                  */
 224                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 225         }
 226 }
 227
 228 int sys_fork(struct pt_regs *regs)
 229 {
 230         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
 231 }
 232
 233 /*
 234  * This is trivial, and on the face of it looks like it
 235  * could equally well be done in user mode.
 236  *
 237  * Not so, for quite unobvious reasons - register pressure.
 238  * In user mode vfork() cannot have a stack frame, and if
 239  * done by calling the "clone()" system call directly, you
 240  * do not have enough call-clobbered registers to hold all
 241  * the information you need.
 242  */
 243 int sys_vfork(struct pt_regs *regs)
 244 {
 245         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
 246                        NULL, NULL);
 247 }
 248
 249
 250 /*
 251  * Idle related variables and functions
 252  */
 253 unsigned long boot_option_idle_override = 0;
 254 EXPORT_SYMBOL(boot_option_idle_override);
 255
 256 /*
 257  * Powermanagement idle function, if any..
 258  */
 259 void (*pm_idle)(void);
 260 EXPORT_SYMBOL(pm_idle);
 261
 262 #ifdef CONFIG_X86_32
 263 /*
 264  * This halt magic was a workaround for ancient floppy DMA
 265  * wreckage. It should be safe to remove.
 266  */
 267 static int hlt_counter;
 268 void disable_hlt(void)
 269 {
 270         hlt_counter++;
 271 }
 272 EXPORT_SYMBOL(disable_hlt);
 273
 274 void enable_hlt(void)
 275 {
 276         hlt_counter--;
 277 }
 278 EXPORT_SYMBOL(enable_hlt);
 279
 280 static inline int hlt_use_halt(void)
 281 {
 282         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
 283 }
 284 #else
 285 static inline int hlt_use_halt(void)
 286 {
 287         return 1;
 288 }
 289 #endif
 290
 291 /*
 292  * We use this if we don't have any better
 293  * idle routine..
 294  */
 295 void default_idle(void)
 296 {
 297         if (hlt_use_halt()) {
 298                 struct power_trace it;
 299
 300                 trace_power_start(&it, POWER_CSTATE, 1);
 301                 current_thread_info()->status &= ~TS_POLLING;
 302                 /*
 303                  * TS_POLLING-cleared state must be visible before we
 304                  * test NEED_RESCHED:
 305                  */
 306                 smp_mb();
 307
 308                 if (!need_resched())
 309                         safe_halt();    /* enables interrupts racelessly */
 310                 else
 311                         local_irq_enable();
 312                 current_thread_info()->status |= TS_POLLING;
 313                 trace_power_end(&it);
 314         } else {
 315                 local_irq_enable();
 316                 /* loop is done by the caller */
 317                 cpu_relax();
 318         }
 319 }
 320 #ifdef CONFIG_APM_MODULE
 321 EXPORT_SYMBOL(default_idle);
 322 #endif
 323
 324 void stop_this_cpu(void *dummy)
 325 {
 326         local_irq_disable();
 327         /*
 328          * Remove this CPU:
 329          */
 330         cpu_clear(smp_processor_id(), cpu_online_map);
 331         disable_local_APIC();
 332
 333         for (;;) {
 334                 if (hlt_works(smp_processor_id()))
 335                         halt();
 336         }
 337 }
 338
 339 static void do_nothing(void *unused)
 340 {
 341 }
 342
 343 /*
 344  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
 345  * pm_idle and update to new pm_idle value. Required while changing pm_idle
 346  * handler on SMP systems.
 347  *
 348  * Caller must have changed pm_idle to the new value before the call. Old
 349  * pm_idle value will not be used by any CPU after the return of this function.
 350  */
 351 void cpu_idle_wait(void)
 352 {
 353         smp_mb();
 354         /* kick all the CPUs so that they exit out of pm_idle */
 355         smp_call_function(do_nothing, NULL, 1);
 356 }
 357 EXPORT_SYMBOL_GPL(cpu_idle_wait);
 358
 359 /*
 360  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 361  * which can obviate IPI to trigger checking of need_resched.
 362  * We execute MONITOR against need_resched and enter optimized wait state
 363  * through MWAIT. Whenever someone changes need_resched, we would be woken
 364  * up from MWAIT (without an IPI).
 365  *
 366  * New with Core Duo processors, MWAIT can take some hints based on CPU
 367  * capability.
 368  */
 369 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 370 {
 371         struct power_trace it;
 372
 373         trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
 374         if (!need_resched()) {
 375                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 376                         clflush((void *)&current_thread_info()->flags);
 377
 378                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 379                 smp_mb();
 380                 if (!need_resched())
 381                         __mwait(ax, cx);
 382         }
 383         trace_power_end(&it);
 384 }
 385
 386 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 387 static void mwait_idle(void)
 388 {
 389         struct power_trace it;
 390         if (!need_resched()) {
 391                 trace_power_start(&it, POWER_CSTATE, 1);
 392                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
 393                         clflush((void *)&current_thread_info()->flags);
 394
 395                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 396                 smp_mb();
 397                 if (!need_resched())
 398                         __sti_mwait(0, 0);
 399                 else
 400                         local_irq_enable();
 401                 trace_power_end(&it);
 402         } else
 403                 local_irq_enable();
 404 }
 405
 406 /*
 407  * On SMP it's slightly faster (but much more power-consuming!)
 408  * to poll the ->work.need_resched flag instead of waiting for the
 409  * cross-CPU IPI to arrive. Use this option with caution.
 410  */
 411 static void poll_idle(void)
 412 {
 413         struct power_trace it;
 414
 415         trace_power_start(&it, POWER_CSTATE, 0);
 416         local_irq_enable();
 417         while (!need_resched())
 418                 cpu_relax();
 419         trace_power_end(&it);
 420 }
 421
 422 /*
 423  * mwait selection logic:
 424  *
 425  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 426  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 427  * then depend on a clock divisor and current Pstate of the core. If
 428  * all cores of a processor are in halt state (C1) the processor can
 429  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 430  * happen.
 431  *
 432  * idle=mwait overrides this decision and forces the usage of mwait.
 433  */
 434 static int __cpuinitdata force_mwait;
 435
 436 #define MWAIT_INFO                      0x05
 437 #define MWAIT_ECX_EXTENDED_INFO         0x01
 438 #define MWAIT_EDX_C1                    0xf0
 439
 440 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
 441 {
 442         u32 eax, ebx, ecx, edx;
 443
 444         if (force_mwait)
 445                 return 1;
 446
 447         if (c->cpuid_level < MWAIT_INFO)
 448                 return 0;
 449
 450         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 451         /* Check, whether EDX has extended info about MWAIT */
 452         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 453                 return 1;
 454
 455         /*
 456          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 457          * C1  supports MWAIT
 458          */
 459         return (edx & MWAIT_EDX_C1);
 460 }
 461
 462 /*
 463  * Check for AMD CPUs, which have potentially C1E support
 464  */
 465 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
 466 {
 467         if (c->x86_vendor != X86_VENDOR_AMD)
 468                 return 0;
 469
 470         if (c->x86 < 0x0F)
 471                 return 0;
 472
 473         /* Family 0x0f models < rev F do not have C1E */
 474         if (c->x86 == 0x0f && c->x86_model < 0x40)
 475                 return 0;
 476
 477         return 1;
 478 }
 479
 480 static cpumask_t c1e_mask = CPU_MASK_NONE;
 481 static int c1e_detected;
 482
 483 void c1e_remove_cpu(int cpu)
 484 {
 485         cpu_clear(cpu, c1e_mask);
 486 }
 487
 488 /*
 489  * C1E aware idle routine. We check for C1E active in the interrupt
 490  * pending message MSR. If we detect C1E, then we handle it the same
 491  * way as C3 power states (local apic timer and TSC stop)
 492  */
 493 static void c1e_idle(void)
 494 {
 495         if (need_resched())
 496                 return;
 497
 498         if (!c1e_detected) {
 499                 u32 lo, hi;
 500
 501                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 502                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 503                         c1e_detected = 1;
 504                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 505                                 mark_tsc_unstable("TSC halt in AMD C1E");
 506                         printk(KERN_INFO "System has AMD C1E enabled\n");
 507                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
 508                 }
 509         }
 510
 511         if (c1e_detected) {
 512                 int cpu = smp_processor_id();
 513
 514                 if (!cpu_isset(cpu, c1e_mask)) {
 515                         cpu_set(cpu, c1e_mask);
 516                         /*
 517                          * Force broadcast so ACPI can not interfere. Needs
 518                          * to run with interrupts enabled as it uses
 519                          * smp_function_call.
 520                          */
 521                         local_irq_enable();
 522                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 523                                            &cpu);
 524                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
 525                                cpu);
 526                         local_irq_disable();
 527                 }
 528                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 529
 530                 default_idle();
 531
 532                 /*
 533                  * The switch back from broadcast mode needs to be
 534                  * called with interrupts disabled.
 535                  */
 536                  local_irq_disable();
 537                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 538                  local_irq_enable();
 539         } else
 540                 default_idle();
 541 }
 542
 543 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 544 {
 545 #ifdef CONFIG_SMP
 546         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 547                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
 548                         " performance may degrade.\n");
 549         }
 550 #endif
 551         if (pm_idle)
 552                 return;
 553
 554         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 555                 /*
 556                  * One CPU supports mwait => All CPUs supports mwait
 557                  */
 558                 printk(KERN_INFO "using mwait in idle threads.\n");
 559                 pm_idle = mwait_idle;
 560         } else if (check_c1e_idle(c)) {
 561                 printk(KERN_INFO "using C1E aware idle routine\n");
 562                 pm_idle = c1e_idle;
 563         } else
 564                 pm_idle = default_idle;
 565 }
 566
 567 static int __init idle_setup(char *str)
 568 {
 569         if (!str)
 570                 return -EINVAL;
 571
 572         if (!strcmp(str, "poll")) {
 573                 printk("using polling idle threads.\n");
 574                 pm_idle = poll_idle;
 575         } else if (!strcmp(str, "mwait"))
 576                 force_mwait = 1;
 577         else if (!strcmp(str, "halt")) {
 578                 /*
 579                  * When the boot option of idle=halt is added, halt is
 580                  * forced to be used for CPU idle. In such case CPU C2/C3
 581                  * won't be used again.
 582                  * To continue to load the CPU idle driver, don't touch
 583                  * the boot_option_idle_override.
 584                  */
 585                 pm_idle = default_idle;
 586                 idle_halt = 1;
 587                 return 0;
 588         } else if (!strcmp(str, "nomwait")) {
 589                 /*
 590                  * If the boot option of "idle=nomwait" is added,
 591                  * it means that mwait will be disabled for CPU C2/C3
 592                  * states. In such case it won't touch the variable
 593                  * of boot_option_idle_override.
 594                  */
 595                 idle_nomwait = 1;
 596                 return 0;
 597         } else
 598                 return -1;
 599
 600         boot_option_idle_override = 1;
 601         return 0;
 602 }
 603 early_param("idle", idle_setup);
 604