2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
68 #include <asm/setup.h>
69 #include <asm/uv/uv.h>
70 #include <linux/mc146818rtc.h>
72 #include <asm/smpboot_hooks.h>
73 #include <asm/i8259.h>
76 u8 apicid_2_node[MAX_APICID];
79 /* State of each CPU */
80 DEFINE_PER_CPU(int, cpu_state) = { 0 };
82 /* Store all idle threads, this can be reused instead of creating
83 * a new thread. Also avoids complicated thread destroy functionality
86 #ifdef CONFIG_HOTPLUG_CPU
88 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
89 * removed after init for !CONFIG_HOTPLUG_CPU.
91 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
92 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
93 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
96 * We need this for trampoline_base protection from concurrent accesses when
97 * off- and onlining cores wildly.
99 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
101 void cpu_hotplug_driver_lock()
103 mutex_lock(&x86_cpu_hotplug_driver_mutex);
106 void cpu_hotplug_driver_unlock()
108 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
111 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
112 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
114 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
115 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
116 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
119 /* Number of siblings per CPU package */
120 int smp_num_siblings = 1;
121 EXPORT_SYMBOL(smp_num_siblings);
123 /* Last level cache ID of each logical CPU */
124 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
126 /* representing HT siblings of each logical CPU */
127 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
128 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
130 /* representing HT and core siblings of each logical CPU */
131 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
132 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
134 /* Per CPU bogomips and other parameters */
135 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
136 EXPORT_PER_CPU_SYMBOL(cpu_info);
138 atomic_t init_deasserted;
140 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
141 /* which node each logical CPU is on */
142 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
143 EXPORT_SYMBOL(cpu_to_node_map);
145 /* set up a mapping between cpu and node. */
146 static void map_cpu_to_node(int cpu, int node)
148 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
149 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
150 cpu_to_node_map[cpu] = node;
153 /* undo a mapping between cpu and node. */
154 static void unmap_cpu_to_node(int cpu)
158 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
159 for (node = 0; node < MAX_NUMNODES; node++)
160 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
161 cpu_to_node_map[cpu] = 0;
163 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
164 #define map_cpu_to_node(cpu, node) ({})
165 #define unmap_cpu_to_node(cpu) ({})
169 static int boot_cpu_logical_apicid;
171 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
172 { [0 ... NR_CPUS-1] = BAD_APICID };
174 static void map_cpu_to_logical_apicid(void)
176 int cpu = smp_processor_id();
177 int apicid = logical_smp_processor_id();
178 int node = apic->apicid_to_node(apicid);
180 if (!node_online(node))
181 node = first_online_node;
183 cpu_2_logical_apicid[cpu] = apicid;
184 map_cpu_to_node(cpu, node);
187 void numa_remove_cpu(int cpu)
189 cpu_2_logical_apicid[cpu] = BAD_APICID;
190 unmap_cpu_to_node(cpu);
193 #define map_cpu_to_logical_apicid() do {} while (0)
197 * Report back to the Boot Processor.
200 static void __cpuinit smp_callin(void)
203 unsigned long timeout;
206 * If waken up by an INIT in an 82489DX configuration
207 * we may get here before an INIT-deassert IPI reaches
208 * our local APIC. We have to wait for the IPI or we'll
209 * lock up on an APIC access.
211 if (apic->wait_for_init_deassert)
212 apic->wait_for_init_deassert(&init_deasserted);
215 * (This works even if the APIC is not enabled.)
217 phys_id = read_apic_id();
218 cpuid = smp_processor_id();
219 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
220 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
223 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
226 * STARTUP IPIs are fragile beasts as they might sometimes
227 * trigger some glue motherboard logic. Complete APIC bus
228 * silence for 1 second, this overestimates the time the
229 * boot CPU is spending to send the up to 2 STARTUP IPIs
230 * by a factor of two. This should be enough.
234 * Waiting 2s total for startup (udelay is not yet working)
236 timeout = jiffies + 2*HZ;
237 while (time_before(jiffies, timeout)) {
239 * Has the boot CPU finished it's STARTUP sequence?
241 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
246 if (!time_before(jiffies, timeout)) {
247 panic("%s: CPU%d started up but did not get a callout!\n",
252 * the boot CPU has finished the init stage and is spinning
253 * on callin_map until we finish. We are free to set up this
254 * CPU, first the APIC. (this is probably redundant on most
258 pr_debug("CALLIN, before setup_local_APIC().\n");
259 if (apic->smp_callin_clear_local_apic)
260 apic->smp_callin_clear_local_apic();
262 end_local_APIC_setup();
263 map_cpu_to_logical_apicid();
266 * Need to setup vector mappings before we enable interrupts.
268 setup_vector_irq(smp_processor_id());
272 * Need to enable IRQs because it can take longer and then
273 * the NMI watchdog might kill us.
278 pr_debug("Stack at about %p\n", &cpuid);
281 * Save our processor parameters
283 smp_store_cpu_info(cpuid);
285 notify_cpu_starting(cpuid);
288 * Allow the master to continue.
290 cpumask_set_cpu(cpuid, cpu_callin_mask);
294 * Activate a secondary processor.
296 notrace static void __cpuinit start_secondary(void *unused)
299 * Don't put *anything* before cpu_init(), SMP booting is too
300 * fragile that we want to limit the things done here to the
301 * most necessary things.
306 * Switch away from the trampoline page-table
308 * Do this before cpu_init() because it needs to access per-cpu
309 * data which may not be mapped in the trampoline page-table.
311 load_cr3(swapper_pg_dir);
320 /* otherwise gcc will move up smp_processor_id before the cpu_init */
323 * Check TSC synchronization with the BP:
325 check_tsc_sync_target();
327 if (nmi_watchdog == NMI_IO_APIC) {
328 legacy_pic->chip->mask(0);
329 enable_NMI_through_LVT0();
330 legacy_pic->chip->unmask(0);
333 /* This must be done before setting cpu_online_mask */
334 set_cpu_sibling_map(raw_smp_processor_id());
338 * We need to hold call_lock, so there is no inconsistency
339 * between the time smp_call_function() determines number of
340 * IPI recipients, and the time when the determination is made
341 * for which cpus receive the IPI. Holding this
342 * lock helps us to not include this cpu in a currently in progress
343 * smp_call_function().
345 * We need to hold vector_lock so there the set of online cpus
346 * does not change while we are assigning vectors to cpus. Holding
347 * this lock ensures we don't half assign or remove an irq from a cpu.
351 set_cpu_online(smp_processor_id(), true);
352 unlock_vector_lock();
354 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
355 x86_platform.nmi_init();
357 /* enable local interrupts */
360 /* to prevent fake stack check failure in clock setup */
361 boot_init_stack_canary();
363 x86_cpuinit.setup_percpu_clockev();
369 #ifdef CONFIG_CPUMASK_OFFSTACK
370 /* In this case, llc_shared_map is a pointer to a cpumask. */
371 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
372 const struct cpuinfo_x86 *src)
374 struct cpumask *llc = dst->llc_shared_map;
376 dst->llc_shared_map = llc;
379 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
380 const struct cpuinfo_x86 *src)
384 #endif /* CONFIG_CPUMASK_OFFSTACK */
387 * The bootstrap kernel entry code has set these up. Save them for
391 void __cpuinit smp_store_cpu_info(int id)
393 struct cpuinfo_x86 *c = &cpu_data(id);
395 copy_cpuinfo_x86(c, &boot_cpu_data);
398 identify_secondary_cpu(c);
401 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
403 struct cpuinfo_x86 *c1 = &cpu_data(cpu1);
404 struct cpuinfo_x86 *c2 = &cpu_data(cpu2);
406 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
407 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
408 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
409 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
410 cpumask_set_cpu(cpu1, c2->llc_shared_map);
411 cpumask_set_cpu(cpu2, c1->llc_shared_map);
415 void __cpuinit set_cpu_sibling_map(int cpu)
418 struct cpuinfo_x86 *c = &cpu_data(cpu);
420 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
422 if (smp_num_siblings > 1) {
423 for_each_cpu(i, cpu_sibling_setup_mask) {
424 struct cpuinfo_x86 *o = &cpu_data(i);
426 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
427 if (c->phys_proc_id == o->phys_proc_id &&
428 c->compute_unit_id == o->compute_unit_id)
429 link_thread_siblings(cpu, i);
430 } else if (c->phys_proc_id == o->phys_proc_id &&
431 c->cpu_core_id == o->cpu_core_id) {
432 link_thread_siblings(cpu, i);
436 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
439 cpumask_set_cpu(cpu, c->llc_shared_map);
441 if (current_cpu_data.x86_max_cores == 1) {
442 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
447 for_each_cpu(i, cpu_sibling_setup_mask) {
448 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
449 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
450 cpumask_set_cpu(i, c->llc_shared_map);
451 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map);
453 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
454 cpumask_set_cpu(i, cpu_core_mask(cpu));
455 cpumask_set_cpu(cpu, cpu_core_mask(i));
457 * Does this new cpu bringup a new core?
459 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
461 * for each core in package, increment
462 * the booted_cores for this new cpu
464 if (cpumask_first(cpu_sibling_mask(i)) == i)
467 * increment the core count for all
468 * the other cpus in this package
471 cpu_data(i).booted_cores++;
472 } else if (i != cpu && !c->booted_cores)
473 c->booted_cores = cpu_data(i).booted_cores;
478 /* maps the cpu to the sched domain representing multi-core */
479 const struct cpumask *cpu_coregroup_mask(int cpu)
481 struct cpuinfo_x86 *c = &cpu_data(cpu);
483 * For perf, we return last level cache shared map.
484 * And for power savings, we return cpu_core_map
486 if ((sched_mc_power_savings || sched_smt_power_savings) &&
487 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
488 return cpu_core_mask(cpu);
490 return c->llc_shared_map;
493 static void impress_friends(void)
496 unsigned long bogosum = 0;
498 * Allow the user to impress friends.
500 pr_debug("Before bogomips.\n");
501 for_each_possible_cpu(cpu)
502 if (cpumask_test_cpu(cpu, cpu_callout_mask))
503 bogosum += cpu_data(cpu).loops_per_jiffy;
505 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
508 (bogosum/(5000/HZ))%100);
510 pr_debug("Before bogocount - setting activated=1.\n");
513 void __inquire_remote_apic(int apicid)
515 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
516 char *names[] = { "ID", "VERSION", "SPIV" };
520 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
522 for (i = 0; i < ARRAY_SIZE(regs); i++) {
523 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
528 status = safe_apic_wait_icr_idle();
531 "a previous APIC delivery may have failed\n");
533 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
538 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
539 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
542 case APIC_ICR_RR_VALID:
543 status = apic_read(APIC_RRR);
544 printk(KERN_CONT "%08x\n", status);
547 printk(KERN_CONT "failed\n");
553 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
554 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
555 * won't ... remember to clear down the APIC, etc later.
558 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
560 unsigned long send_status, accept_status = 0;
564 /* Boot on the stack */
565 /* Kick the second */
566 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
568 pr_debug("Waiting for send to finish...\n");
569 send_status = safe_apic_wait_icr_idle();
572 * Give the other CPU some time to accept the IPI.
575 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
576 maxlvt = lapic_get_maxlvt();
577 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
578 apic_write(APIC_ESR, 0);
579 accept_status = (apic_read(APIC_ESR) & 0xEF);
581 pr_debug("NMI sent.\n");
584 printk(KERN_ERR "APIC never delivered???\n");
586 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
588 return (send_status | accept_status);
592 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
594 unsigned long send_status, accept_status = 0;
595 int maxlvt, num_starts, j;
597 maxlvt = lapic_get_maxlvt();
600 * Be paranoid about clearing APIC errors.
602 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
603 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
604 apic_write(APIC_ESR, 0);
608 pr_debug("Asserting INIT.\n");
611 * Turn INIT on target chip
616 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
619 pr_debug("Waiting for send to finish...\n");
620 send_status = safe_apic_wait_icr_idle();
624 pr_debug("Deasserting INIT.\n");
628 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
630 pr_debug("Waiting for send to finish...\n");
631 send_status = safe_apic_wait_icr_idle();
634 atomic_set(&init_deasserted, 1);
637 * Should we send STARTUP IPIs ?
639 * Determine this based on the APIC version.
640 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
642 if (APIC_INTEGRATED(apic_version[phys_apicid]))
648 * Paravirt / VMI wants a startup IPI hook here to set up the
649 * target processor state.
651 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
652 (unsigned long)stack_start.sp);
655 * Run STARTUP IPI loop.
657 pr_debug("#startup loops: %d.\n", num_starts);
659 for (j = 1; j <= num_starts; j++) {
660 pr_debug("Sending STARTUP #%d.\n", j);
661 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
662 apic_write(APIC_ESR, 0);
664 pr_debug("After apic_write.\n");
671 /* Boot on the stack */
672 /* Kick the second */
673 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
677 * Give the other CPU some time to accept the IPI.
681 pr_debug("Startup point 1.\n");
683 pr_debug("Waiting for send to finish...\n");
684 send_status = safe_apic_wait_icr_idle();
687 * Give the other CPU some time to accept the IPI.
690 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
691 apic_write(APIC_ESR, 0);
692 accept_status = (apic_read(APIC_ESR) & 0xEF);
693 if (send_status || accept_status)
696 pr_debug("After Startup.\n");
699 printk(KERN_ERR "APIC never delivered???\n");
701 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
703 return (send_status | accept_status);
707 struct work_struct work;
708 struct task_struct *idle;
709 struct completion done;
713 static void __cpuinit do_fork_idle(struct work_struct *work)
715 struct create_idle *c_idle =
716 container_of(work, struct create_idle, work);
718 c_idle->idle = fork_idle(c_idle->cpu);
719 complete(&c_idle->done);
722 /* reduce the number of lines printed when booting a large cpu count system */
723 static void __cpuinit announce_cpu(int cpu, int apicid)
725 static int current_node = -1;
726 int node = early_cpu_to_node(cpu);
728 if (system_state == SYSTEM_BOOTING) {
729 if (node != current_node) {
730 if (current_node > (-1))
733 pr_info("Booting Node %3d, Processors ", node);
735 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
738 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
743 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
744 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
745 * Returns zero if CPU booted OK, else error code from
746 * ->wakeup_secondary_cpu.
748 static int __cpuinit do_boot_cpu(int apicid, int cpu)
750 unsigned long boot_error = 0;
751 unsigned long start_ip;
753 struct create_idle c_idle = {
755 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
758 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle);
760 alternatives_smp_switch(1);
762 c_idle.idle = get_idle_for_cpu(cpu);
765 * We can't use kernel_thread since we must avoid to
766 * reschedule the child.
769 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
770 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
771 init_idle(c_idle.idle, cpu);
775 schedule_work(&c_idle.work);
776 wait_for_completion(&c_idle.done);
778 if (IS_ERR(c_idle.idle)) {
779 printk("failed fork for CPU %d\n", cpu);
780 destroy_work_on_stack(&c_idle.work);
781 return PTR_ERR(c_idle.idle);
784 set_idle_for_cpu(cpu, c_idle.idle);
786 per_cpu(current_task, cpu) = c_idle.idle;
788 /* Stack for startup_32 can be just as for start_secondary onwards */
790 initial_page_table = __pa(&trampoline_pg_dir);
792 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
793 initial_gs = per_cpu_offset(cpu);
794 per_cpu(kernel_stack, cpu) =
795 (unsigned long)task_stack_page(c_idle.idle) -
796 KERNEL_STACK_OFFSET + THREAD_SIZE;
798 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
799 initial_code = (unsigned long)start_secondary;
800 stack_start.sp = (void *) c_idle.idle->thread.sp;
802 /* start_ip had better be page-aligned! */
803 start_ip = setup_trampoline();
805 /* So we see what's up */
806 announce_cpu(cpu, apicid);
809 * This grunge runs the startup process for
810 * the targeted processor.
813 atomic_set(&init_deasserted, 0);
815 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
817 pr_debug("Setting warm reset code and vector.\n");
819 smpboot_setup_warm_reset_vector(start_ip);
821 * Be paranoid about clearing APIC errors.
823 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
824 apic_write(APIC_ESR, 0);
830 * Kick the secondary CPU. Use the method in the APIC driver
831 * if it's defined - or use an INIT boot APIC message otherwise:
833 if (apic->wakeup_secondary_cpu)
834 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
836 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
840 * allow APs to start initializing.
842 pr_debug("Before Callout %d.\n", cpu);
843 cpumask_set_cpu(cpu, cpu_callout_mask);
844 pr_debug("After Callout %d.\n", cpu);
847 * Wait 5s total for a response
849 for (timeout = 0; timeout < 50000; timeout++) {
850 if (cpumask_test_cpu(cpu, cpu_callin_mask))
851 break; /* It has booted */
854 * Allow other tasks to run while we wait for the
855 * AP to come online. This also gives a chance
856 * for the MTRR work(triggered by the AP coming online)
857 * to be completed in the stop machine context.
862 if (cpumask_test_cpu(cpu, cpu_callin_mask))
863 pr_debug("CPU%d: has booted.\n", cpu);
866 if (*((volatile unsigned char *)trampoline_base)
868 /* trampoline started but...? */
869 pr_err("CPU%d: Stuck ??\n", cpu);
871 /* trampoline code not run */
872 pr_err("CPU%d: Not responding.\n", cpu);
873 if (apic->inquire_remote_apic)
874 apic->inquire_remote_apic(apicid);
879 /* Try to put things back the way they were before ... */
880 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
882 /* was set by do_boot_cpu() */
883 cpumask_clear_cpu(cpu, cpu_callout_mask);
885 /* was set by cpu_init() */
886 cpumask_clear_cpu(cpu, cpu_initialized_mask);
888 set_cpu_present(cpu, false);
889 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
892 /* mark "stuck" area as not stuck */
893 *((volatile unsigned long *)trampoline_base) = 0;
895 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
897 * Cleanup possible dangling ends...
899 smpboot_restore_warm_reset_vector();
902 destroy_work_on_stack(&c_idle.work);
906 int __cpuinit native_cpu_up(unsigned int cpu)
908 int apicid = apic->cpu_present_to_apicid(cpu);
912 WARN_ON(irqs_disabled());
914 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
916 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
917 !physid_isset(apicid, phys_cpu_present_map)) {
918 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
923 * Already booted CPU?
925 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
926 pr_debug("do_boot_cpu %d Already started\n", cpu);
931 * Save current MTRR state in case it was changed since early boot
932 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
936 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
938 err = do_boot_cpu(apicid, cpu);
941 pr_debug("do_boot_cpu failed %d\n", err);
946 * Check TSC synchronization with the AP (keep irqs disabled
949 local_irq_save(flags);
950 check_tsc_sync_source(cpu);
951 local_irq_restore(flags);
953 while (!cpu_online(cpu)) {
955 touch_nmi_watchdog();
962 * Fall back to non SMP mode after errors.
964 * RED-PEN audit/test this more. I bet there is more state messed up here.
966 static __init void disable_smp(void)
968 init_cpu_present(cpumask_of(0));
969 init_cpu_possible(cpumask_of(0));
970 smpboot_clear_io_apic_irqs();
972 if (smp_found_config)
973 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
975 physid_set_mask_of_physid(0, &phys_cpu_present_map);
976 map_cpu_to_logical_apicid();
977 cpumask_set_cpu(0, cpu_sibling_mask(0));
978 cpumask_set_cpu(0, cpu_core_mask(0));
982 * Various sanity checks.
984 static int __init smp_sanity_check(unsigned max_cpus)
988 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
989 if (def_to_bigsmp && nr_cpu_ids > 8) {
994 "More than 8 CPUs detected - skipping them.\n"
995 "Use CONFIG_X86_BIGSMP.\n");
998 for_each_present_cpu(cpu) {
1000 set_cpu_present(cpu, false);
1005 for_each_possible_cpu(cpu) {
1007 set_cpu_possible(cpu, false);
1015 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1017 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1018 hard_smp_processor_id());
1020 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1024 * If we couldn't find an SMP configuration at boot time,
1025 * get out of here now!
1027 if (!smp_found_config && !acpi_lapic) {
1029 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1031 if (APIC_init_uniprocessor())
1032 printk(KERN_NOTICE "Local APIC not detected."
1033 " Using dummy APIC emulation.\n");
1038 * Should not be necessary because the MP table should list the boot
1039 * CPU too, but we do it for the sake of robustness anyway.
1041 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1043 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1044 boot_cpu_physical_apicid);
1045 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1050 * If we couldn't find a local APIC, then get out of here now!
1052 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1054 if (!disable_apic) {
1055 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1056 boot_cpu_physical_apicid);
1057 pr_err("... forcing use of dummy APIC emulation."
1058 "(tell your hw vendor)\n");
1060 smpboot_clear_io_apic();
1061 arch_disable_smp_support();
1065 verify_local_APIC();
1068 * If SMP should be disabled, then really disable it!
1071 printk(KERN_INFO "SMP mode deactivated.\n");
1072 smpboot_clear_io_apic();
1074 localise_nmi_watchdog();
1078 end_local_APIC_setup();
1085 static void __init smp_cpu_index_default(void)
1088 struct cpuinfo_x86 *c;
1090 for_each_possible_cpu(i) {
1092 /* mark all to hotplug */
1093 c->cpu_index = nr_cpu_ids;
1098 * Prepare for SMP bootup. The MP table or ACPI has been read
1099 * earlier. Just do some sanity checking here and enable APIC mode.
1101 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1106 smp_cpu_index_default();
1107 current_cpu_data = boot_cpu_data;
1108 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1111 * Setup boot CPU information
1113 smp_store_cpu_info(0); /* Final full version of the data */
1114 #ifdef CONFIG_X86_32
1115 boot_cpu_logical_apicid = logical_smp_processor_id();
1117 current_thread_info()->cpu = 0; /* needed? */
1118 for_each_possible_cpu(i) {
1119 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1120 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1121 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL);
1123 set_cpu_sibling_map(0);
1126 default_setup_apic_routing();
1128 if (smp_sanity_check(max_cpus) < 0) {
1129 printk(KERN_INFO "SMP disabled\n");
1135 if (read_apic_id() != boot_cpu_physical_apicid) {
1136 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1137 read_apic_id(), boot_cpu_physical_apicid);
1138 /* Or can we switch back to PIC here? */
1145 * Switch from PIC to APIC mode.
1150 * Enable IO APIC before setting up error vector
1152 if (!skip_ioapic_setup && nr_ioapics)
1155 end_local_APIC_setup();
1157 map_cpu_to_logical_apicid();
1159 if (apic->setup_portio_remap)
1160 apic->setup_portio_remap();
1162 smpboot_setup_io_apic();
1164 * Set up local APIC timer on boot CPU.
1167 printk(KERN_INFO "CPU%d: ", 0);
1168 print_cpu_info(&cpu_data(0));
1169 x86_init.timers.setup_percpu_clockev();
1174 set_mtrr_aps_delayed_init();
1179 void arch_enable_nonboot_cpus_begin(void)
1181 set_mtrr_aps_delayed_init();
1184 void arch_enable_nonboot_cpus_end(void)
1190 * Early setup to make printk work.
1192 void __init native_smp_prepare_boot_cpu(void)
1194 int me = smp_processor_id();
1195 switch_to_new_gdt(me);
1196 /* already set me in cpu_online_mask in boot_cpu_init() */
1197 cpumask_set_cpu(me, cpu_callout_mask);
1198 per_cpu(cpu_state, me) = CPU_ONLINE;
1201 void __init native_smp_cpus_done(unsigned int max_cpus)
1203 pr_debug("Boot done.\n");
1206 #ifdef CONFIG_X86_IO_APIC
1207 setup_ioapic_dest();
1209 check_nmi_watchdog();
1213 static int __initdata setup_possible_cpus = -1;
1214 static int __init _setup_possible_cpus(char *str)
1216 get_option(&str, &setup_possible_cpus);
1219 early_param("possible_cpus", _setup_possible_cpus);
1223 * cpu_possible_mask should be static, it cannot change as cpu's
1224 * are onlined, or offlined. The reason is per-cpu data-structures
1225 * are allocated by some modules at init time, and dont expect to
1226 * do this dynamically on cpu arrival/departure.
1227 * cpu_present_mask on the other hand can change dynamically.
1228 * In case when cpu_hotplug is not compiled, then we resort to current
1229 * behaviour, which is cpu_possible == cpu_present.
1232 * Three ways to find out the number of additional hotplug CPUs:
1233 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1234 * - The user can overwrite it with possible_cpus=NUM
1235 * - Otherwise don't reserve additional CPUs.
1236 * We do this because additional CPUs waste a lot of memory.
1239 __init void prefill_possible_map(void)
1243 /* no processor from mptable or madt */
1244 if (!num_processors)
1247 i = setup_max_cpus ?: 1;
1248 if (setup_possible_cpus == -1) {
1249 possible = num_processors;
1250 #ifdef CONFIG_HOTPLUG_CPU
1252 possible += disabled_cpus;
1258 possible = setup_possible_cpus;
1260 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1262 /* nr_cpu_ids could be reduced via nr_cpus= */
1263 if (possible > nr_cpu_ids) {
1265 "%d Processors exceeds NR_CPUS limit of %d\n",
1266 possible, nr_cpu_ids);
1267 possible = nr_cpu_ids;
1270 #ifdef CONFIG_HOTPLUG_CPU
1271 if (!setup_max_cpus)
1275 "%d Processors exceeds max_cpus limit of %u\n",
1276 possible, setup_max_cpus);
1280 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1281 possible, max_t(int, possible - num_processors, 0));
1283 for (i = 0; i < possible; i++)
1284 set_cpu_possible(i, true);
1285 for (; i < NR_CPUS; i++)
1286 set_cpu_possible(i, false);
1288 nr_cpu_ids = possible;
1291 #ifdef CONFIG_HOTPLUG_CPU
1293 static void remove_siblinginfo(int cpu)
1296 struct cpuinfo_x86 *c = &cpu_data(cpu);
1298 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1299 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1301 * last thread sibling in this cpu core going down
1303 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1304 cpu_data(sibling).booted_cores--;
1307 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1308 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1309 cpumask_clear(cpu_sibling_mask(cpu));
1310 cpumask_clear(cpu_core_mask(cpu));
1311 c->phys_proc_id = 0;
1313 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1316 static void __ref remove_cpu_from_maps(int cpu)
1318 set_cpu_online(cpu, false);
1319 cpumask_clear_cpu(cpu, cpu_callout_mask);
1320 cpumask_clear_cpu(cpu, cpu_callin_mask);
1321 /* was set by cpu_init() */
1322 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1323 numa_remove_cpu(cpu);
1326 void cpu_disable_common(void)
1328 int cpu = smp_processor_id();
1330 remove_siblinginfo(cpu);
1332 /* It's now safe to remove this processor from the online map */
1334 remove_cpu_from_maps(cpu);
1335 unlock_vector_lock();
1339 int native_cpu_disable(void)
1341 int cpu = smp_processor_id();
1344 * Perhaps use cpufreq to drop frequency, but that could go
1345 * into generic code.
1347 * We won't take down the boot processor on i386 due to some
1348 * interrupts only being able to be serviced by the BSP.
1349 * Especially so if we're not using an IOAPIC -zwane
1354 if (nmi_watchdog == NMI_LOCAL_APIC)
1355 stop_apic_nmi_watchdog(NULL);
1358 cpu_disable_common();
1362 void native_cpu_die(unsigned int cpu)
1364 /* We don't do anything here: idle task is faking death itself. */
1367 for (i = 0; i < 10; i++) {
1368 /* They ack this in play_dead by setting CPU_DEAD */
1369 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1370 if (system_state == SYSTEM_RUNNING)
1371 pr_info("CPU %u is now offline\n", cpu);
1373 if (1 == num_online_cpus())
1374 alternatives_smp_switch(0);
1379 pr_err("CPU %u didn't die...\n", cpu);
1382 void play_dead_common(void)
1385 reset_lazy_tlbstate();
1386 irq_ctx_exit(raw_smp_processor_id());
1387 c1e_remove_cpu(raw_smp_processor_id());
1391 __get_cpu_var(cpu_state) = CPU_DEAD;
1394 * With physical CPU hotplug, we should halt the cpu
1396 local_irq_disable();
1400 * We need to flush the caches before going to sleep, lest we have
1401 * dirty data in our caches when we come back up.
1403 static inline void mwait_play_dead(void)
1405 unsigned int eax, ebx, ecx, edx;
1406 unsigned int highest_cstate = 0;
1407 unsigned int highest_subcstate = 0;
1411 if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT))
1413 if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH))
1415 if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1418 eax = CPUID_MWAIT_LEAF;
1420 native_cpuid(&eax, &ebx, &ecx, &edx);
1423 * eax will be 0 if EDX enumeration is not valid.
1424 * Initialized below to cstate, sub_cstate value when EDX is valid.
1426 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1429 edx >>= MWAIT_SUBSTATE_SIZE;
1430 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1431 if (edx & MWAIT_SUBSTATE_MASK) {
1433 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1436 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1437 (highest_subcstate - 1);
1441 * This should be a memory location in a cache line which is
1442 * unlikely to be touched by other processors. The actual
1443 * content is immaterial as it is not actually modified in any way.
1445 mwait_ptr = ¤t_thread_info()->flags;
1451 * The CLFLUSH is a workaround for erratum AAI65 for
1452 * the Xeon 7400 series. It's not clear it is actually
1453 * needed, but it should be harmless in either case.
1454 * The WBINVD is insufficient due to the spurious-wakeup
1455 * case where we return around the loop.
1458 __monitor(mwait_ptr, 0, 0);
1464 static inline void hlt_play_dead(void)
1466 if (current_cpu_data.x86 >= 4)
1474 void native_play_dead(void)
1477 tboot_shutdown(TB_SHUTDOWN_WFS);
1479 mwait_play_dead(); /* Only returns on failure */
1483 #else /* ... !CONFIG_HOTPLUG_CPU */
1484 int native_cpu_disable(void)
1489 void native_cpu_die(unsigned int cpu)
1491 /* We said "no" in __cpu_disable */
1495 void native_play_dead(void)