2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
53 #include <linux/cpuidle.h>
60 #include <asm/realmode.h>
63 #include <asm/pgtable.h>
64 #include <asm/tlbflush.h>
66 #include <asm/mwait.h>
68 #include <asm/io_apic.h>
69 #include <asm/setup.h>
70 #include <asm/uv/uv.h>
71 #include <linux/mc146818rtc.h>
73 #include <asm/smpboot_hooks.h>
74 #include <asm/i8259.h>
76 #include <asm/realmode.h>
78 /* State of each CPU */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
81 #ifdef CONFIG_HOTPLUG_CPU
83 * We need this for trampoline_base protection from concurrent accesses when
84 * off- and onlining cores wildly.
86 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
88 void cpu_hotplug_driver_lock(void)
90 mutex_lock(&x86_cpu_hotplug_driver_mutex);
93 void cpu_hotplug_driver_unlock(void)
95 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
98 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
99 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
102 /* Number of siblings per CPU package */
103 int smp_num_siblings = 1;
104 EXPORT_SYMBOL(smp_num_siblings);
106 /* Last level cache ID of each logical CPU */
107 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
109 /* representing HT siblings of each logical CPU */
110 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
111 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
113 /* representing HT and core siblings of each logical CPU */
114 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
115 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
117 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
119 /* Per CPU bogomips and other parameters */
120 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
121 EXPORT_PER_CPU_SYMBOL(cpu_info);
123 atomic_t init_deasserted;
126 * Report back to the Boot Processor.
129 static void __cpuinit smp_callin(void)
132 unsigned long timeout;
135 * If waken up by an INIT in an 82489DX configuration
136 * we may get here before an INIT-deassert IPI reaches
137 * our local APIC. We have to wait for the IPI or we'll
138 * lock up on an APIC access.
140 if (apic->wait_for_init_deassert)
141 apic->wait_for_init_deassert(&init_deasserted);
144 * (This works even if the APIC is not enabled.)
146 phys_id = read_apic_id();
147 cpuid = smp_processor_id();
148 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
149 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
152 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
155 * STARTUP IPIs are fragile beasts as they might sometimes
156 * trigger some glue motherboard logic. Complete APIC bus
157 * silence for 1 second, this overestimates the time the
158 * boot CPU is spending to send the up to 2 STARTUP IPIs
159 * by a factor of two. This should be enough.
163 * Waiting 2s total for startup (udelay is not yet working)
165 timeout = jiffies + 2*HZ;
166 while (time_before(jiffies, timeout)) {
168 * Has the boot CPU finished it's STARTUP sequence?
170 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
175 if (!time_before(jiffies, timeout)) {
176 panic("%s: CPU%d started up but did not get a callout!\n",
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
187 pr_debug("CALLIN, before setup_local_APIC().\n");
188 if (apic->smp_callin_clear_local_apic)
189 apic->smp_callin_clear_local_apic();
191 end_local_APIC_setup();
194 * Need to setup vector mappings before we enable interrupts.
196 setup_vector_irq(smp_processor_id());
199 * Save our processor parameters. Note: this information
200 * is needed for clock calibration.
202 smp_store_cpu_info(cpuid);
206 * Update loops_per_jiffy in cpu_data. Previous call to
207 * smp_store_cpu_info() stored a value that is close but not as
208 * accurate as the value just calculated.
211 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
212 pr_debug("Stack at about %p\n", &cpuid);
215 * This must be done before setting cpu_online_mask
216 * or calling notify_cpu_starting.
218 set_cpu_sibling_map(raw_smp_processor_id());
221 notify_cpu_starting(cpuid);
224 * Allow the master to continue.
226 cpumask_set_cpu(cpuid, cpu_callin_mask);
230 * Activate a secondary processor.
232 notrace static void __cpuinit start_secondary(void *unused)
235 * Don't put *anything* before cpu_init(), SMP booting is too
236 * fragile that we want to limit the things done here to the
237 * most necessary things.
240 x86_cpuinit.early_percpu_clock_init();
245 /* switch away from the initial page table */
246 load_cr3(swapper_pg_dir);
250 /* otherwise gcc will move up smp_processor_id before the cpu_init */
253 * Check TSC synchronization with the BP:
255 check_tsc_sync_target();
258 * We need to hold vector_lock so there the set of online cpus
259 * does not change while we are assigning vectors to cpus. Holding
260 * this lock ensures we don't half assign or remove an irq from a cpu.
263 set_cpu_online(smp_processor_id(), true);
264 unlock_vector_lock();
265 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
266 x86_platform.nmi_init();
268 /* enable local interrupts */
271 /* to prevent fake stack check failure in clock setup */
272 boot_init_stack_canary();
274 x86_cpuinit.setup_percpu_clockev();
281 * The bootstrap kernel entry code has set these up. Save them for
285 void __cpuinit smp_store_cpu_info(int id)
287 struct cpuinfo_x86 *c = &cpu_data(id);
292 identify_secondary_cpu(c);
295 static bool __cpuinit
296 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
298 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
300 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
301 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
302 "[node: %d != %d]. Ignoring dependency.\n",
303 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
306 #define link_mask(_m, c1, c2) \
308 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
309 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
312 static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
314 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
315 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
317 if (c->phys_proc_id == o->phys_proc_id &&
318 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
319 c->compute_unit_id == o->compute_unit_id)
320 return topology_sane(c, o, "smt");
322 } else if (c->phys_proc_id == o->phys_proc_id &&
323 c->cpu_core_id == o->cpu_core_id) {
324 return topology_sane(c, o, "smt");
330 static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
332 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
334 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
335 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
336 return topology_sane(c, o, "llc");
341 static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
343 if (c->phys_proc_id == o->phys_proc_id) {
344 if (cpu_has(c, X86_FEATURE_AMD_DCM))
347 return topology_sane(c, o, "mc");
352 void __cpuinit set_cpu_sibling_map(int cpu)
354 bool has_mc = boot_cpu_data.x86_max_cores > 1;
355 bool has_smt = smp_num_siblings > 1;
356 struct cpuinfo_x86 *c = &cpu_data(cpu);
357 struct cpuinfo_x86 *o;
360 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
362 if (!has_smt && !has_mc) {
363 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
365 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
370 for_each_cpu(i, cpu_sibling_setup_mask) {
373 if ((i == cpu) || (has_smt && match_smt(c, o)))
374 link_mask(sibling, cpu, i);
376 if ((i == cpu) || (has_mc && match_llc(c, o)))
377 link_mask(llc_shared, cpu, i);
382 * This needs a separate iteration over the cpus because we rely on all
383 * cpu_sibling_mask links to be set-up.
385 for_each_cpu(i, cpu_sibling_setup_mask) {
388 if ((i == cpu) || (has_mc && match_mc(c, o))) {
389 link_mask(core, cpu, i);
392 * Does this new cpu bringup a new core?
394 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
396 * for each core in package, increment
397 * the booted_cores for this new cpu
399 if (cpumask_first(cpu_sibling_mask(i)) == i)
402 * increment the core count for all
403 * the other cpus in this package
406 cpu_data(i).booted_cores++;
407 } else if (i != cpu && !c->booted_cores)
408 c->booted_cores = cpu_data(i).booted_cores;
413 /* maps the cpu to the sched domain representing multi-core */
414 const struct cpumask *cpu_coregroup_mask(int cpu)
416 return cpu_llc_shared_mask(cpu);
419 static void impress_friends(void)
422 unsigned long bogosum = 0;
424 * Allow the user to impress friends.
426 pr_debug("Before bogomips.\n");
427 for_each_possible_cpu(cpu)
428 if (cpumask_test_cpu(cpu, cpu_callout_mask))
429 bogosum += cpu_data(cpu).loops_per_jiffy;
431 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
434 (bogosum/(5000/HZ))%100);
436 pr_debug("Before bogocount - setting activated=1.\n");
439 void __inquire_remote_apic(int apicid)
441 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
442 const char * const names[] = { "ID", "VERSION", "SPIV" };
446 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
448 for (i = 0; i < ARRAY_SIZE(regs); i++) {
449 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
454 status = safe_apic_wait_icr_idle();
457 "a previous APIC delivery may have failed\n");
459 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
464 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
465 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
468 case APIC_ICR_RR_VALID:
469 status = apic_read(APIC_RRR);
470 printk(KERN_CONT "%08x\n", status);
473 printk(KERN_CONT "failed\n");
479 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
480 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
481 * won't ... remember to clear down the APIC, etc later.
484 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
486 unsigned long send_status, accept_status = 0;
490 /* Boot on the stack */
491 /* Kick the second */
492 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
494 pr_debug("Waiting for send to finish...\n");
495 send_status = safe_apic_wait_icr_idle();
498 * Give the other CPU some time to accept the IPI.
501 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
502 maxlvt = lapic_get_maxlvt();
503 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
504 apic_write(APIC_ESR, 0);
505 accept_status = (apic_read(APIC_ESR) & 0xEF);
507 pr_debug("NMI sent.\n");
510 printk(KERN_ERR "APIC never delivered???\n");
512 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
514 return (send_status | accept_status);
518 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
520 unsigned long send_status, accept_status = 0;
521 int maxlvt, num_starts, j;
523 maxlvt = lapic_get_maxlvt();
526 * Be paranoid about clearing APIC errors.
528 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
529 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
530 apic_write(APIC_ESR, 0);
534 pr_debug("Asserting INIT.\n");
537 * Turn INIT on target chip
542 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
545 pr_debug("Waiting for send to finish...\n");
546 send_status = safe_apic_wait_icr_idle();
550 pr_debug("Deasserting INIT.\n");
554 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
556 pr_debug("Waiting for send to finish...\n");
557 send_status = safe_apic_wait_icr_idle();
560 atomic_set(&init_deasserted, 1);
563 * Should we send STARTUP IPIs ?
565 * Determine this based on the APIC version.
566 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
568 if (APIC_INTEGRATED(apic_version[phys_apicid]))
574 * Paravirt / VMI wants a startup IPI hook here to set up the
575 * target processor state.
577 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
581 * Run STARTUP IPI loop.
583 pr_debug("#startup loops: %d.\n", num_starts);
585 for (j = 1; j <= num_starts; j++) {
586 pr_debug("Sending STARTUP #%d.\n", j);
587 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
588 apic_write(APIC_ESR, 0);
590 pr_debug("After apic_write.\n");
597 /* Boot on the stack */
598 /* Kick the second */
599 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
603 * Give the other CPU some time to accept the IPI.
607 pr_debug("Startup point 1.\n");
609 pr_debug("Waiting for send to finish...\n");
610 send_status = safe_apic_wait_icr_idle();
613 * Give the other CPU some time to accept the IPI.
616 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
617 apic_write(APIC_ESR, 0);
618 accept_status = (apic_read(APIC_ESR) & 0xEF);
619 if (send_status || accept_status)
622 pr_debug("After Startup.\n");
625 printk(KERN_ERR "APIC never delivered???\n");
627 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
629 return (send_status | accept_status);
632 /* reduce the number of lines printed when booting a large cpu count system */
633 static void __cpuinit announce_cpu(int cpu, int apicid)
635 static int current_node = -1;
636 int node = early_cpu_to_node(cpu);
638 if (system_state == SYSTEM_BOOTING) {
639 if (node != current_node) {
640 if (current_node > (-1))
643 pr_info("Booting Node %3d, Processors ", node);
645 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
648 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
653 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
654 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
655 * Returns zero if CPU booted OK, else error code from
656 * ->wakeup_secondary_cpu.
658 static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
660 volatile u32 *trampoline_status =
661 (volatile u32 *) __va(real_mode_header->trampoline_status);
662 /* start_ip had better be page-aligned! */
663 unsigned long start_ip = real_mode_header->trampoline_start;
665 unsigned long boot_error = 0;
668 alternatives_smp_switch(1);
670 idle->thread.sp = (unsigned long) (((struct pt_regs *)
671 (THREAD_SIZE + task_stack_page(idle))) - 1);
672 per_cpu(current_task, cpu) = idle;
675 /* Stack for startup_32 can be just as for start_secondary onwards */
678 clear_tsk_thread_flag(idle, TIF_FORK);
679 initial_gs = per_cpu_offset(cpu);
680 per_cpu(kernel_stack, cpu) =
681 (unsigned long)task_stack_page(idle) -
682 KERNEL_STACK_OFFSET + THREAD_SIZE;
684 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
685 initial_code = (unsigned long)start_secondary;
686 stack_start = idle->thread.sp;
688 /* So we see what's up */
689 announce_cpu(cpu, apicid);
692 * This grunge runs the startup process for
693 * the targeted processor.
696 atomic_set(&init_deasserted, 0);
698 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
700 pr_debug("Setting warm reset code and vector.\n");
702 smpboot_setup_warm_reset_vector(start_ip);
704 * Be paranoid about clearing APIC errors.
706 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
707 apic_write(APIC_ESR, 0);
713 * Kick the secondary CPU. Use the method in the APIC driver
714 * if it's defined - or use an INIT boot APIC message otherwise:
716 if (apic->wakeup_secondary_cpu)
717 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
719 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
723 * allow APs to start initializing.
725 pr_debug("Before Callout %d.\n", cpu);
726 cpumask_set_cpu(cpu, cpu_callout_mask);
727 pr_debug("After Callout %d.\n", cpu);
730 * Wait 5s total for a response
732 for (timeout = 0; timeout < 50000; timeout++) {
733 if (cpumask_test_cpu(cpu, cpu_callin_mask))
734 break; /* It has booted */
737 * Allow other tasks to run while we wait for the
738 * AP to come online. This also gives a chance
739 * for the MTRR work(triggered by the AP coming online)
740 * to be completed in the stop machine context.
745 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
746 print_cpu_msr(&cpu_data(cpu));
747 pr_debug("CPU%d: has booted.\n", cpu);
750 if (*trampoline_status == 0xA5A5A5A5)
751 /* trampoline started but...? */
752 pr_err("CPU%d: Stuck ??\n", cpu);
754 /* trampoline code not run */
755 pr_err("CPU%d: Not responding.\n", cpu);
756 if (apic->inquire_remote_apic)
757 apic->inquire_remote_apic(apicid);
762 /* Try to put things back the way they were before ... */
763 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
765 /* was set by do_boot_cpu() */
766 cpumask_clear_cpu(cpu, cpu_callout_mask);
768 /* was set by cpu_init() */
769 cpumask_clear_cpu(cpu, cpu_initialized_mask);
771 set_cpu_present(cpu, false);
772 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
775 /* mark "stuck" area as not stuck */
776 *trampoline_status = 0;
778 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
780 * Cleanup possible dangling ends...
782 smpboot_restore_warm_reset_vector();
787 int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle)
789 int apicid = apic->cpu_present_to_apicid(cpu);
793 WARN_ON(irqs_disabled());
795 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
797 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
798 !physid_isset(apicid, phys_cpu_present_map) ||
799 !apic->apic_id_valid(apicid)) {
800 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
805 * Already booted CPU?
807 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
808 pr_debug("do_boot_cpu %d Already started\n", cpu);
813 * Save current MTRR state in case it was changed since early boot
814 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
818 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
820 err = do_boot_cpu(apicid, cpu, tidle);
822 pr_debug("do_boot_cpu failed %d\n", err);
827 * Check TSC synchronization with the AP (keep irqs disabled
830 local_irq_save(flags);
831 check_tsc_sync_source(cpu);
832 local_irq_restore(flags);
834 while (!cpu_online(cpu)) {
836 touch_nmi_watchdog();
843 * arch_disable_smp_support() - disables SMP support for x86 at runtime
845 void arch_disable_smp_support(void)
847 disable_ioapic_support();
851 * Fall back to non SMP mode after errors.
853 * RED-PEN audit/test this more. I bet there is more state messed up here.
855 static __init void disable_smp(void)
857 init_cpu_present(cpumask_of(0));
858 init_cpu_possible(cpumask_of(0));
859 smpboot_clear_io_apic_irqs();
861 if (smp_found_config)
862 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
864 physid_set_mask_of_physid(0, &phys_cpu_present_map);
865 cpumask_set_cpu(0, cpu_sibling_mask(0));
866 cpumask_set_cpu(0, cpu_core_mask(0));
870 * Various sanity checks.
872 static int __init smp_sanity_check(unsigned max_cpus)
876 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
877 if (def_to_bigsmp && nr_cpu_ids > 8) {
882 "More than 8 CPUs detected - skipping them.\n"
883 "Use CONFIG_X86_BIGSMP.\n");
886 for_each_present_cpu(cpu) {
888 set_cpu_present(cpu, false);
893 for_each_possible_cpu(cpu) {
895 set_cpu_possible(cpu, false);
903 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
905 "weird, boot CPU (#%d) not listed by the BIOS.\n",
906 hard_smp_processor_id());
908 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
912 * If we couldn't find an SMP configuration at boot time,
913 * get out of here now!
915 if (!smp_found_config && !acpi_lapic) {
917 printk(KERN_NOTICE "SMP motherboard not detected.\n");
919 if (APIC_init_uniprocessor())
920 printk(KERN_NOTICE "Local APIC not detected."
921 " Using dummy APIC emulation.\n");
926 * Should not be necessary because the MP table should list the boot
927 * CPU too, but we do it for the sake of robustness anyway.
929 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
931 "weird, boot CPU (#%d) not listed by the BIOS.\n",
932 boot_cpu_physical_apicid);
933 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
938 * If we couldn't find a local APIC, then get out of here now!
940 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
943 pr_err("BIOS bug, local APIC #%d not detected!...\n",
944 boot_cpu_physical_apicid);
945 pr_err("... forcing use of dummy APIC emulation."
946 "(tell your hw vendor)\n");
948 smpboot_clear_io_apic();
949 disable_ioapic_support();
956 * If SMP should be disabled, then really disable it!
959 printk(KERN_INFO "SMP mode deactivated.\n");
960 smpboot_clear_io_apic();
964 bsp_end_local_APIC_setup();
971 static void __init smp_cpu_index_default(void)
974 struct cpuinfo_x86 *c;
976 for_each_possible_cpu(i) {
978 /* mark all to hotplug */
979 c->cpu_index = nr_cpu_ids;
984 * Prepare for SMP bootup. The MP table or ACPI has been read
985 * earlier. Just do some sanity checking here and enable APIC mode.
987 void __init native_smp_prepare_cpus(unsigned int max_cpus)
992 smp_cpu_index_default();
995 * Setup boot CPU information
997 smp_store_cpu_info(0); /* Final full version of the data */
998 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1001 current_thread_info()->cpu = 0; /* needed? */
1002 for_each_possible_cpu(i) {
1003 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1004 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1005 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1007 set_cpu_sibling_map(0);
1010 if (smp_sanity_check(max_cpus) < 0) {
1011 printk(KERN_INFO "SMP disabled\n");
1016 default_setup_apic_routing();
1019 if (read_apic_id() != boot_cpu_physical_apicid) {
1020 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1021 read_apic_id(), boot_cpu_physical_apicid);
1022 /* Or can we switch back to PIC here? */
1029 * Switch from PIC to APIC mode.
1034 * Enable IO APIC before setting up error vector
1036 if (!skip_ioapic_setup && nr_ioapics)
1039 bsp_end_local_APIC_setup();
1041 if (apic->setup_portio_remap)
1042 apic->setup_portio_remap();
1044 smpboot_setup_io_apic();
1046 * Set up local APIC timer on boot CPU.
1049 printk(KERN_INFO "CPU%d: ", 0);
1050 print_cpu_info(&cpu_data(0));
1051 x86_init.timers.setup_percpu_clockev();
1056 set_mtrr_aps_delayed_init();
1061 void arch_disable_nonboot_cpus_begin(void)
1064 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1065 * In the suspend path, we will be back in the SMP mode shortly anyways.
1067 skip_smp_alternatives = true;
1070 void arch_disable_nonboot_cpus_end(void)
1072 skip_smp_alternatives = false;
1075 void arch_enable_nonboot_cpus_begin(void)
1077 set_mtrr_aps_delayed_init();
1080 void arch_enable_nonboot_cpus_end(void)
1086 * Early setup to make printk work.
1088 void __init native_smp_prepare_boot_cpu(void)
1090 int me = smp_processor_id();
1091 switch_to_new_gdt(me);
1092 /* already set me in cpu_online_mask in boot_cpu_init() */
1093 cpumask_set_cpu(me, cpu_callout_mask);
1094 per_cpu(cpu_state, me) = CPU_ONLINE;
1097 void __init native_smp_cpus_done(unsigned int max_cpus)
1099 pr_debug("Boot done.\n");
1103 #ifdef CONFIG_X86_IO_APIC
1104 setup_ioapic_dest();
1109 static int __initdata setup_possible_cpus = -1;
1110 static int __init _setup_possible_cpus(char *str)
1112 get_option(&str, &setup_possible_cpus);
1115 early_param("possible_cpus", _setup_possible_cpus);
1119 * cpu_possible_mask should be static, it cannot change as cpu's
1120 * are onlined, or offlined. The reason is per-cpu data-structures
1121 * are allocated by some modules at init time, and dont expect to
1122 * do this dynamically on cpu arrival/departure.
1123 * cpu_present_mask on the other hand can change dynamically.
1124 * In case when cpu_hotplug is not compiled, then we resort to current
1125 * behaviour, which is cpu_possible == cpu_present.
1128 * Three ways to find out the number of additional hotplug CPUs:
1129 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1130 * - The user can overwrite it with possible_cpus=NUM
1131 * - Otherwise don't reserve additional CPUs.
1132 * We do this because additional CPUs waste a lot of memory.
1135 __init void prefill_possible_map(void)
1139 /* no processor from mptable or madt */
1140 if (!num_processors)
1143 i = setup_max_cpus ?: 1;
1144 if (setup_possible_cpus == -1) {
1145 possible = num_processors;
1146 #ifdef CONFIG_HOTPLUG_CPU
1148 possible += disabled_cpus;
1154 possible = setup_possible_cpus;
1156 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1158 /* nr_cpu_ids could be reduced via nr_cpus= */
1159 if (possible > nr_cpu_ids) {
1161 "%d Processors exceeds NR_CPUS limit of %d\n",
1162 possible, nr_cpu_ids);
1163 possible = nr_cpu_ids;
1166 #ifdef CONFIG_HOTPLUG_CPU
1167 if (!setup_max_cpus)
1171 "%d Processors exceeds max_cpus limit of %u\n",
1172 possible, setup_max_cpus);
1176 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1177 possible, max_t(int, possible - num_processors, 0));
1179 for (i = 0; i < possible; i++)
1180 set_cpu_possible(i, true);
1181 for (; i < NR_CPUS; i++)
1182 set_cpu_possible(i, false);
1184 nr_cpu_ids = possible;
1187 #ifdef CONFIG_HOTPLUG_CPU
1189 static void remove_siblinginfo(int cpu)
1192 struct cpuinfo_x86 *c = &cpu_data(cpu);
1194 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1195 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1197 * last thread sibling in this cpu core going down
1199 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1200 cpu_data(sibling).booted_cores--;
1203 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1204 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1205 cpumask_clear(cpu_sibling_mask(cpu));
1206 cpumask_clear(cpu_core_mask(cpu));
1207 c->phys_proc_id = 0;
1209 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1212 static void __ref remove_cpu_from_maps(int cpu)
1214 set_cpu_online(cpu, false);
1215 cpumask_clear_cpu(cpu, cpu_callout_mask);
1216 cpumask_clear_cpu(cpu, cpu_callin_mask);
1217 /* was set by cpu_init() */
1218 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1219 numa_remove_cpu(cpu);
1222 void cpu_disable_common(void)
1224 int cpu = smp_processor_id();
1226 remove_siblinginfo(cpu);
1228 /* It's now safe to remove this processor from the online map */
1230 remove_cpu_from_maps(cpu);
1231 unlock_vector_lock();
1235 int native_cpu_disable(void)
1237 int cpu = smp_processor_id();
1240 * Perhaps use cpufreq to drop frequency, but that could go
1241 * into generic code.
1243 * We won't take down the boot processor on i386 due to some
1244 * interrupts only being able to be serviced by the BSP.
1245 * Especially so if we're not using an IOAPIC -zwane
1252 cpu_disable_common();
1256 void native_cpu_die(unsigned int cpu)
1258 /* We don't do anything here: idle task is faking death itself. */
1261 for (i = 0; i < 10; i++) {
1262 /* They ack this in play_dead by setting CPU_DEAD */
1263 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1264 if (system_state == SYSTEM_RUNNING)
1265 pr_info("CPU %u is now offline\n", cpu);
1267 if (1 == num_online_cpus())
1268 alternatives_smp_switch(0);
1273 pr_err("CPU %u didn't die...\n", cpu);
1276 void play_dead_common(void)
1279 reset_lazy_tlbstate();
1280 amd_e400_remove_cpu(raw_smp_processor_id());
1284 __this_cpu_write(cpu_state, CPU_DEAD);
1287 * With physical CPU hotplug, we should halt the cpu
1289 local_irq_disable();
1293 * We need to flush the caches before going to sleep, lest we have
1294 * dirty data in our caches when we come back up.
1296 static inline void mwait_play_dead(void)
1298 unsigned int eax, ebx, ecx, edx;
1299 unsigned int highest_cstate = 0;
1300 unsigned int highest_subcstate = 0;
1303 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1305 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1307 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1309 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1312 eax = CPUID_MWAIT_LEAF;
1314 native_cpuid(&eax, &ebx, &ecx, &edx);
1317 * eax will be 0 if EDX enumeration is not valid.
1318 * Initialized below to cstate, sub_cstate value when EDX is valid.
1320 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1323 edx >>= MWAIT_SUBSTATE_SIZE;
1324 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1325 if (edx & MWAIT_SUBSTATE_MASK) {
1327 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1330 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1331 (highest_subcstate - 1);
1335 * This should be a memory location in a cache line which is
1336 * unlikely to be touched by other processors. The actual
1337 * content is immaterial as it is not actually modified in any way.
1339 mwait_ptr = ¤t_thread_info()->flags;
1345 * The CLFLUSH is a workaround for erratum AAI65 for
1346 * the Xeon 7400 series. It's not clear it is actually
1347 * needed, but it should be harmless in either case.
1348 * The WBINVD is insufficient due to the spurious-wakeup
1349 * case where we return around the loop.
1352 __monitor(mwait_ptr, 0, 0);
1358 static inline void hlt_play_dead(void)
1360 if (__this_cpu_read(cpu_info.x86) >= 4)
1368 void native_play_dead(void)
1371 tboot_shutdown(TB_SHUTDOWN_WFS);
1373 mwait_play_dead(); /* Only returns on failure */
1374 if (cpuidle_play_dead())
1378 #else /* ... !CONFIG_HOTPLUG_CPU */
1379 int native_cpu_disable(void)
1384 void native_cpu_die(unsigned int cpu)
1386 /* We said "no" in __cpu_disable */
1390 void native_play_dead(void)