2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/smpboot_hooks.h>
77 #include <asm/i8259.h>
78 #include <asm/realmode.h>
81 /* State of each CPU */
82 DEFINE_PER_CPU(int, cpu_state) = { 0 };
84 #ifdef CONFIG_HOTPLUG_CPU
86 * We need this for trampoline_base protection from concurrent accesses when
87 * off- and onlining cores wildly.
89 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
91 void cpu_hotplug_driver_lock(void)
93 mutex_lock(&x86_cpu_hotplug_driver_mutex);
96 void cpu_hotplug_driver_unlock(void)
98 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
101 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
102 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
105 /* Number of siblings per CPU package */
106 int smp_num_siblings = 1;
107 EXPORT_SYMBOL(smp_num_siblings);
109 /* Last level cache ID of each logical CPU */
110 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
112 /* representing HT siblings of each logical CPU */
113 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
114 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
116 /* representing HT and core siblings of each logical CPU */
117 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
118 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
120 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
122 /* Per CPU bogomips and other parameters */
123 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
124 EXPORT_PER_CPU_SYMBOL(cpu_info);
126 atomic_t init_deasserted;
129 * Report back to the Boot Processor during boot time or to the caller processor
132 static void smp_callin(void)
135 unsigned long timeout;
138 * If waken up by an INIT in an 82489DX configuration
139 * we may get here before an INIT-deassert IPI reaches
140 * our local APIC. We have to wait for the IPI or we'll
141 * lock up on an APIC access.
143 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
145 cpuid = smp_processor_id();
146 if (apic->wait_for_init_deassert && cpuid != 0)
147 apic->wait_for_init_deassert(&init_deasserted);
150 * (This works even if the APIC is not enabled.)
152 phys_id = read_apic_id();
153 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
154 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
157 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
160 * STARTUP IPIs are fragile beasts as they might sometimes
161 * trigger some glue motherboard logic. Complete APIC bus
162 * silence for 1 second, this overestimates the time the
163 * boot CPU is spending to send the up to 2 STARTUP IPIs
164 * by a factor of two. This should be enough.
168 * Waiting 2s total for startup (udelay is not yet working)
170 timeout = jiffies + 2*HZ;
171 while (time_before(jiffies, timeout)) {
173 * Has the boot CPU finished it's STARTUP sequence?
175 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
180 if (!time_before(jiffies, timeout)) {
181 panic("%s: CPU%d started up but did not get a callout!\n",
186 * the boot CPU has finished the init stage and is spinning
187 * on callin_map until we finish. We are free to set up this
188 * CPU, first the APIC. (this is probably redundant on most
192 pr_debug("CALLIN, before setup_local_APIC()\n");
193 if (apic->smp_callin_clear_local_apic)
194 apic->smp_callin_clear_local_apic();
196 end_local_APIC_setup();
199 * Need to setup vector mappings before we enable interrupts.
201 setup_vector_irq(smp_processor_id());
204 * Save our processor parameters. Note: this information
205 * is needed for clock calibration.
207 smp_store_cpu_info(cpuid);
211 * Update loops_per_jiffy in cpu_data. Previous call to
212 * smp_store_cpu_info() stored a value that is close but not as
213 * accurate as the value just calculated.
216 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
217 pr_debug("Stack at about %p\n", &cpuid);
220 * This must be done before setting cpu_online_mask
221 * or calling notify_cpu_starting.
223 set_cpu_sibling_map(raw_smp_processor_id());
226 notify_cpu_starting(cpuid);
229 * Allow the master to continue.
231 cpumask_set_cpu(cpuid, cpu_callin_mask);
234 static int cpu0_logical_apicid;
235 static int enable_start_cpu0;
237 * Activate a secondary processor.
239 static void notrace start_secondary(void *unused)
242 * Don't put *anything* before cpu_init(), SMP booting is too
243 * fragile that we want to limit the things done here to the
244 * most necessary things.
247 x86_cpuinit.early_percpu_clock_init();
251 enable_start_cpu0 = 0;
254 /* switch away from the initial page table */
255 load_cr3(swapper_pg_dir);
259 /* otherwise gcc will move up smp_processor_id before the cpu_init */
262 * Check TSC synchronization with the BP:
264 check_tsc_sync_target();
267 * We need to hold vector_lock so there the set of online cpus
268 * does not change while we are assigning vectors to cpus. Holding
269 * this lock ensures we don't half assign or remove an irq from a cpu.
272 set_cpu_online(smp_processor_id(), true);
273 unlock_vector_lock();
274 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
275 x86_platform.nmi_init();
277 /* enable local interrupts */
280 /* to prevent fake stack check failure in clock setup */
281 boot_init_stack_canary();
283 x86_cpuinit.setup_percpu_clockev();
286 cpu_startup_entry(CPUHP_ONLINE);
289 void __init smp_store_boot_cpu_info(void)
291 int id = 0; /* CPU 0 */
292 struct cpuinfo_x86 *c = &cpu_data(id);
299 * The bootstrap kernel entry code has set these up. Save them for
302 void smp_store_cpu_info(int id)
304 struct cpuinfo_x86 *c = &cpu_data(id);
309 * During boot time, CPU0 has this setup already. Save the info when
310 * bringing up AP or offlined CPU0.
312 identify_secondary_cpu(c);
316 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
318 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
320 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
321 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
322 "[node: %d != %d]. Ignoring dependency.\n",
323 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
326 #define link_mask(_m, c1, c2) \
328 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
329 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
332 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
334 if (cpu_has_topoext) {
335 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
337 if (c->phys_proc_id == o->phys_proc_id &&
338 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
339 c->compute_unit_id == o->compute_unit_id)
340 return topology_sane(c, o, "smt");
342 } else if (c->phys_proc_id == o->phys_proc_id &&
343 c->cpu_core_id == o->cpu_core_id) {
344 return topology_sane(c, o, "smt");
350 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
352 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
354 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
355 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
356 return topology_sane(c, o, "llc");
361 static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
363 if (c->phys_proc_id == o->phys_proc_id) {
364 if (cpu_has(c, X86_FEATURE_AMD_DCM))
367 return topology_sane(c, o, "mc");
372 void set_cpu_sibling_map(int cpu)
374 bool has_smt = smp_num_siblings > 1;
375 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
376 struct cpuinfo_x86 *c = &cpu_data(cpu);
377 struct cpuinfo_x86 *o;
380 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
383 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
384 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
385 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
390 for_each_cpu(i, cpu_sibling_setup_mask) {
393 if ((i == cpu) || (has_smt && match_smt(c, o)))
394 link_mask(sibling, cpu, i);
396 if ((i == cpu) || (has_mp && match_llc(c, o)))
397 link_mask(llc_shared, cpu, i);
402 * This needs a separate iteration over the cpus because we rely on all
403 * cpu_sibling_mask links to be set-up.
405 for_each_cpu(i, cpu_sibling_setup_mask) {
408 if ((i == cpu) || (has_mp && match_mc(c, o))) {
409 link_mask(core, cpu, i);
412 * Does this new cpu bringup a new core?
414 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
416 * for each core in package, increment
417 * the booted_cores for this new cpu
419 if (cpumask_first(cpu_sibling_mask(i)) == i)
422 * increment the core count for all
423 * the other cpus in this package
426 cpu_data(i).booted_cores++;
427 } else if (i != cpu && !c->booted_cores)
428 c->booted_cores = cpu_data(i).booted_cores;
433 /* maps the cpu to the sched domain representing multi-core */
434 const struct cpumask *cpu_coregroup_mask(int cpu)
436 return cpu_llc_shared_mask(cpu);
439 static void impress_friends(void)
442 unsigned long bogosum = 0;
444 * Allow the user to impress friends.
446 pr_debug("Before bogomips\n");
447 for_each_possible_cpu(cpu)
448 if (cpumask_test_cpu(cpu, cpu_callout_mask))
449 bogosum += cpu_data(cpu).loops_per_jiffy;
450 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
453 (bogosum/(5000/HZ))%100);
455 pr_debug("Before bogocount - setting activated=1\n");
458 void __inquire_remote_apic(int apicid)
460 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
461 const char * const names[] = { "ID", "VERSION", "SPIV" };
465 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
467 for (i = 0; i < ARRAY_SIZE(regs); i++) {
468 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
473 status = safe_apic_wait_icr_idle();
475 pr_cont("a previous APIC delivery may have failed\n");
477 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
482 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
483 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
486 case APIC_ICR_RR_VALID:
487 status = apic_read(APIC_RRR);
488 pr_cont("%08x\n", status);
497 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
498 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
499 * won't ... remember to clear down the APIC, etc later.
502 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
504 unsigned long send_status, accept_status = 0;
508 /* Boot on the stack */
509 /* Kick the second */
510 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
512 pr_debug("Waiting for send to finish...\n");
513 send_status = safe_apic_wait_icr_idle();
516 * Give the other CPU some time to accept the IPI.
519 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
520 maxlvt = lapic_get_maxlvt();
521 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
522 apic_write(APIC_ESR, 0);
523 accept_status = (apic_read(APIC_ESR) & 0xEF);
525 pr_debug("NMI sent\n");
528 pr_err("APIC never delivered???\n");
530 pr_err("APIC delivery error (%lx)\n", accept_status);
532 return (send_status | accept_status);
536 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
538 unsigned long send_status, accept_status = 0;
539 int maxlvt, num_starts, j;
541 maxlvt = lapic_get_maxlvt();
544 * Be paranoid about clearing APIC errors.
546 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
547 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
548 apic_write(APIC_ESR, 0);
552 pr_debug("Asserting INIT\n");
555 * Turn INIT on target chip
560 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
563 pr_debug("Waiting for send to finish...\n");
564 send_status = safe_apic_wait_icr_idle();
568 pr_debug("Deasserting INIT\n");
572 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
574 pr_debug("Waiting for send to finish...\n");
575 send_status = safe_apic_wait_icr_idle();
578 atomic_set(&init_deasserted, 1);
581 * Should we send STARTUP IPIs ?
583 * Determine this based on the APIC version.
584 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
586 if (APIC_INTEGRATED(apic_version[phys_apicid]))
592 * Paravirt / VMI wants a startup IPI hook here to set up the
593 * target processor state.
595 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
599 * Run STARTUP IPI loop.
601 pr_debug("#startup loops: %d\n", num_starts);
603 for (j = 1; j <= num_starts; j++) {
604 pr_debug("Sending STARTUP #%d\n", j);
605 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
606 apic_write(APIC_ESR, 0);
608 pr_debug("After apic_write\n");
615 /* Boot on the stack */
616 /* Kick the second */
617 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
621 * Give the other CPU some time to accept the IPI.
625 pr_debug("Startup point 1\n");
627 pr_debug("Waiting for send to finish...\n");
628 send_status = safe_apic_wait_icr_idle();
631 * Give the other CPU some time to accept the IPI.
634 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
635 apic_write(APIC_ESR, 0);
636 accept_status = (apic_read(APIC_ESR) & 0xEF);
637 if (send_status || accept_status)
640 pr_debug("After Startup\n");
643 pr_err("APIC never delivered???\n");
645 pr_err("APIC delivery error (%lx)\n", accept_status);
647 return (send_status | accept_status);
650 void smp_announce(void)
652 int num_nodes = num_online_nodes();
654 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
655 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
658 /* reduce the number of lines printed when booting a large cpu count system */
659 static void announce_cpu(int cpu, int apicid)
661 static int current_node = -1;
662 int node = early_cpu_to_node(cpu);
663 static int width, node_width;
666 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
669 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
672 printk(KERN_INFO "x86: Booting SMP configuration:\n");
674 if (system_state == SYSTEM_BOOTING) {
675 if (node != current_node) {
676 if (current_node > (-1))
680 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
681 node_width - num_digits(node), " ", node);
684 /* Add padding for the BSP */
686 pr_cont("%*s", width + 1, " ");
688 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
691 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
695 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
699 cpu = smp_processor_id();
700 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
707 * Wake up AP by INIT, INIT, STARTUP sequence.
709 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
710 * boot-strap code which is not a desired behavior for waking up BSP. To
711 * void the boot-strap code, wake up CPU0 by NMI instead.
713 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
714 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
715 * We'll change this code in the future to wake up hard offlined CPU0 if
716 * real platform and request are available.
719 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
720 int *cpu0_nmi_registered)
726 * Wake up AP by INIT, INIT, STARTUP sequence.
729 return wakeup_secondary_cpu_via_init(apicid, start_ip);
732 * Wake up BSP by nmi.
734 * Register a NMI handler to help wake up CPU0.
736 boot_error = register_nmi_handler(NMI_LOCAL,
737 wakeup_cpu0_nmi, 0, "wake_cpu0");
740 enable_start_cpu0 = 1;
741 *cpu0_nmi_registered = 1;
742 if (apic->dest_logical == APIC_DEST_LOGICAL)
743 id = cpu0_logical_apicid;
746 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
753 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
754 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
755 * Returns zero if CPU booted OK, else error code from
756 * ->wakeup_secondary_cpu.
758 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
760 volatile u32 *trampoline_status =
761 (volatile u32 *) __va(real_mode_header->trampoline_status);
762 /* start_ip had better be page-aligned! */
763 unsigned long start_ip = real_mode_header->trampoline_start;
765 unsigned long boot_error = 0;
767 int cpu0_nmi_registered = 0;
769 /* Just in case we booted with a single CPU. */
770 alternatives_enable_smp();
772 idle->thread.sp = (unsigned long) (((struct pt_regs *)
773 (THREAD_SIZE + task_stack_page(idle))) - 1);
774 per_cpu(current_task, cpu) = idle;
777 /* Stack for startup_32 can be just as for start_secondary onwards */
780 clear_tsk_thread_flag(idle, TIF_FORK);
781 initial_gs = per_cpu_offset(cpu);
782 per_cpu(kernel_stack, cpu) =
783 (unsigned long)task_stack_page(idle) -
784 KERNEL_STACK_OFFSET + THREAD_SIZE;
786 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
787 initial_code = (unsigned long)start_secondary;
788 stack_start = idle->thread.sp;
790 /* So we see what's up */
791 announce_cpu(cpu, apicid);
794 * This grunge runs the startup process for
795 * the targeted processor.
798 atomic_set(&init_deasserted, 0);
800 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
802 pr_debug("Setting warm reset code and vector.\n");
804 smpboot_setup_warm_reset_vector(start_ip);
806 * Be paranoid about clearing APIC errors.
808 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
809 apic_write(APIC_ESR, 0);
815 * Wake up a CPU in difference cases:
816 * - Use the method in the APIC driver if it's defined
818 * - Use an INIT boot APIC message for APs or NMI for BSP.
820 if (apic->wakeup_secondary_cpu)
821 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
823 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
824 &cpu0_nmi_registered);
828 * allow APs to start initializing.
830 pr_debug("Before Callout %d\n", cpu);
831 cpumask_set_cpu(cpu, cpu_callout_mask);
832 pr_debug("After Callout %d\n", cpu);
835 * Wait 5s total for a response
837 for (timeout = 0; timeout < 50000; timeout++) {
838 if (cpumask_test_cpu(cpu, cpu_callin_mask))
839 break; /* It has booted */
842 * Allow other tasks to run while we wait for the
843 * AP to come online. This also gives a chance
844 * for the MTRR work(triggered by the AP coming online)
845 * to be completed in the stop machine context.
850 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
851 print_cpu_msr(&cpu_data(cpu));
852 pr_debug("CPU%d: has booted.\n", cpu);
855 if (*trampoline_status == 0xA5A5A5A5)
856 /* trampoline started but...? */
857 pr_err("CPU%d: Stuck ??\n", cpu);
859 /* trampoline code not run */
860 pr_err("CPU%d: Not responding\n", cpu);
861 if (apic->inquire_remote_apic)
862 apic->inquire_remote_apic(apicid);
867 /* Try to put things back the way they were before ... */
868 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
870 /* was set by do_boot_cpu() */
871 cpumask_clear_cpu(cpu, cpu_callout_mask);
873 /* was set by cpu_init() */
874 cpumask_clear_cpu(cpu, cpu_initialized_mask);
876 set_cpu_present(cpu, false);
877 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
880 /* mark "stuck" area as not stuck */
881 *trampoline_status = 0;
883 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
885 * Cleanup possible dangling ends...
887 smpboot_restore_warm_reset_vector();
890 * Clean up the nmi handler. Do this after the callin and callout sync
891 * to avoid impact of possible long unregister time.
893 if (cpu0_nmi_registered)
894 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
899 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
901 int apicid = apic->cpu_present_to_apicid(cpu);
905 WARN_ON(irqs_disabled());
907 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
909 if (apicid == BAD_APICID ||
910 !physid_isset(apicid, phys_cpu_present_map) ||
911 !apic->apic_id_valid(apicid)) {
912 pr_err("%s: bad cpu %d\n", __func__, cpu);
917 * Already booted CPU?
919 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
920 pr_debug("do_boot_cpu %d Already started\n", cpu);
925 * Save current MTRR state in case it was changed since early boot
926 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
930 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
932 /* the FPU context is blank, nobody can own it */
933 __cpu_disable_lazy_restore(cpu);
935 err = do_boot_cpu(apicid, cpu, tidle);
937 pr_debug("do_boot_cpu failed %d\n", err);
942 * Check TSC synchronization with the AP (keep irqs disabled
945 local_irq_save(flags);
946 check_tsc_sync_source(cpu);
947 local_irq_restore(flags);
949 while (!cpu_online(cpu)) {
951 touch_nmi_watchdog();
958 * arch_disable_smp_support() - disables SMP support for x86 at runtime
960 void arch_disable_smp_support(void)
962 disable_ioapic_support();
966 * Fall back to non SMP mode after errors.
968 * RED-PEN audit/test this more. I bet there is more state messed up here.
970 static __init void disable_smp(void)
972 init_cpu_present(cpumask_of(0));
973 init_cpu_possible(cpumask_of(0));
974 smpboot_clear_io_apic_irqs();
976 if (smp_found_config)
977 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
979 physid_set_mask_of_physid(0, &phys_cpu_present_map);
980 cpumask_set_cpu(0, cpu_sibling_mask(0));
981 cpumask_set_cpu(0, cpu_core_mask(0));
985 * Various sanity checks.
987 static int __init smp_sanity_check(unsigned max_cpus)
991 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
992 if (def_to_bigsmp && nr_cpu_ids > 8) {
996 pr_warn("More than 8 CPUs detected - skipping them\n"
997 "Use CONFIG_X86_BIGSMP\n");
1000 for_each_present_cpu(cpu) {
1002 set_cpu_present(cpu, false);
1007 for_each_possible_cpu(cpu) {
1009 set_cpu_possible(cpu, false);
1017 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1018 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1019 hard_smp_processor_id());
1021 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1025 * If we couldn't find an SMP configuration at boot time,
1026 * get out of here now!
1028 if (!smp_found_config && !acpi_lapic) {
1030 pr_notice("SMP motherboard not detected\n");
1032 if (APIC_init_uniprocessor())
1033 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1038 * Should not be necessary because the MP table should list the boot
1039 * CPU too, but we do it for the sake of robustness anyway.
1041 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1042 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1043 boot_cpu_physical_apicid);
1044 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1049 * If we couldn't find a local APIC, then get out of here now!
1051 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1053 if (!disable_apic) {
1054 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1055 boot_cpu_physical_apicid);
1056 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1058 smpboot_clear_io_apic();
1059 disable_ioapic_support();
1063 verify_local_APIC();
1066 * If SMP should be disabled, then really disable it!
1069 pr_info("SMP mode deactivated\n");
1070 smpboot_clear_io_apic();
1074 bsp_end_local_APIC_setup();
1081 static void __init smp_cpu_index_default(void)
1084 struct cpuinfo_x86 *c;
1086 for_each_possible_cpu(i) {
1088 /* mark all to hotplug */
1089 c->cpu_index = nr_cpu_ids;
1094 * Prepare for SMP bootup. The MP table or ACPI has been read
1095 * earlier. Just do some sanity checking here and enable APIC mode.
1097 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1102 smp_cpu_index_default();
1105 * Setup boot CPU information
1107 smp_store_boot_cpu_info(); /* Final full version of the data */
1108 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1111 current_thread_info()->cpu = 0; /* needed? */
1112 for_each_possible_cpu(i) {
1113 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1114 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1115 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1117 set_cpu_sibling_map(0);
1120 if (smp_sanity_check(max_cpus) < 0) {
1121 pr_info("SMP disabled\n");
1126 default_setup_apic_routing();
1129 if (read_apic_id() != boot_cpu_physical_apicid) {
1130 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1131 read_apic_id(), boot_cpu_physical_apicid);
1132 /* Or can we switch back to PIC here? */
1139 * Switch from PIC to APIC mode.
1144 cpu0_logical_apicid = apic_read(APIC_LDR);
1146 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1149 * Enable IO APIC before setting up error vector
1151 if (!skip_ioapic_setup && nr_ioapics)
1154 bsp_end_local_APIC_setup();
1156 if (apic->setup_portio_remap)
1157 apic->setup_portio_remap();
1159 smpboot_setup_io_apic();
1161 * Set up local APIC timer on boot CPU.
1164 pr_info("CPU%d: ", 0);
1165 print_cpu_info(&cpu_data(0));
1166 x86_init.timers.setup_percpu_clockev();
1171 set_mtrr_aps_delayed_init();
1176 void arch_enable_nonboot_cpus_begin(void)
1178 set_mtrr_aps_delayed_init();
1181 void arch_enable_nonboot_cpus_end(void)
1187 * Early setup to make printk work.
1189 void __init native_smp_prepare_boot_cpu(void)
1191 int me = smp_processor_id();
1192 switch_to_new_gdt(me);
1193 /* already set me in cpu_online_mask in boot_cpu_init() */
1194 cpumask_set_cpu(me, cpu_callout_mask);
1195 per_cpu(cpu_state, me) = CPU_ONLINE;
1198 void __init native_smp_cpus_done(unsigned int max_cpus)
1200 pr_debug("Boot done\n");
1204 #ifdef CONFIG_X86_IO_APIC
1205 setup_ioapic_dest();
1210 static int __initdata setup_possible_cpus = -1;
1211 static int __init _setup_possible_cpus(char *str)
1213 get_option(&str, &setup_possible_cpus);
1216 early_param("possible_cpus", _setup_possible_cpus);
1220 * cpu_possible_mask should be static, it cannot change as cpu's
1221 * are onlined, or offlined. The reason is per-cpu data-structures
1222 * are allocated by some modules at init time, and dont expect to
1223 * do this dynamically on cpu arrival/departure.
1224 * cpu_present_mask on the other hand can change dynamically.
1225 * In case when cpu_hotplug is not compiled, then we resort to current
1226 * behaviour, which is cpu_possible == cpu_present.
1229 * Three ways to find out the number of additional hotplug CPUs:
1230 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1231 * - The user can overwrite it with possible_cpus=NUM
1232 * - Otherwise don't reserve additional CPUs.
1233 * We do this because additional CPUs waste a lot of memory.
1236 __init void prefill_possible_map(void)
1240 /* no processor from mptable or madt */
1241 if (!num_processors)
1244 i = setup_max_cpus ?: 1;
1245 if (setup_possible_cpus == -1) {
1246 possible = num_processors;
1247 #ifdef CONFIG_HOTPLUG_CPU
1249 possible += disabled_cpus;
1255 possible = setup_possible_cpus;
1257 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1259 /* nr_cpu_ids could be reduced via nr_cpus= */
1260 if (possible > nr_cpu_ids) {
1261 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1262 possible, nr_cpu_ids);
1263 possible = nr_cpu_ids;
1266 #ifdef CONFIG_HOTPLUG_CPU
1267 if (!setup_max_cpus)
1270 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1271 possible, setup_max_cpus);
1275 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1276 possible, max_t(int, possible - num_processors, 0));
1278 for (i = 0; i < possible; i++)
1279 set_cpu_possible(i, true);
1280 for (; i < NR_CPUS; i++)
1281 set_cpu_possible(i, false);
1283 nr_cpu_ids = possible;
1286 #ifdef CONFIG_HOTPLUG_CPU
1288 static void remove_siblinginfo(int cpu)
1291 struct cpuinfo_x86 *c = &cpu_data(cpu);
1293 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1294 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1296 * last thread sibling in this cpu core going down
1298 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1299 cpu_data(sibling).booted_cores--;
1302 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1303 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1304 cpumask_clear(cpu_sibling_mask(cpu));
1305 cpumask_clear(cpu_core_mask(cpu));
1306 c->phys_proc_id = 0;
1308 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1311 static void __ref remove_cpu_from_maps(int cpu)
1313 set_cpu_online(cpu, false);
1314 cpumask_clear_cpu(cpu, cpu_callout_mask);
1315 cpumask_clear_cpu(cpu, cpu_callin_mask);
1316 /* was set by cpu_init() */
1317 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1318 numa_remove_cpu(cpu);
1321 void cpu_disable_common(void)
1323 int cpu = smp_processor_id();
1325 remove_siblinginfo(cpu);
1327 /* It's now safe to remove this processor from the online map */
1329 remove_cpu_from_maps(cpu);
1330 unlock_vector_lock();
1334 int native_cpu_disable(void)
1338 cpu_disable_common();
1342 void native_cpu_die(unsigned int cpu)
1344 /* We don't do anything here: idle task is faking death itself. */
1347 for (i = 0; i < 10; i++) {
1348 /* They ack this in play_dead by setting CPU_DEAD */
1349 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1350 if (system_state == SYSTEM_RUNNING)
1351 pr_info("CPU %u is now offline\n", cpu);
1356 pr_err("CPU %u didn't die...\n", cpu);
1359 void play_dead_common(void)
1362 reset_lazy_tlbstate();
1363 amd_e400_remove_cpu(raw_smp_processor_id());
1367 __this_cpu_write(cpu_state, CPU_DEAD);
1370 * With physical CPU hotplug, we should halt the cpu
1372 local_irq_disable();
1375 static bool wakeup_cpu0(void)
1377 if (smp_processor_id() == 0 && enable_start_cpu0)
1384 * We need to flush the caches before going to sleep, lest we have
1385 * dirty data in our caches when we come back up.
1387 static inline void mwait_play_dead(void)
1389 unsigned int eax, ebx, ecx, edx;
1390 unsigned int highest_cstate = 0;
1391 unsigned int highest_subcstate = 0;
1395 if (!this_cpu_has(X86_FEATURE_MWAIT))
1397 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1399 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1402 eax = CPUID_MWAIT_LEAF;
1404 native_cpuid(&eax, &ebx, &ecx, &edx);
1407 * eax will be 0 if EDX enumeration is not valid.
1408 * Initialized below to cstate, sub_cstate value when EDX is valid.
1410 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1413 edx >>= MWAIT_SUBSTATE_SIZE;
1414 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1415 if (edx & MWAIT_SUBSTATE_MASK) {
1417 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1420 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1421 (highest_subcstate - 1);
1425 * This should be a memory location in a cache line which is
1426 * unlikely to be touched by other processors. The actual
1427 * content is immaterial as it is not actually modified in any way.
1429 mwait_ptr = ¤t_thread_info()->flags;
1435 * The CLFLUSH is a workaround for erratum AAI65 for
1436 * the Xeon 7400 series. It's not clear it is actually
1437 * needed, but it should be harmless in either case.
1438 * The WBINVD is insufficient due to the spurious-wakeup
1439 * case where we return around the loop.
1442 __monitor(mwait_ptr, 0, 0);
1446 * If NMI wants to wake up CPU0, start CPU0.
1453 static inline void hlt_play_dead(void)
1455 if (__this_cpu_read(cpu_info.x86) >= 4)
1461 * If NMI wants to wake up CPU0, start CPU0.
1468 void native_play_dead(void)
1471 tboot_shutdown(TB_SHUTDOWN_WFS);
1473 mwait_play_dead(); /* Only returns on failure */
1474 if (cpuidle_play_dead())
1478 #else /* ... !CONFIG_HOTPLUG_CPU */
1479 int native_cpu_disable(void)
1484 void native_cpu_die(unsigned int cpu)
1486 /* We said "no" in __cpu_disable */
1490 void native_play_dead(void)