2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
50 #include <linux/tboot.h>
51 #include <linux/stackprotector.h>
52 #include <linux/gfp.h>
59 #include <asm/trampoline.h>
62 #include <asm/pgtable.h>
63 #include <asm/tlbflush.h>
65 #include <asm/mwait.h>
67 #include <asm/setup.h>
68 #include <asm/uv/uv.h>
69 #include <linux/mc146818rtc.h>
71 #include <asm/smpboot_hooks.h>
72 #include <asm/i8259.h>
75 u8 apicid_2_node[MAX_APICID];
78 /* State of each CPU */
79 DEFINE_PER_CPU(int, cpu_state) = { 0 };
81 /* Store all idle threads, this can be reused instead of creating
82 * a new thread. Also avoids complicated thread destroy functionality
85 #ifdef CONFIG_HOTPLUG_CPU
87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
88 * removed after init for !CONFIG_HOTPLUG_CPU.
90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
95 * We need this for trampoline_base protection from concurrent accesses when
96 * off- and onlining cores wildly.
98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
100 void cpu_hotplug_driver_lock()
102 mutex_lock(&x86_cpu_hotplug_driver_mutex);
105 void cpu_hotplug_driver_unlock()
107 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
114 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
118 /* Number of siblings per CPU package */
119 int smp_num_siblings = 1;
120 EXPORT_SYMBOL(smp_num_siblings);
122 /* Last level cache ID of each logical CPU */
123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
125 /* representing HT siblings of each logical CPU */
126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
129 /* representing HT and core siblings of each logical CPU */
130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
131 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
133 /* Per CPU bogomips and other parameters */
134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
135 EXPORT_PER_CPU_SYMBOL(cpu_info);
137 atomic_t init_deasserted;
139 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
140 /* which node each logical CPU is on */
141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
142 EXPORT_SYMBOL(cpu_to_node_map);
144 /* set up a mapping between cpu and node. */
145 static void map_cpu_to_node(int cpu, int node)
147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
148 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
149 cpu_to_node_map[cpu] = node;
152 /* undo a mapping between cpu and node. */
153 static void unmap_cpu_to_node(int cpu)
157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
158 for (node = 0; node < MAX_NUMNODES; node++)
159 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]);
160 cpu_to_node_map[cpu] = 0;
162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
163 #define map_cpu_to_node(cpu, node) ({})
164 #define unmap_cpu_to_node(cpu) ({})
168 static int boot_cpu_logical_apicid;
170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
171 { [0 ... NR_CPUS-1] = BAD_APICID };
173 static void map_cpu_to_logical_apicid(void)
175 int cpu = smp_processor_id();
176 int apicid = logical_smp_processor_id();
177 int node = apic->apicid_to_node(apicid);
179 if (!node_online(node))
180 node = first_online_node;
182 cpu_2_logical_apicid[cpu] = apicid;
183 map_cpu_to_node(cpu, node);
186 void numa_remove_cpu(int cpu)
188 cpu_2_logical_apicid[cpu] = BAD_APICID;
189 unmap_cpu_to_node(cpu);
192 #define map_cpu_to_logical_apicid() do {} while (0)
196 * Report back to the Boot Processor.
199 static void __cpuinit smp_callin(void)
202 unsigned long timeout;
205 * If waken up by an INIT in an 82489DX configuration
206 * we may get here before an INIT-deassert IPI reaches
207 * our local APIC. We have to wait for the IPI or we'll
208 * lock up on an APIC access.
210 if (apic->wait_for_init_deassert)
211 apic->wait_for_init_deassert(&init_deasserted);
214 * (This works even if the APIC is not enabled.)
216 phys_id = read_apic_id();
217 cpuid = smp_processor_id();
218 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
219 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
222 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
225 * STARTUP IPIs are fragile beasts as they might sometimes
226 * trigger some glue motherboard logic. Complete APIC bus
227 * silence for 1 second, this overestimates the time the
228 * boot CPU is spending to send the up to 2 STARTUP IPIs
229 * by a factor of two. This should be enough.
233 * Waiting 2s total for startup (udelay is not yet working)
235 timeout = jiffies + 2*HZ;
236 while (time_before(jiffies, timeout)) {
238 * Has the boot CPU finished it's STARTUP sequence?
240 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
245 if (!time_before(jiffies, timeout)) {
246 panic("%s: CPU%d started up but did not get a callout!\n",
251 * the boot CPU has finished the init stage and is spinning
252 * on callin_map until we finish. We are free to set up this
253 * CPU, first the APIC. (this is probably redundant on most
257 pr_debug("CALLIN, before setup_local_APIC().\n");
258 if (apic->smp_callin_clear_local_apic)
259 apic->smp_callin_clear_local_apic();
261 end_local_APIC_setup();
262 map_cpu_to_logical_apicid();
265 * Need to setup vector mappings before we enable interrupts.
267 setup_vector_irq(smp_processor_id());
271 * Need to enable IRQs because it can take longer and then
272 * the NMI watchdog might kill us.
277 pr_debug("Stack at about %p\n", &cpuid);
280 * Save our processor parameters
282 smp_store_cpu_info(cpuid);
284 notify_cpu_starting(cpuid);
287 * Allow the master to continue.
289 cpumask_set_cpu(cpuid, cpu_callin_mask);
293 * Activate a secondary processor.
295 notrace static void __cpuinit start_secondary(void *unused)
298 * Don't put *anything* before cpu_init(), SMP booting is too
299 * fragile that we want to limit the things done here to the
300 * most necessary things.
307 /* switch away from the initial page table */
308 load_cr3(swapper_pg_dir);
312 /* otherwise gcc will move up smp_processor_id before the cpu_init */
315 * Check TSC synchronization with the BP:
317 check_tsc_sync_target();
319 /* This must be done before setting cpu_online_mask */
320 set_cpu_sibling_map(raw_smp_processor_id());
324 * We need to hold call_lock, so there is no inconsistency
325 * between the time smp_call_function() determines number of
326 * IPI recipients, and the time when the determination is made
327 * for which cpus receive the IPI. Holding this
328 * lock helps us to not include this cpu in a currently in progress
329 * smp_call_function().
331 * We need to hold vector_lock so there the set of online cpus
332 * does not change while we are assigning vectors to cpus. Holding
333 * this lock ensures we don't half assign or remove an irq from a cpu.
337 set_cpu_online(smp_processor_id(), true);
338 unlock_vector_lock();
340 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
341 x86_platform.nmi_init();
343 /* enable local interrupts */
346 /* to prevent fake stack check failure in clock setup */
347 boot_init_stack_canary();
349 x86_cpuinit.setup_percpu_clockev();
355 #ifdef CONFIG_CPUMASK_OFFSTACK
356 /* In this case, llc_shared_map is a pointer to a cpumask. */
357 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
358 const struct cpuinfo_x86 *src)
360 struct cpumask *llc = dst->llc_shared_map;
362 dst->llc_shared_map = llc;
365 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst,
366 const struct cpuinfo_x86 *src)
370 #endif /* CONFIG_CPUMASK_OFFSTACK */
373 * The bootstrap kernel entry code has set these up. Save them for
377 void __cpuinit smp_store_cpu_info(int id)
379 struct cpuinfo_x86 *c = &cpu_data(id);
381 copy_cpuinfo_x86(c, &boot_cpu_data);
384 identify_secondary_cpu(c);
387 static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
389 struct cpuinfo_x86 *c1 = &cpu_data(cpu1);
390 struct cpuinfo_x86 *c2 = &cpu_data(cpu2);
392 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
393 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
394 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
395 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
396 cpumask_set_cpu(cpu1, c2->llc_shared_map);
397 cpumask_set_cpu(cpu2, c1->llc_shared_map);
401 void __cpuinit set_cpu_sibling_map(int cpu)
404 struct cpuinfo_x86 *c = &cpu_data(cpu);
406 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
408 if (smp_num_siblings > 1) {
409 for_each_cpu(i, cpu_sibling_setup_mask) {
410 struct cpuinfo_x86 *o = &cpu_data(i);
412 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
413 if (c->phys_proc_id == o->phys_proc_id &&
414 c->compute_unit_id == o->compute_unit_id)
415 link_thread_siblings(cpu, i);
416 } else if (c->phys_proc_id == o->phys_proc_id &&
417 c->cpu_core_id == o->cpu_core_id) {
418 link_thread_siblings(cpu, i);
422 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
425 cpumask_set_cpu(cpu, c->llc_shared_map);
427 if (current_cpu_data.x86_max_cores == 1) {
428 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
433 for_each_cpu(i, cpu_sibling_setup_mask) {
434 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
435 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
436 cpumask_set_cpu(i, c->llc_shared_map);
437 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map);
439 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
440 cpumask_set_cpu(i, cpu_core_mask(cpu));
441 cpumask_set_cpu(cpu, cpu_core_mask(i));
443 * Does this new cpu bringup a new core?
445 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
447 * for each core in package, increment
448 * the booted_cores for this new cpu
450 if (cpumask_first(cpu_sibling_mask(i)) == i)
453 * increment the core count for all
454 * the other cpus in this package
457 cpu_data(i).booted_cores++;
458 } else if (i != cpu && !c->booted_cores)
459 c->booted_cores = cpu_data(i).booted_cores;
464 /* maps the cpu to the sched domain representing multi-core */
465 const struct cpumask *cpu_coregroup_mask(int cpu)
467 struct cpuinfo_x86 *c = &cpu_data(cpu);
469 * For perf, we return last level cache shared map.
470 * And for power savings, we return cpu_core_map
472 if ((sched_mc_power_savings || sched_smt_power_savings) &&
473 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
474 return cpu_core_mask(cpu);
476 return c->llc_shared_map;
479 static void impress_friends(void)
482 unsigned long bogosum = 0;
484 * Allow the user to impress friends.
486 pr_debug("Before bogomips.\n");
487 for_each_possible_cpu(cpu)
488 if (cpumask_test_cpu(cpu, cpu_callout_mask))
489 bogosum += cpu_data(cpu).loops_per_jiffy;
491 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
494 (bogosum/(5000/HZ))%100);
496 pr_debug("Before bogocount - setting activated=1.\n");
499 void __inquire_remote_apic(int apicid)
501 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
502 char *names[] = { "ID", "VERSION", "SPIV" };
506 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
508 for (i = 0; i < ARRAY_SIZE(regs); i++) {
509 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
514 status = safe_apic_wait_icr_idle();
517 "a previous APIC delivery may have failed\n");
519 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
524 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
525 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
528 case APIC_ICR_RR_VALID:
529 status = apic_read(APIC_RRR);
530 printk(KERN_CONT "%08x\n", status);
533 printk(KERN_CONT "failed\n");
539 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
540 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
541 * won't ... remember to clear down the APIC, etc later.
544 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
546 unsigned long send_status, accept_status = 0;
550 /* Boot on the stack */
551 /* Kick the second */
552 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
554 pr_debug("Waiting for send to finish...\n");
555 send_status = safe_apic_wait_icr_idle();
558 * Give the other CPU some time to accept the IPI.
561 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
562 maxlvt = lapic_get_maxlvt();
563 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
564 apic_write(APIC_ESR, 0);
565 accept_status = (apic_read(APIC_ESR) & 0xEF);
567 pr_debug("NMI sent.\n");
570 printk(KERN_ERR "APIC never delivered???\n");
572 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
574 return (send_status | accept_status);
578 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
580 unsigned long send_status, accept_status = 0;
581 int maxlvt, num_starts, j;
583 maxlvt = lapic_get_maxlvt();
586 * Be paranoid about clearing APIC errors.
588 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
589 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
590 apic_write(APIC_ESR, 0);
594 pr_debug("Asserting INIT.\n");
597 * Turn INIT on target chip
602 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
605 pr_debug("Waiting for send to finish...\n");
606 send_status = safe_apic_wait_icr_idle();
610 pr_debug("Deasserting INIT.\n");
614 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
616 pr_debug("Waiting for send to finish...\n");
617 send_status = safe_apic_wait_icr_idle();
620 atomic_set(&init_deasserted, 1);
623 * Should we send STARTUP IPIs ?
625 * Determine this based on the APIC version.
626 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
628 if (APIC_INTEGRATED(apic_version[phys_apicid]))
634 * Paravirt / VMI wants a startup IPI hook here to set up the
635 * target processor state.
637 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
638 (unsigned long)stack_start.sp);
641 * Run STARTUP IPI loop.
643 pr_debug("#startup loops: %d.\n", num_starts);
645 for (j = 1; j <= num_starts; j++) {
646 pr_debug("Sending STARTUP #%d.\n", j);
647 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
648 apic_write(APIC_ESR, 0);
650 pr_debug("After apic_write.\n");
657 /* Boot on the stack */
658 /* Kick the second */
659 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
663 * Give the other CPU some time to accept the IPI.
667 pr_debug("Startup point 1.\n");
669 pr_debug("Waiting for send to finish...\n");
670 send_status = safe_apic_wait_icr_idle();
673 * Give the other CPU some time to accept the IPI.
676 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
677 apic_write(APIC_ESR, 0);
678 accept_status = (apic_read(APIC_ESR) & 0xEF);
679 if (send_status || accept_status)
682 pr_debug("After Startup.\n");
685 printk(KERN_ERR "APIC never delivered???\n");
687 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
689 return (send_status | accept_status);
693 struct work_struct work;
694 struct task_struct *idle;
695 struct completion done;
699 static void __cpuinit do_fork_idle(struct work_struct *work)
701 struct create_idle *c_idle =
702 container_of(work, struct create_idle, work);
704 c_idle->idle = fork_idle(c_idle->cpu);
705 complete(&c_idle->done);
708 /* reduce the number of lines printed when booting a large cpu count system */
709 static void __cpuinit announce_cpu(int cpu, int apicid)
711 static int current_node = -1;
712 int node = early_cpu_to_node(cpu);
714 if (system_state == SYSTEM_BOOTING) {
715 if (node != current_node) {
716 if (current_node > (-1))
719 pr_info("Booting Node %3d, Processors ", node);
721 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
724 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
729 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
730 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
731 * Returns zero if CPU booted OK, else error code from
732 * ->wakeup_secondary_cpu.
734 static int __cpuinit do_boot_cpu(int apicid, int cpu)
736 unsigned long boot_error = 0;
737 unsigned long start_ip;
739 struct create_idle c_idle = {
741 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
744 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
746 alternatives_smp_switch(1);
748 c_idle.idle = get_idle_for_cpu(cpu);
751 * We can't use kernel_thread since we must avoid to
752 * reschedule the child.
755 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
756 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
757 init_idle(c_idle.idle, cpu);
761 schedule_work(&c_idle.work);
762 wait_for_completion(&c_idle.done);
764 if (IS_ERR(c_idle.idle)) {
765 printk("failed fork for CPU %d\n", cpu);
766 destroy_work_on_stack(&c_idle.work);
767 return PTR_ERR(c_idle.idle);
770 set_idle_for_cpu(cpu, c_idle.idle);
772 per_cpu(current_task, cpu) = c_idle.idle;
774 /* Stack for startup_32 can be just as for start_secondary onwards */
777 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
778 initial_gs = per_cpu_offset(cpu);
779 per_cpu(kernel_stack, cpu) =
780 (unsigned long)task_stack_page(c_idle.idle) -
781 KERNEL_STACK_OFFSET + THREAD_SIZE;
783 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
784 initial_code = (unsigned long)start_secondary;
785 stack_start.sp = (void *) c_idle.idle->thread.sp;
787 /* start_ip had better be page-aligned! */
788 start_ip = setup_trampoline();
790 /* So we see what's up */
791 announce_cpu(cpu, apicid);
794 * This grunge runs the startup process for
795 * the targeted processor.
798 atomic_set(&init_deasserted, 0);
800 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
802 pr_debug("Setting warm reset code and vector.\n");
804 smpboot_setup_warm_reset_vector(start_ip);
806 * Be paranoid about clearing APIC errors.
808 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
809 apic_write(APIC_ESR, 0);
815 * Kick the secondary CPU. Use the method in the APIC driver
816 * if it's defined - or use an INIT boot APIC message otherwise:
818 if (apic->wakeup_secondary_cpu)
819 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
821 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
825 * allow APs to start initializing.
827 pr_debug("Before Callout %d.\n", cpu);
828 cpumask_set_cpu(cpu, cpu_callout_mask);
829 pr_debug("After Callout %d.\n", cpu);
832 * Wait 5s total for a response
834 for (timeout = 0; timeout < 50000; timeout++) {
835 if (cpumask_test_cpu(cpu, cpu_callin_mask))
836 break; /* It has booted */
839 * Allow other tasks to run while we wait for the
840 * AP to come online. This also gives a chance
841 * for the MTRR work(triggered by the AP coming online)
842 * to be completed in the stop machine context.
847 if (cpumask_test_cpu(cpu, cpu_callin_mask))
848 pr_debug("CPU%d: has booted.\n", cpu);
851 if (*((volatile unsigned char *)trampoline_base)
853 /* trampoline started but...? */
854 pr_err("CPU%d: Stuck ??\n", cpu);
856 /* trampoline code not run */
857 pr_err("CPU%d: Not responding.\n", cpu);
858 if (apic->inquire_remote_apic)
859 apic->inquire_remote_apic(apicid);
864 /* Try to put things back the way they were before ... */
865 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
867 /* was set by do_boot_cpu() */
868 cpumask_clear_cpu(cpu, cpu_callout_mask);
870 /* was set by cpu_init() */
871 cpumask_clear_cpu(cpu, cpu_initialized_mask);
873 set_cpu_present(cpu, false);
874 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
877 /* mark "stuck" area as not stuck */
878 *((volatile unsigned long *)trampoline_base) = 0;
880 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
882 * Cleanup possible dangling ends...
884 smpboot_restore_warm_reset_vector();
887 destroy_work_on_stack(&c_idle.work);
891 int __cpuinit native_cpu_up(unsigned int cpu)
893 int apicid = apic->cpu_present_to_apicid(cpu);
897 WARN_ON(irqs_disabled());
899 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
901 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
902 !physid_isset(apicid, phys_cpu_present_map)) {
903 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
908 * Already booted CPU?
910 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
911 pr_debug("do_boot_cpu %d Already started\n", cpu);
916 * Save current MTRR state in case it was changed since early boot
917 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
921 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
923 err = do_boot_cpu(apicid, cpu);
925 pr_debug("do_boot_cpu failed %d\n", err);
930 * Check TSC synchronization with the AP (keep irqs disabled
933 local_irq_save(flags);
934 check_tsc_sync_source(cpu);
935 local_irq_restore(flags);
937 while (!cpu_online(cpu)) {
939 touch_nmi_watchdog();
946 * Fall back to non SMP mode after errors.
948 * RED-PEN audit/test this more. I bet there is more state messed up here.
950 static __init void disable_smp(void)
952 init_cpu_present(cpumask_of(0));
953 init_cpu_possible(cpumask_of(0));
954 smpboot_clear_io_apic_irqs();
956 if (smp_found_config)
957 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
959 physid_set_mask_of_physid(0, &phys_cpu_present_map);
960 map_cpu_to_logical_apicid();
961 cpumask_set_cpu(0, cpu_sibling_mask(0));
962 cpumask_set_cpu(0, cpu_core_mask(0));
966 * Various sanity checks.
968 static int __init smp_sanity_check(unsigned max_cpus)
972 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
973 if (def_to_bigsmp && nr_cpu_ids > 8) {
978 "More than 8 CPUs detected - skipping them.\n"
979 "Use CONFIG_X86_BIGSMP.\n");
982 for_each_present_cpu(cpu) {
984 set_cpu_present(cpu, false);
989 for_each_possible_cpu(cpu) {
991 set_cpu_possible(cpu, false);
999 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1001 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1002 hard_smp_processor_id());
1004 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1008 * If we couldn't find an SMP configuration at boot time,
1009 * get out of here now!
1011 if (!smp_found_config && !acpi_lapic) {
1013 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1015 if (APIC_init_uniprocessor())
1016 printk(KERN_NOTICE "Local APIC not detected."
1017 " Using dummy APIC emulation.\n");
1022 * Should not be necessary because the MP table should list the boot
1023 * CPU too, but we do it for the sake of robustness anyway.
1025 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1027 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1028 boot_cpu_physical_apicid);
1029 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1034 * If we couldn't find a local APIC, then get out of here now!
1036 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1038 if (!disable_apic) {
1039 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1040 boot_cpu_physical_apicid);
1041 pr_err("... forcing use of dummy APIC emulation."
1042 "(tell your hw vendor)\n");
1044 smpboot_clear_io_apic();
1045 arch_disable_smp_support();
1049 verify_local_APIC();
1052 * If SMP should be disabled, then really disable it!
1055 printk(KERN_INFO "SMP mode deactivated.\n");
1056 smpboot_clear_io_apic();
1060 end_local_APIC_setup();
1067 static void __init smp_cpu_index_default(void)
1070 struct cpuinfo_x86 *c;
1072 for_each_possible_cpu(i) {
1074 /* mark all to hotplug */
1075 c->cpu_index = nr_cpu_ids;
1080 * Prepare for SMP bootup. The MP table or ACPI has been read
1081 * earlier. Just do some sanity checking here and enable APIC mode.
1083 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1088 smp_cpu_index_default();
1089 current_cpu_data = boot_cpu_data;
1090 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1093 * Setup boot CPU information
1095 smp_store_cpu_info(0); /* Final full version of the data */
1096 #ifdef CONFIG_X86_32
1097 boot_cpu_logical_apicid = logical_smp_processor_id();
1099 current_thread_info()->cpu = 0; /* needed? */
1100 for_each_possible_cpu(i) {
1101 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1102 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1103 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL);
1105 set_cpu_sibling_map(0);
1108 if (smp_sanity_check(max_cpus) < 0) {
1109 printk(KERN_INFO "SMP disabled\n");
1114 default_setup_apic_routing();
1117 if (read_apic_id() != boot_cpu_physical_apicid) {
1118 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1119 read_apic_id(), boot_cpu_physical_apicid);
1120 /* Or can we switch back to PIC here? */
1127 * Switch from PIC to APIC mode.
1132 * Enable IO APIC before setting up error vector
1134 if (!skip_ioapic_setup && nr_ioapics)
1137 end_local_APIC_setup();
1139 map_cpu_to_logical_apicid();
1141 if (apic->setup_portio_remap)
1142 apic->setup_portio_remap();
1144 smpboot_setup_io_apic();
1146 * Set up local APIC timer on boot CPU.
1149 printk(KERN_INFO "CPU%d: ", 0);
1150 print_cpu_info(&cpu_data(0));
1151 x86_init.timers.setup_percpu_clockev();
1156 set_mtrr_aps_delayed_init();
1161 void arch_enable_nonboot_cpus_begin(void)
1163 set_mtrr_aps_delayed_init();
1166 void arch_enable_nonboot_cpus_end(void)
1172 * Early setup to make printk work.
1174 void __init native_smp_prepare_boot_cpu(void)
1176 int me = smp_processor_id();
1177 switch_to_new_gdt(me);
1178 /* already set me in cpu_online_mask in boot_cpu_init() */
1179 cpumask_set_cpu(me, cpu_callout_mask);
1180 per_cpu(cpu_state, me) = CPU_ONLINE;
1183 void __init native_smp_cpus_done(unsigned int max_cpus)
1185 pr_debug("Boot done.\n");
1188 #ifdef CONFIG_X86_IO_APIC
1189 setup_ioapic_dest();
1194 static int __initdata setup_possible_cpus = -1;
1195 static int __init _setup_possible_cpus(char *str)
1197 get_option(&str, &setup_possible_cpus);
1200 early_param("possible_cpus", _setup_possible_cpus);
1204 * cpu_possible_mask should be static, it cannot change as cpu's
1205 * are onlined, or offlined. The reason is per-cpu data-structures
1206 * are allocated by some modules at init time, and dont expect to
1207 * do this dynamically on cpu arrival/departure.
1208 * cpu_present_mask on the other hand can change dynamically.
1209 * In case when cpu_hotplug is not compiled, then we resort to current
1210 * behaviour, which is cpu_possible == cpu_present.
1213 * Three ways to find out the number of additional hotplug CPUs:
1214 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1215 * - The user can overwrite it with possible_cpus=NUM
1216 * - Otherwise don't reserve additional CPUs.
1217 * We do this because additional CPUs waste a lot of memory.
1220 __init void prefill_possible_map(void)
1224 /* no processor from mptable or madt */
1225 if (!num_processors)
1228 i = setup_max_cpus ?: 1;
1229 if (setup_possible_cpus == -1) {
1230 possible = num_processors;
1231 #ifdef CONFIG_HOTPLUG_CPU
1233 possible += disabled_cpus;
1239 possible = setup_possible_cpus;
1241 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1243 /* nr_cpu_ids could be reduced via nr_cpus= */
1244 if (possible > nr_cpu_ids) {
1246 "%d Processors exceeds NR_CPUS limit of %d\n",
1247 possible, nr_cpu_ids);
1248 possible = nr_cpu_ids;
1251 #ifdef CONFIG_HOTPLUG_CPU
1252 if (!setup_max_cpus)
1256 "%d Processors exceeds max_cpus limit of %u\n",
1257 possible, setup_max_cpus);
1261 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1262 possible, max_t(int, possible - num_processors, 0));
1264 for (i = 0; i < possible; i++)
1265 set_cpu_possible(i, true);
1266 for (; i < NR_CPUS; i++)
1267 set_cpu_possible(i, false);
1269 nr_cpu_ids = possible;
1272 #ifdef CONFIG_HOTPLUG_CPU
1274 static void remove_siblinginfo(int cpu)
1277 struct cpuinfo_x86 *c = &cpu_data(cpu);
1279 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1280 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1282 * last thread sibling in this cpu core going down
1284 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1285 cpu_data(sibling).booted_cores--;
1288 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1289 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1290 cpumask_clear(cpu_sibling_mask(cpu));
1291 cpumask_clear(cpu_core_mask(cpu));
1292 c->phys_proc_id = 0;
1294 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1297 static void __ref remove_cpu_from_maps(int cpu)
1299 set_cpu_online(cpu, false);
1300 cpumask_clear_cpu(cpu, cpu_callout_mask);
1301 cpumask_clear_cpu(cpu, cpu_callin_mask);
1302 /* was set by cpu_init() */
1303 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1304 numa_remove_cpu(cpu);
1307 void cpu_disable_common(void)
1309 int cpu = smp_processor_id();
1311 remove_siblinginfo(cpu);
1313 /* It's now safe to remove this processor from the online map */
1315 remove_cpu_from_maps(cpu);
1316 unlock_vector_lock();
1320 int native_cpu_disable(void)
1322 int cpu = smp_processor_id();
1325 * Perhaps use cpufreq to drop frequency, but that could go
1326 * into generic code.
1328 * We won't take down the boot processor on i386 due to some
1329 * interrupts only being able to be serviced by the BSP.
1330 * Especially so if we're not using an IOAPIC -zwane
1337 cpu_disable_common();
1341 void native_cpu_die(unsigned int cpu)
1343 /* We don't do anything here: idle task is faking death itself. */
1346 for (i = 0; i < 10; i++) {
1347 /* They ack this in play_dead by setting CPU_DEAD */
1348 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1349 if (system_state == SYSTEM_RUNNING)
1350 pr_info("CPU %u is now offline\n", cpu);
1352 if (1 == num_online_cpus())
1353 alternatives_smp_switch(0);
1358 pr_err("CPU %u didn't die...\n", cpu);
1361 void play_dead_common(void)
1364 reset_lazy_tlbstate();
1365 c1e_remove_cpu(raw_smp_processor_id());
1369 __get_cpu_var(cpu_state) = CPU_DEAD;
1372 * With physical CPU hotplug, we should halt the cpu
1374 local_irq_disable();
1378 * We need to flush the caches before going to sleep, lest we have
1379 * dirty data in our caches when we come back up.
1381 static inline void mwait_play_dead(void)
1383 unsigned int eax, ebx, ecx, edx;
1384 unsigned int highest_cstate = 0;
1385 unsigned int highest_subcstate = 0;
1389 if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT))
1391 if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH))
1393 if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1396 eax = CPUID_MWAIT_LEAF;
1398 native_cpuid(&eax, &ebx, &ecx, &edx);
1401 * eax will be 0 if EDX enumeration is not valid.
1402 * Initialized below to cstate, sub_cstate value when EDX is valid.
1404 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1407 edx >>= MWAIT_SUBSTATE_SIZE;
1408 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1409 if (edx & MWAIT_SUBSTATE_MASK) {
1411 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1414 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1415 (highest_subcstate - 1);
1419 * This should be a memory location in a cache line which is
1420 * unlikely to be touched by other processors. The actual
1421 * content is immaterial as it is not actually modified in any way.
1423 mwait_ptr = ¤t_thread_info()->flags;
1429 * The CLFLUSH is a workaround for erratum AAI65 for
1430 * the Xeon 7400 series. It's not clear it is actually
1431 * needed, but it should be harmless in either case.
1432 * The WBINVD is insufficient due to the spurious-wakeup
1433 * case where we return around the loop.
1436 __monitor(mwait_ptr, 0, 0);
1442 static inline void hlt_play_dead(void)
1444 if (current_cpu_data.x86 >= 4)
1452 void native_play_dead(void)
1455 tboot_shutdown(TB_SHUTDOWN_WFS);
1457 mwait_play_dead(); /* Only returns on failure */
1461 #else /* ... !CONFIG_HOTPLUG_CPU */
1462 int native_cpu_disable(void)
1467 void native_cpu_die(unsigned int cpu)
1469 /* We said "no" in __cpu_disable */
1473 void native_play_dead(void)