2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
61 #include <asm/realmode.h>
64 #include <asm/pgtable.h>
65 #include <asm/tlbflush.h>
67 #include <asm/mwait.h>
69 #include <asm/io_apic.h>
70 #include <asm/fpu/internal.h>
71 #include <asm/setup.h>
72 #include <asm/uv/uv.h>
73 #include <linux/mc146818rtc.h>
74 #include <asm/i8259.h>
75 #include <asm/realmode.h>
78 /* Number of siblings per CPU package */
79 int smp_num_siblings = 1;
80 EXPORT_SYMBOL(smp_num_siblings);
82 /* Last level cache ID of each logical CPU */
83 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
85 /* representing HT siblings of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 /* representing HT and core siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95 /* Per CPU bogomips and other parameters */
96 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
97 EXPORT_PER_CPU_SYMBOL(cpu_info);
99 /* Logical package management. We might want to allocate that dynamically */
100 static int *physical_to_logical_pkg __read_mostly;
101 static unsigned long *physical_package_map __read_mostly;;
102 static unsigned int max_physical_pkg_id __read_mostly;
103 unsigned int __max_logical_packages __read_mostly;
104 EXPORT_SYMBOL(__max_logical_packages);
105 static unsigned int logical_packages __read_mostly;
107 /* Maximum number of SMT threads on any online core */
108 int __max_smt_threads __read_mostly;
110 /* Flag to indicate if a complete sched domain rebuild is required */
111 bool x86_topology_update;
113 int arch_update_cpu_topology(void)
115 int retval = x86_topology_update;
117 x86_topology_update = false;
121 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
125 spin_lock_irqsave(&rtc_lock, flags);
126 CMOS_WRITE(0xa, 0xf);
127 spin_unlock_irqrestore(&rtc_lock, flags);
130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
138 static inline void smpboot_restore_warm_reset_vector(void)
143 * Install writable page 0 entry to set BIOS data area.
148 * Paranoid: Set warm reset code and vector here back
151 spin_lock_irqsave(&rtc_lock, flags);
153 spin_unlock_irqrestore(&rtc_lock, flags);
155 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
159 * Report back to the Boot Processor during boot time or to the caller processor
162 static void smp_callin(void)
167 * If waken up by an INIT in an 82489DX configuration
168 * cpu_callout_mask guarantees we don't get here before
169 * an INIT_deassert IPI reaches our local APIC, so it is
170 * now safe to touch our local APIC.
172 cpuid = smp_processor_id();
175 * (This works even if the APIC is not enabled.)
177 phys_id = read_apic_id();
180 * the boot CPU has finished the init stage and is spinning
181 * on callin_map until we finish. We are free to set up this
182 * CPU, first the APIC. (this is probably redundant on most
188 * Save our processor parameters. Note: this information
189 * is needed for clock calibration.
191 smp_store_cpu_info(cpuid);
195 * Update loops_per_jiffy in cpu_data. Previous call to
196 * smp_store_cpu_info() stored a value that is close but not as
197 * accurate as the value just calculated.
200 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
201 pr_debug("Stack at about %p\n", &cpuid);
204 * This must be done before setting cpu_online_mask
205 * or calling notify_cpu_starting.
207 set_cpu_sibling_map(raw_smp_processor_id());
210 notify_cpu_starting(cpuid);
213 * Allow the master to continue.
215 cpumask_set_cpu(cpuid, cpu_callin_mask);
218 static int cpu0_logical_apicid;
219 static int enable_start_cpu0;
221 * Activate a secondary processor.
223 static void notrace start_secondary(void *unused)
226 * Don't put *anything* before cpu_init(), SMP booting is too
227 * fragile that we want to limit the things done here to the
228 * most necessary things.
231 x86_cpuinit.early_percpu_clock_init();
235 enable_start_cpu0 = 0;
238 /* switch away from the initial page table */
239 load_cr3(swapper_pg_dir);
243 /* otherwise gcc will move up smp_processor_id before the cpu_init */
246 * Check TSC synchronization with the BP:
248 check_tsc_sync_target();
251 * Lock vector_lock and initialize the vectors on this cpu
252 * before setting the cpu online. We must set it online with
253 * vector_lock held to prevent a concurrent setup/teardown
254 * from seeing a half valid vector space.
257 setup_vector_irq(smp_processor_id());
258 set_cpu_online(smp_processor_id(), true);
259 unlock_vector_lock();
260 cpu_set_state_online(smp_processor_id());
261 x86_platform.nmi_init();
263 /* enable local interrupts */
266 /* to prevent fake stack check failure in clock setup */
267 boot_init_stack_canary();
269 x86_cpuinit.setup_percpu_clockev();
272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
276 * topology_update_package_map - Update the physical to logical package map
277 * @pkg: The physical package id as retrieved via CPUID
278 * @cpu: The cpu for which this is updated
280 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
284 /* Called from early boot ? */
285 if (!physical_package_map)
288 if (pkg >= max_physical_pkg_id)
291 /* Set the logical package id */
292 if (test_and_set_bit(pkg, physical_package_map))
295 if (logical_packages >= __max_logical_packages) {
296 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n",
297 logical_packages, cpu, __max_logical_packages);
301 new = logical_packages++;
303 pr_info("CPU %u Converting physical %u to logical package %u\n",
306 physical_to_logical_pkg[pkg] = new;
309 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
314 * topology_phys_to_logical_pkg - Map a physical package id to a logical
316 * Returns logical package id or -1 if not found
318 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
320 if (phys_pkg >= max_physical_pkg_id)
322 return physical_to_logical_pkg[phys_pkg];
324 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
326 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu)
332 * Today neither Intel nor AMD support heterogenous systems. That
333 * might change in the future....
335 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
336 * computation, this won't actually work since some Intel BIOSes
337 * report inconsistent HT data when they disable HT.
339 * In particular, they reduce the APIC-IDs to only include the cores,
340 * but leave the CPUID topology to say there are (2) siblings.
341 * This means we don't know how many threads there will be until
342 * after the APIC enumeration.
344 * By not including this we'll sometimes over-estimate the number of
345 * logical packages by the amount of !present siblings, but this is
346 * still better than MAX_LOCAL_APIC.
348 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
349 * on the command line leading to a similar issue as the HT disable
350 * problem because the hyperthreads are usually enumerated after the
353 ncpus = boot_cpu_data.x86_max_cores;
355 pr_warn("x86_max_cores == zero !?!?");
359 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
360 logical_packages = 0;
363 * Possibly larger than what we need as the number of apic ids per
364 * package can be smaller than the actual used apic ids.
366 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
367 size = max_physical_pkg_id * sizeof(unsigned int);
368 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
369 memset(physical_to_logical_pkg, 0xff, size);
370 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
371 physical_package_map = kzalloc(size, GFP_KERNEL);
373 pr_info("Max logical packages: %u\n", __max_logical_packages);
375 topology_update_package_map(c->phys_proc_id, cpu);
378 void __init smp_store_boot_cpu_info(void)
380 int id = 0; /* CPU 0 */
381 struct cpuinfo_x86 *c = &cpu_data(id);
385 smp_init_package_map(c, id);
389 * The bootstrap kernel entry code has set these up. Save them for
392 void smp_store_cpu_info(int id)
394 struct cpuinfo_x86 *c = &cpu_data(id);
399 * During boot time, CPU0 has this setup already. Save the info when
400 * bringing up AP or offlined CPU0.
402 identify_secondary_cpu(c);
406 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
408 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
410 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
414 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
416 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
418 return !WARN_ONCE(!topology_same_node(c, o),
419 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
420 "[node: %d != %d]. Ignoring dependency.\n",
421 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
424 #define link_mask(mfunc, c1, c2) \
426 cpumask_set_cpu((c1), mfunc(c2)); \
427 cpumask_set_cpu((c2), mfunc(c1)); \
430 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
432 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
435 if (c->phys_proc_id == o->phys_proc_id &&
436 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
437 c->cpu_core_id == o->cpu_core_id)
438 return topology_sane(c, o, "smt");
440 } else if (c->phys_proc_id == o->phys_proc_id &&
441 c->cpu_core_id == o->cpu_core_id) {
442 return topology_sane(c, o, "smt");
448 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
450 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
452 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
453 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
454 return topology_sane(c, o, "llc");
460 * Unlike the other levels, we do not enforce keeping a
461 * multicore group inside a NUMA node. If this happens, we will
462 * discard the MC level of the topology later.
464 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
466 if (c->phys_proc_id == o->phys_proc_id)
471 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
472 static inline int x86_sched_itmt_flags(void)
474 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
477 #ifdef CONFIG_SCHED_MC
478 static int x86_core_flags(void)
480 return cpu_core_flags() | x86_sched_itmt_flags();
483 #ifdef CONFIG_SCHED_SMT
484 static int x86_smt_flags(void)
486 return cpu_smt_flags() | x86_sched_itmt_flags();
491 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
492 #ifdef CONFIG_SCHED_SMT
493 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
495 #ifdef CONFIG_SCHED_MC
496 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
501 static struct sched_domain_topology_level x86_topology[] = {
502 #ifdef CONFIG_SCHED_SMT
503 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
505 #ifdef CONFIG_SCHED_MC
506 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
508 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
513 * Set if a package/die has multiple NUMA nodes inside.
514 * AMD Magny-Cours and Intel Cluster-on-Die have this.
516 static bool x86_has_numa_in_package;
518 void set_cpu_sibling_map(int cpu)
520 bool has_smt = smp_num_siblings > 1;
521 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
522 struct cpuinfo_x86 *c = &cpu_data(cpu);
523 struct cpuinfo_x86 *o;
526 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
529 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
530 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
531 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
536 for_each_cpu(i, cpu_sibling_setup_mask) {
539 if ((i == cpu) || (has_smt && match_smt(c, o)))
540 link_mask(topology_sibling_cpumask, cpu, i);
542 if ((i == cpu) || (has_mp && match_llc(c, o)))
543 link_mask(cpu_llc_shared_mask, cpu, i);
548 * This needs a separate iteration over the cpus because we rely on all
549 * topology_sibling_cpumask links to be set-up.
551 for_each_cpu(i, cpu_sibling_setup_mask) {
554 if ((i == cpu) || (has_mp && match_die(c, o))) {
555 link_mask(topology_core_cpumask, cpu, i);
558 * Does this new cpu bringup a new core?
561 topology_sibling_cpumask(cpu)) == 1) {
563 * for each core in package, increment
564 * the booted_cores for this new cpu
567 topology_sibling_cpumask(i)) == i)
570 * increment the core count for all
571 * the other cpus in this package
574 cpu_data(i).booted_cores++;
575 } else if (i != cpu && !c->booted_cores)
576 c->booted_cores = cpu_data(i).booted_cores;
578 if (match_die(c, o) && !topology_same_node(c, o))
579 x86_has_numa_in_package = true;
582 threads = cpumask_weight(topology_sibling_cpumask(cpu));
583 if (threads > __max_smt_threads)
584 __max_smt_threads = threads;
587 /* maps the cpu to the sched domain representing multi-core */
588 const struct cpumask *cpu_coregroup_mask(int cpu)
590 return cpu_llc_shared_mask(cpu);
593 static void impress_friends(void)
596 unsigned long bogosum = 0;
598 * Allow the user to impress friends.
600 pr_debug("Before bogomips\n");
601 for_each_possible_cpu(cpu)
602 if (cpumask_test_cpu(cpu, cpu_callout_mask))
603 bogosum += cpu_data(cpu).loops_per_jiffy;
604 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
607 (bogosum/(5000/HZ))%100);
609 pr_debug("Before bogocount - setting activated=1\n");
612 void __inquire_remote_apic(int apicid)
614 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
615 const char * const names[] = { "ID", "VERSION", "SPIV" };
619 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
621 for (i = 0; i < ARRAY_SIZE(regs); i++) {
622 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
627 status = safe_apic_wait_icr_idle();
629 pr_cont("a previous APIC delivery may have failed\n");
631 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
636 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
637 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
640 case APIC_ICR_RR_VALID:
641 status = apic_read(APIC_RRR);
642 pr_cont("%08x\n", status);
651 * The Multiprocessor Specification 1.4 (1997) example code suggests
652 * that there should be a 10ms delay between the BSP asserting INIT
653 * and de-asserting INIT, when starting a remote processor.
654 * But that slows boot and resume on modern processors, which include
655 * many cores and don't require that delay.
657 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
658 * Modern processor families are quirked to remove the delay entirely.
660 #define UDELAY_10MS_DEFAULT 10000
662 static unsigned int init_udelay = UINT_MAX;
664 static int __init cpu_init_udelay(char *str)
666 get_option(&str, &init_udelay);
670 early_param("cpu_init_udelay", cpu_init_udelay);
672 static void __init smp_quirk_init_udelay(void)
674 /* if cmdline changed it from default, leave it alone */
675 if (init_udelay != UINT_MAX)
678 /* if modern processor, use no delay */
679 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
680 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
684 /* else, use legacy delay */
685 init_udelay = UDELAY_10MS_DEFAULT;
689 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
690 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
691 * won't ... remember to clear down the APIC, etc later.
694 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
696 unsigned long send_status, accept_status = 0;
700 /* Boot on the stack */
701 /* Kick the second */
702 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
704 pr_debug("Waiting for send to finish...\n");
705 send_status = safe_apic_wait_icr_idle();
708 * Give the other CPU some time to accept the IPI.
711 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
712 maxlvt = lapic_get_maxlvt();
713 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
714 apic_write(APIC_ESR, 0);
715 accept_status = (apic_read(APIC_ESR) & 0xEF);
717 pr_debug("NMI sent\n");
720 pr_err("APIC never delivered???\n");
722 pr_err("APIC delivery error (%lx)\n", accept_status);
724 return (send_status | accept_status);
728 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
730 unsigned long send_status = 0, accept_status = 0;
731 int maxlvt, num_starts, j;
733 maxlvt = lapic_get_maxlvt();
736 * Be paranoid about clearing APIC errors.
738 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
739 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
740 apic_write(APIC_ESR, 0);
744 pr_debug("Asserting INIT\n");
747 * Turn INIT on target chip
752 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
755 pr_debug("Waiting for send to finish...\n");
756 send_status = safe_apic_wait_icr_idle();
760 pr_debug("Deasserting INIT\n");
764 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
766 pr_debug("Waiting for send to finish...\n");
767 send_status = safe_apic_wait_icr_idle();
772 * Should we send STARTUP IPIs ?
774 * Determine this based on the APIC version.
775 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
777 if (APIC_INTEGRATED(boot_cpu_apic_version))
783 * Run STARTUP IPI loop.
785 pr_debug("#startup loops: %d\n", num_starts);
787 for (j = 1; j <= num_starts; j++) {
788 pr_debug("Sending STARTUP #%d\n", j);
789 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
790 apic_write(APIC_ESR, 0);
792 pr_debug("After apic_write\n");
799 /* Boot on the stack */
800 /* Kick the second */
801 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
805 * Give the other CPU some time to accept the IPI.
807 if (init_udelay == 0)
812 pr_debug("Startup point 1\n");
814 pr_debug("Waiting for send to finish...\n");
815 send_status = safe_apic_wait_icr_idle();
818 * Give the other CPU some time to accept the IPI.
820 if (init_udelay == 0)
825 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
826 apic_write(APIC_ESR, 0);
827 accept_status = (apic_read(APIC_ESR) & 0xEF);
828 if (send_status || accept_status)
831 pr_debug("After Startup\n");
834 pr_err("APIC never delivered???\n");
836 pr_err("APIC delivery error (%lx)\n", accept_status);
838 return (send_status | accept_status);
841 /* reduce the number of lines printed when booting a large cpu count system */
842 static void announce_cpu(int cpu, int apicid)
844 static int current_node = -1;
845 int node = early_cpu_to_node(cpu);
846 static int width, node_width;
849 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
852 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
855 printk(KERN_INFO "x86: Booting SMP configuration:\n");
857 if (system_state == SYSTEM_BOOTING) {
858 if (node != current_node) {
859 if (current_node > (-1))
863 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
864 node_width - num_digits(node), " ", node);
867 /* Add padding for the BSP */
869 pr_cont("%*s", width + 1, " ");
871 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
874 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
878 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
882 cpu = smp_processor_id();
883 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
890 * Wake up AP by INIT, INIT, STARTUP sequence.
892 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
893 * boot-strap code which is not a desired behavior for waking up BSP. To
894 * void the boot-strap code, wake up CPU0 by NMI instead.
896 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
897 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
898 * We'll change this code in the future to wake up hard offlined CPU0 if
899 * real platform and request are available.
902 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
903 int *cpu0_nmi_registered)
911 * Wake up AP by INIT, INIT, STARTUP sequence.
914 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
919 * Wake up BSP by nmi.
921 * Register a NMI handler to help wake up CPU0.
923 boot_error = register_nmi_handler(NMI_LOCAL,
924 wakeup_cpu0_nmi, 0, "wake_cpu0");
927 enable_start_cpu0 = 1;
928 *cpu0_nmi_registered = 1;
929 if (apic->dest_logical == APIC_DEST_LOGICAL)
930 id = cpu0_logical_apicid;
933 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
942 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
944 /* Just in case we booted with a single CPU. */
945 alternatives_enable_smp();
947 per_cpu(current_task, cpu) = idle;
950 /* Stack for startup_32 can be just as for start_secondary onwards */
952 per_cpu(cpu_current_top_of_stack, cpu) =
953 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
955 initial_gs = per_cpu_offset(cpu);
960 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
961 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
962 * Returns zero if CPU booted OK, else error code from
963 * ->wakeup_secondary_cpu.
965 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
967 volatile u32 *trampoline_status =
968 (volatile u32 *) __va(real_mode_header->trampoline_status);
969 /* start_ip had better be page-aligned! */
970 unsigned long start_ip = real_mode_header->trampoline_start;
972 unsigned long boot_error = 0;
973 int cpu0_nmi_registered = 0;
974 unsigned long timeout;
976 idle->thread.sp = (unsigned long)task_pt_regs(idle);
977 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
978 initial_code = (unsigned long)start_secondary;
979 initial_stack = idle->thread.sp;
982 * Enable the espfix hack for this CPU
984 #ifdef CONFIG_X86_ESPFIX64
988 /* So we see what's up */
989 announce_cpu(cpu, apicid);
992 * This grunge runs the startup process for
993 * the targeted processor.
996 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
998 pr_debug("Setting warm reset code and vector.\n");
1000 smpboot_setup_warm_reset_vector(start_ip);
1002 * Be paranoid about clearing APIC errors.
1004 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1005 apic_write(APIC_ESR, 0);
1006 apic_read(APIC_ESR);
1011 * AP might wait on cpu_callout_mask in cpu_init() with
1012 * cpu_initialized_mask set if previous attempt to online
1013 * it timed-out. Clear cpu_initialized_mask so that after
1014 * INIT/SIPI it could start with a clean state.
1016 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1020 * Wake up a CPU in difference cases:
1021 * - Use the method in the APIC driver if it's defined
1023 * - Use an INIT boot APIC message for APs or NMI for BSP.
1025 if (apic->wakeup_secondary_cpu)
1026 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1028 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1029 &cpu0_nmi_registered);
1033 * Wait 10s total for first sign of life from AP
1036 timeout = jiffies + 10*HZ;
1037 while (time_before(jiffies, timeout)) {
1038 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1040 * Tell AP to proceed with initialization
1042 cpumask_set_cpu(cpu, cpu_callout_mask);
1052 * Wait till AP completes initial initialization
1054 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1056 * Allow other tasks to run while we wait for the
1057 * AP to come online. This also gives a chance
1058 * for the MTRR work(triggered by the AP coming online)
1059 * to be completed in the stop machine context.
1065 /* mark "stuck" area as not stuck */
1066 *trampoline_status = 0;
1068 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1070 * Cleanup possible dangling ends...
1072 smpboot_restore_warm_reset_vector();
1075 * Clean up the nmi handler. Do this after the callin and callout sync
1076 * to avoid impact of possible long unregister time.
1078 if (cpu0_nmi_registered)
1079 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1084 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1086 int apicid = apic->cpu_present_to_apicid(cpu);
1087 unsigned long flags;
1090 WARN_ON(irqs_disabled());
1092 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1094 if (apicid == BAD_APICID ||
1095 !physid_isset(apicid, phys_cpu_present_map) ||
1096 !apic->apic_id_valid(apicid)) {
1097 pr_err("%s: bad cpu %d\n", __func__, cpu);
1102 * Already booted CPU?
1104 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1105 pr_debug("do_boot_cpu %d Already started\n", cpu);
1110 * Save current MTRR state in case it was changed since early boot
1111 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1115 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1116 err = cpu_check_up_prepare(cpu);
1117 if (err && err != -EBUSY)
1120 /* the FPU context is blank, nobody can own it */
1121 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1123 common_cpu_up(cpu, tidle);
1125 err = do_boot_cpu(apicid, cpu, tidle);
1127 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1132 * Check TSC synchronization with the AP (keep irqs disabled
1135 local_irq_save(flags);
1136 check_tsc_sync_source(cpu);
1137 local_irq_restore(flags);
1139 while (!cpu_online(cpu)) {
1141 touch_nmi_watchdog();
1148 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1150 void arch_disable_smp_support(void)
1152 disable_ioapic_support();
1156 * Fall back to non SMP mode after errors.
1158 * RED-PEN audit/test this more. I bet there is more state messed up here.
1160 static __init void disable_smp(void)
1162 pr_info("SMP disabled\n");
1164 disable_ioapic_support();
1166 init_cpu_present(cpumask_of(0));
1167 init_cpu_possible(cpumask_of(0));
1169 if (smp_found_config)
1170 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1172 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1173 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1174 cpumask_set_cpu(0, topology_core_cpumask(0));
1185 * Various sanity checks.
1187 static int __init smp_sanity_check(unsigned max_cpus)
1191 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1192 if (def_to_bigsmp && nr_cpu_ids > 8) {
1196 pr_warn("More than 8 CPUs detected - skipping them\n"
1197 "Use CONFIG_X86_BIGSMP\n");
1200 for_each_present_cpu(cpu) {
1202 set_cpu_present(cpu, false);
1207 for_each_possible_cpu(cpu) {
1209 set_cpu_possible(cpu, false);
1217 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1218 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1219 hard_smp_processor_id());
1221 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1225 * If we couldn't find an SMP configuration at boot time,
1226 * get out of here now!
1228 if (!smp_found_config && !acpi_lapic) {
1230 pr_notice("SMP motherboard not detected\n");
1231 return SMP_NO_CONFIG;
1235 * Should not be necessary because the MP table should list the boot
1236 * CPU too, but we do it for the sake of robustness anyway.
1238 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1239 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1240 boot_cpu_physical_apicid);
1241 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1246 * If we couldn't find a local APIC, then get out of here now!
1248 if (APIC_INTEGRATED(boot_cpu_apic_version) &&
1249 !boot_cpu_has(X86_FEATURE_APIC)) {
1250 if (!disable_apic) {
1251 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1252 boot_cpu_physical_apicid);
1253 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1259 * If SMP should be disabled, then really disable it!
1262 pr_info("SMP mode deactivated\n");
1263 return SMP_FORCE_UP;
1269 static void __init smp_cpu_index_default(void)
1272 struct cpuinfo_x86 *c;
1274 for_each_possible_cpu(i) {
1276 /* mark all to hotplug */
1277 c->cpu_index = nr_cpu_ids;
1282 * Prepare for SMP bootup. The MP table or ACPI has been read
1283 * earlier. Just do some sanity checking here and enable APIC mode.
1285 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1289 smp_cpu_index_default();
1292 * Setup boot CPU information
1294 smp_store_boot_cpu_info(); /* Final full version of the data */
1295 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1298 for_each_possible_cpu(i) {
1299 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1300 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1301 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1305 * Set 'default' x86 topology, this matches default_topology() in that
1306 * it has NUMA nodes as a topology level. See also
1307 * native_smp_cpus_done().
1309 * Must be done before set_cpus_sibling_map() is ran.
1311 set_sched_topology(x86_topology);
1313 set_cpu_sibling_map(0);
1315 switch (smp_sanity_check(max_cpus)) {
1318 if (APIC_init_uniprocessor())
1319 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1326 apic_bsp_setup(false);
1332 if (read_apic_id() != boot_cpu_physical_apicid) {
1333 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1334 read_apic_id(), boot_cpu_physical_apicid);
1335 /* Or can we switch back to PIC here? */
1338 default_setup_apic_routing();
1339 cpu0_logical_apicid = apic_bsp_setup(false);
1342 print_cpu_info(&cpu_data(0));
1347 set_mtrr_aps_delayed_init();
1349 smp_quirk_init_udelay();
1352 void arch_enable_nonboot_cpus_begin(void)
1354 set_mtrr_aps_delayed_init();
1357 void arch_enable_nonboot_cpus_end(void)
1363 * Early setup to make printk work.
1365 void __init native_smp_prepare_boot_cpu(void)
1367 int me = smp_processor_id();
1368 switch_to_new_gdt(me);
1369 /* already set me in cpu_online_mask in boot_cpu_init() */
1370 cpumask_set_cpu(me, cpu_callout_mask);
1371 cpu_set_state_online(me);
1374 void __init native_smp_cpus_done(unsigned int max_cpus)
1376 pr_debug("Boot done\n");
1378 if (x86_has_numa_in_package)
1379 set_sched_topology(x86_numa_in_package_topology);
1383 setup_ioapic_dest();
1387 static int __initdata setup_possible_cpus = -1;
1388 static int __init _setup_possible_cpus(char *str)
1390 get_option(&str, &setup_possible_cpus);
1393 early_param("possible_cpus", _setup_possible_cpus);
1397 * cpu_possible_mask should be static, it cannot change as cpu's
1398 * are onlined, or offlined. The reason is per-cpu data-structures
1399 * are allocated by some modules at init time, and dont expect to
1400 * do this dynamically on cpu arrival/departure.
1401 * cpu_present_mask on the other hand can change dynamically.
1402 * In case when cpu_hotplug is not compiled, then we resort to current
1403 * behaviour, which is cpu_possible == cpu_present.
1406 * Three ways to find out the number of additional hotplug CPUs:
1407 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1408 * - The user can overwrite it with possible_cpus=NUM
1409 * - Otherwise don't reserve additional CPUs.
1410 * We do this because additional CPUs waste a lot of memory.
1413 __init void prefill_possible_map(void)
1417 /* No boot processor was found in mptable or ACPI MADT */
1418 if (!num_processors) {
1419 if (boot_cpu_has(X86_FEATURE_APIC)) {
1420 int apicid = boot_cpu_physical_apicid;
1421 int cpu = hard_smp_processor_id();
1423 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1425 /* Make sure boot cpu is enumerated */
1426 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1427 apic->apic_id_valid(apicid))
1428 generic_processor_info(apicid, boot_cpu_apic_version);
1431 if (!num_processors)
1435 i = setup_max_cpus ?: 1;
1436 if (setup_possible_cpus == -1) {
1437 possible = num_processors;
1438 #ifdef CONFIG_HOTPLUG_CPU
1440 possible += disabled_cpus;
1446 possible = setup_possible_cpus;
1448 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1450 /* nr_cpu_ids could be reduced via nr_cpus= */
1451 if (possible > nr_cpu_ids) {
1452 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1453 possible, nr_cpu_ids);
1454 possible = nr_cpu_ids;
1457 #ifdef CONFIG_HOTPLUG_CPU
1458 if (!setup_max_cpus)
1461 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1462 possible, setup_max_cpus);
1466 nr_cpu_ids = possible;
1468 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1469 possible, max_t(int, possible - num_processors, 0));
1471 reset_cpu_possible_mask();
1473 for (i = 0; i < possible; i++)
1474 set_cpu_possible(i, true);
1477 #ifdef CONFIG_HOTPLUG_CPU
1479 /* Recompute SMT state for all CPUs on offline */
1480 static void recompute_smt_state(void)
1482 int max_threads, cpu;
1485 for_each_online_cpu (cpu) {
1486 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1488 if (threads > max_threads)
1489 max_threads = threads;
1491 __max_smt_threads = max_threads;
1494 static void remove_siblinginfo(int cpu)
1497 struct cpuinfo_x86 *c = &cpu_data(cpu);
1499 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1500 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1502 * last thread sibling in this cpu core going down
1504 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1505 cpu_data(sibling).booted_cores--;
1508 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1509 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1510 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1511 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1512 cpumask_clear(cpu_llc_shared_mask(cpu));
1513 cpumask_clear(topology_sibling_cpumask(cpu));
1514 cpumask_clear(topology_core_cpumask(cpu));
1515 c->phys_proc_id = 0;
1517 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1518 recompute_smt_state();
1521 static void remove_cpu_from_maps(int cpu)
1523 set_cpu_online(cpu, false);
1524 cpumask_clear_cpu(cpu, cpu_callout_mask);
1525 cpumask_clear_cpu(cpu, cpu_callin_mask);
1526 /* was set by cpu_init() */
1527 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1528 numa_remove_cpu(cpu);
1531 void cpu_disable_common(void)
1533 int cpu = smp_processor_id();
1535 remove_siblinginfo(cpu);
1537 /* It's now safe to remove this processor from the online map */
1539 remove_cpu_from_maps(cpu);
1540 unlock_vector_lock();
1544 int native_cpu_disable(void)
1548 ret = check_irq_vectors_for_cpu_disable();
1553 cpu_disable_common();
1558 int common_cpu_die(unsigned int cpu)
1562 /* We don't do anything here: idle task is faking death itself. */
1564 /* They ack this in play_dead() by setting CPU_DEAD */
1565 if (cpu_wait_death(cpu, 5)) {
1566 if (system_state == SYSTEM_RUNNING)
1567 pr_info("CPU %u is now offline\n", cpu);
1569 pr_err("CPU %u didn't die...\n", cpu);
1576 void native_cpu_die(unsigned int cpu)
1578 common_cpu_die(cpu);
1581 void play_dead_common(void)
1584 reset_lazy_tlbstate();
1587 (void)cpu_report_death();
1590 * With physical CPU hotplug, we should halt the cpu
1592 local_irq_disable();
1595 static bool wakeup_cpu0(void)
1597 if (smp_processor_id() == 0 && enable_start_cpu0)
1604 * We need to flush the caches before going to sleep, lest we have
1605 * dirty data in our caches when we come back up.
1607 static inline void mwait_play_dead(void)
1609 unsigned int eax, ebx, ecx, edx;
1610 unsigned int highest_cstate = 0;
1611 unsigned int highest_subcstate = 0;
1615 if (!this_cpu_has(X86_FEATURE_MWAIT))
1617 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1619 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1622 eax = CPUID_MWAIT_LEAF;
1624 native_cpuid(&eax, &ebx, &ecx, &edx);
1627 * eax will be 0 if EDX enumeration is not valid.
1628 * Initialized below to cstate, sub_cstate value when EDX is valid.
1630 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1633 edx >>= MWAIT_SUBSTATE_SIZE;
1634 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1635 if (edx & MWAIT_SUBSTATE_MASK) {
1637 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1640 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1641 (highest_subcstate - 1);
1645 * This should be a memory location in a cache line which is
1646 * unlikely to be touched by other processors. The actual
1647 * content is immaterial as it is not actually modified in any way.
1649 mwait_ptr = ¤t_thread_info()->flags;
1655 * The CLFLUSH is a workaround for erratum AAI65 for
1656 * the Xeon 7400 series. It's not clear it is actually
1657 * needed, but it should be harmless in either case.
1658 * The WBINVD is insufficient due to the spurious-wakeup
1659 * case where we return around the loop.
1664 __monitor(mwait_ptr, 0, 0);
1668 * If NMI wants to wake up CPU0, start CPU0.
1675 void hlt_play_dead(void)
1677 if (__this_cpu_read(cpu_info.x86) >= 4)
1683 * If NMI wants to wake up CPU0, start CPU0.
1690 void native_play_dead(void)
1693 tboot_shutdown(TB_SHUTDOWN_WFS);
1695 mwait_play_dead(); /* Only returns on failure */
1696 if (cpuidle_play_dead())
1700 #else /* ... !CONFIG_HOTPLUG_CPU */
1701 int native_cpu_disable(void)
1706 void native_cpu_die(unsigned int cpu)
1708 /* We said "no" in __cpu_disable */
1712 void native_play_dead(void)