2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
61 #include <asm/realmode.h>
64 #include <asm/pgtable.h>
65 #include <asm/tlbflush.h>
67 #include <asm/mwait.h>
69 #include <asm/io_apic.h>
70 #include <asm/fpu/internal.h>
71 #include <asm/setup.h>
72 #include <asm/uv/uv.h>
73 #include <linux/mc146818rtc.h>
74 #include <asm/i8259.h>
75 #include <asm/realmode.h>
78 /* Number of siblings per CPU package */
79 int smp_num_siblings = 1;
80 EXPORT_SYMBOL(smp_num_siblings);
82 /* Last level cache ID of each logical CPU */
83 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
85 /* representing HT siblings of each logical CPU */
86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 /* representing HT and core siblings of each logical CPU */
90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95 /* Per CPU bogomips and other parameters */
96 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
97 EXPORT_PER_CPU_SYMBOL(cpu_info);
99 /* Logical package management. We might want to allocate that dynamically */
100 static int *physical_to_logical_pkg __read_mostly;
101 static unsigned long *physical_package_map __read_mostly;;
102 static unsigned int max_physical_pkg_id __read_mostly;
103 unsigned int __max_logical_packages __read_mostly;
104 EXPORT_SYMBOL(__max_logical_packages);
105 static unsigned int logical_packages __read_mostly;
106 static bool logical_packages_frozen __read_mostly;
108 /* Maximum number of SMT threads on any online core */
109 int __max_smt_threads __read_mostly;
111 /* Flag to indicate if a complete sched domain rebuild is required */
112 bool x86_topology_update;
114 int arch_update_cpu_topology(void)
116 int retval = x86_topology_update;
118 x86_topology_update = false;
122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
126 spin_lock_irqsave(&rtc_lock, flags);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock, flags);
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
139 static inline void smpboot_restore_warm_reset_vector(void)
144 * Install writable page 0 entry to set BIOS data area.
149 * Paranoid: Set warm reset code and vector here back
152 spin_lock_irqsave(&rtc_lock, flags);
154 spin_unlock_irqrestore(&rtc_lock, flags);
156 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
160 * Report back to the Boot Processor during boot time or to the caller processor
163 static void smp_callin(void)
168 * If waken up by an INIT in an 82489DX configuration
169 * cpu_callout_mask guarantees we don't get here before
170 * an INIT_deassert IPI reaches our local APIC, so it is
171 * now safe to touch our local APIC.
173 cpuid = smp_processor_id();
176 * (This works even if the APIC is not enabled.)
178 phys_id = read_apic_id();
181 * the boot CPU has finished the init stage and is spinning
182 * on callin_map until we finish. We are free to set up this
183 * CPU, first the APIC. (this is probably redundant on most
189 * Save our processor parameters. Note: this information
190 * is needed for clock calibration.
192 smp_store_cpu_info(cpuid);
196 * Update loops_per_jiffy in cpu_data. Previous call to
197 * smp_store_cpu_info() stored a value that is close but not as
198 * accurate as the value just calculated.
201 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
202 pr_debug("Stack at about %p\n", &cpuid);
205 * This must be done before setting cpu_online_mask
206 * or calling notify_cpu_starting.
208 set_cpu_sibling_map(raw_smp_processor_id());
211 notify_cpu_starting(cpuid);
214 * Allow the master to continue.
216 cpumask_set_cpu(cpuid, cpu_callin_mask);
219 static int cpu0_logical_apicid;
220 static int enable_start_cpu0;
222 * Activate a secondary processor.
224 static void notrace start_secondary(void *unused)
227 * Don't put *anything* before cpu_init(), SMP booting is too
228 * fragile that we want to limit the things done here to the
229 * most necessary things.
232 x86_cpuinit.early_percpu_clock_init();
236 enable_start_cpu0 = 0;
239 /* switch away from the initial page table */
240 load_cr3(swapper_pg_dir);
244 /* otherwise gcc will move up smp_processor_id before the cpu_init */
247 * Check TSC synchronization with the BP:
249 check_tsc_sync_target();
252 * Lock vector_lock and initialize the vectors on this cpu
253 * before setting the cpu online. We must set it online with
254 * vector_lock held to prevent a concurrent setup/teardown
255 * from seeing a half valid vector space.
258 setup_vector_irq(smp_processor_id());
259 set_cpu_online(smp_processor_id(), true);
260 unlock_vector_lock();
261 cpu_set_state_online(smp_processor_id());
262 x86_platform.nmi_init();
264 /* enable local interrupts */
267 /* to prevent fake stack check failure in clock setup */
268 boot_init_stack_canary();
270 x86_cpuinit.setup_percpu_clockev();
273 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
276 int topology_update_package_map(unsigned int apicid, unsigned int cpu)
278 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits;
280 /* Called from early boot ? */
281 if (!physical_package_map)
284 if (pkg >= max_physical_pkg_id)
287 /* Set the logical package id */
288 if (test_and_set_bit(pkg, physical_package_map))
291 if (logical_packages_frozen) {
292 physical_to_logical_pkg[pkg] = -1;
293 pr_warn("APIC(%x) Package %u exceeds logical package max\n",
298 new = logical_packages++;
299 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
301 physical_to_logical_pkg[pkg] = new;
304 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
309 * topology_phys_to_logical_pkg - Map a physical package id to a logical
311 * Returns logical package id or -1 if not found
313 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
315 if (phys_pkg >= max_physical_pkg_id)
317 return physical_to_logical_pkg[phys_pkg];
319 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
321 static void __init smp_init_package_map(void)
323 unsigned int ncpus, cpu;
327 * Today neither Intel nor AMD support heterogenous systems. That
328 * might change in the future....
330 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
331 * computation, this won't actually work since some Intel BIOSes
332 * report inconsistent HT data when they disable HT.
334 * In particular, they reduce the APIC-IDs to only include the cores,
335 * but leave the CPUID topology to say there are (2) siblings.
336 * This means we don't know how many threads there will be until
337 * after the APIC enumeration.
339 * By not including this we'll sometimes over-estimate the number of
340 * logical packages by the amount of !present siblings, but this is
341 * still better than MAX_LOCAL_APIC.
343 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
344 * on the command line leading to a similar issue as the HT disable
345 * problem because the hyperthreads are usually enumerated after the
348 ncpus = boot_cpu_data.x86_max_cores;
350 pr_warn("x86_max_cores == zero !?!?");
354 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
355 logical_packages = 0;
358 * Possibly larger than what we need as the number of apic ids per
359 * package can be smaller than the actual used apic ids.
361 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
362 size = max_physical_pkg_id * sizeof(unsigned int);
363 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
364 memset(physical_to_logical_pkg, 0xff, size);
365 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
366 physical_package_map = kzalloc(size, GFP_KERNEL);
368 for_each_present_cpu(cpu) {
369 unsigned int apicid = apic->cpu_present_to_apicid(cpu);
371 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid))
373 if (!topology_update_package_map(apicid, cpu))
375 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid);
376 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID;
377 set_cpu_possible(cpu, false);
378 set_cpu_present(cpu, false);
381 if (logical_packages > __max_logical_packages) {
382 pr_warn("Detected more packages (%u), then computed by BIOS data (%u).\n",
383 logical_packages, __max_logical_packages);
384 logical_packages_frozen = true;
385 __max_logical_packages = logical_packages;
388 pr_info("Max logical packages: %u\n", __max_logical_packages);
391 void __init smp_store_boot_cpu_info(void)
393 int id = 0; /* CPU 0 */
394 struct cpuinfo_x86 *c = &cpu_data(id);
398 smp_init_package_map();
402 * The bootstrap kernel entry code has set these up. Save them for
405 void smp_store_cpu_info(int id)
407 struct cpuinfo_x86 *c = &cpu_data(id);
412 * During boot time, CPU0 has this setup already. Save the info when
413 * bringing up AP or offlined CPU0.
415 identify_secondary_cpu(c);
419 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
421 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
423 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
427 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
429 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
431 return !WARN_ONCE(!topology_same_node(c, o),
432 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
433 "[node: %d != %d]. Ignoring dependency.\n",
434 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
437 #define link_mask(mfunc, c1, c2) \
439 cpumask_set_cpu((c1), mfunc(c2)); \
440 cpumask_set_cpu((c2), mfunc(c1)); \
443 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
445 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
446 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
448 if (c->phys_proc_id == o->phys_proc_id &&
449 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
450 c->cpu_core_id == o->cpu_core_id)
451 return topology_sane(c, o, "smt");
453 } else if (c->phys_proc_id == o->phys_proc_id &&
454 c->cpu_core_id == o->cpu_core_id) {
455 return topology_sane(c, o, "smt");
461 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
463 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
465 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
466 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
467 return topology_sane(c, o, "llc");
473 * Unlike the other levels, we do not enforce keeping a
474 * multicore group inside a NUMA node. If this happens, we will
475 * discard the MC level of the topology later.
477 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
479 if (c->phys_proc_id == o->phys_proc_id)
484 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
485 static inline int x86_sched_itmt_flags(void)
487 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
490 #ifdef CONFIG_SCHED_MC
491 static int x86_core_flags(void)
493 return cpu_core_flags() | x86_sched_itmt_flags();
496 #ifdef CONFIG_SCHED_SMT
497 static int x86_smt_flags(void)
499 return cpu_smt_flags() | x86_sched_itmt_flags();
504 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
505 #ifdef CONFIG_SCHED_SMT
506 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
508 #ifdef CONFIG_SCHED_MC
509 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
514 static struct sched_domain_topology_level x86_topology[] = {
515 #ifdef CONFIG_SCHED_SMT
516 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
518 #ifdef CONFIG_SCHED_MC
519 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
521 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
526 * Set if a package/die has multiple NUMA nodes inside.
527 * AMD Magny-Cours and Intel Cluster-on-Die have this.
529 static bool x86_has_numa_in_package;
531 void set_cpu_sibling_map(int cpu)
533 bool has_smt = smp_num_siblings > 1;
534 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
535 struct cpuinfo_x86 *c = &cpu_data(cpu);
536 struct cpuinfo_x86 *o;
539 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
542 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
543 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
544 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
549 for_each_cpu(i, cpu_sibling_setup_mask) {
552 if ((i == cpu) || (has_smt && match_smt(c, o)))
553 link_mask(topology_sibling_cpumask, cpu, i);
555 if ((i == cpu) || (has_mp && match_llc(c, o)))
556 link_mask(cpu_llc_shared_mask, cpu, i);
561 * This needs a separate iteration over the cpus because we rely on all
562 * topology_sibling_cpumask links to be set-up.
564 for_each_cpu(i, cpu_sibling_setup_mask) {
567 if ((i == cpu) || (has_mp && match_die(c, o))) {
568 link_mask(topology_core_cpumask, cpu, i);
571 * Does this new cpu bringup a new core?
574 topology_sibling_cpumask(cpu)) == 1) {
576 * for each core in package, increment
577 * the booted_cores for this new cpu
580 topology_sibling_cpumask(i)) == i)
583 * increment the core count for all
584 * the other cpus in this package
587 cpu_data(i).booted_cores++;
588 } else if (i != cpu && !c->booted_cores)
589 c->booted_cores = cpu_data(i).booted_cores;
591 if (match_die(c, o) && !topology_same_node(c, o))
592 x86_has_numa_in_package = true;
595 threads = cpumask_weight(topology_sibling_cpumask(cpu));
596 if (threads > __max_smt_threads)
597 __max_smt_threads = threads;
600 /* maps the cpu to the sched domain representing multi-core */
601 const struct cpumask *cpu_coregroup_mask(int cpu)
603 return cpu_llc_shared_mask(cpu);
606 static void impress_friends(void)
609 unsigned long bogosum = 0;
611 * Allow the user to impress friends.
613 pr_debug("Before bogomips\n");
614 for_each_possible_cpu(cpu)
615 if (cpumask_test_cpu(cpu, cpu_callout_mask))
616 bogosum += cpu_data(cpu).loops_per_jiffy;
617 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
620 (bogosum/(5000/HZ))%100);
622 pr_debug("Before bogocount - setting activated=1\n");
625 void __inquire_remote_apic(int apicid)
627 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
628 const char * const names[] = { "ID", "VERSION", "SPIV" };
632 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
634 for (i = 0; i < ARRAY_SIZE(regs); i++) {
635 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
640 status = safe_apic_wait_icr_idle();
642 pr_cont("a previous APIC delivery may have failed\n");
644 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
649 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
650 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
653 case APIC_ICR_RR_VALID:
654 status = apic_read(APIC_RRR);
655 pr_cont("%08x\n", status);
664 * The Multiprocessor Specification 1.4 (1997) example code suggests
665 * that there should be a 10ms delay between the BSP asserting INIT
666 * and de-asserting INIT, when starting a remote processor.
667 * But that slows boot and resume on modern processors, which include
668 * many cores and don't require that delay.
670 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
671 * Modern processor families are quirked to remove the delay entirely.
673 #define UDELAY_10MS_DEFAULT 10000
675 static unsigned int init_udelay = UINT_MAX;
677 static int __init cpu_init_udelay(char *str)
679 get_option(&str, &init_udelay);
683 early_param("cpu_init_udelay", cpu_init_udelay);
685 static void __init smp_quirk_init_udelay(void)
687 /* if cmdline changed it from default, leave it alone */
688 if (init_udelay != UINT_MAX)
691 /* if modern processor, use no delay */
692 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
693 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
697 /* else, use legacy delay */
698 init_udelay = UDELAY_10MS_DEFAULT;
702 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
703 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
704 * won't ... remember to clear down the APIC, etc later.
707 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
709 unsigned long send_status, accept_status = 0;
713 /* Boot on the stack */
714 /* Kick the second */
715 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
717 pr_debug("Waiting for send to finish...\n");
718 send_status = safe_apic_wait_icr_idle();
721 * Give the other CPU some time to accept the IPI.
724 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
725 maxlvt = lapic_get_maxlvt();
726 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
727 apic_write(APIC_ESR, 0);
728 accept_status = (apic_read(APIC_ESR) & 0xEF);
730 pr_debug("NMI sent\n");
733 pr_err("APIC never delivered???\n");
735 pr_err("APIC delivery error (%lx)\n", accept_status);
737 return (send_status | accept_status);
741 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
743 unsigned long send_status = 0, accept_status = 0;
744 int maxlvt, num_starts, j;
746 maxlvt = lapic_get_maxlvt();
749 * Be paranoid about clearing APIC errors.
751 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
753 apic_write(APIC_ESR, 0);
757 pr_debug("Asserting INIT\n");
760 * Turn INIT on target chip
765 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
768 pr_debug("Waiting for send to finish...\n");
769 send_status = safe_apic_wait_icr_idle();
773 pr_debug("Deasserting INIT\n");
777 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
779 pr_debug("Waiting for send to finish...\n");
780 send_status = safe_apic_wait_icr_idle();
785 * Should we send STARTUP IPIs ?
787 * Determine this based on the APIC version.
788 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
790 if (APIC_INTEGRATED(boot_cpu_apic_version))
796 * Run STARTUP IPI loop.
798 pr_debug("#startup loops: %d\n", num_starts);
800 for (j = 1; j <= num_starts; j++) {
801 pr_debug("Sending STARTUP #%d\n", j);
802 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
803 apic_write(APIC_ESR, 0);
805 pr_debug("After apic_write\n");
812 /* Boot on the stack */
813 /* Kick the second */
814 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
818 * Give the other CPU some time to accept the IPI.
820 if (init_udelay == 0)
825 pr_debug("Startup point 1\n");
827 pr_debug("Waiting for send to finish...\n");
828 send_status = safe_apic_wait_icr_idle();
831 * Give the other CPU some time to accept the IPI.
833 if (init_udelay == 0)
838 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
839 apic_write(APIC_ESR, 0);
840 accept_status = (apic_read(APIC_ESR) & 0xEF);
841 if (send_status || accept_status)
844 pr_debug("After Startup\n");
847 pr_err("APIC never delivered???\n");
849 pr_err("APIC delivery error (%lx)\n", accept_status);
851 return (send_status | accept_status);
854 /* reduce the number of lines printed when booting a large cpu count system */
855 static void announce_cpu(int cpu, int apicid)
857 static int current_node = -1;
858 int node = early_cpu_to_node(cpu);
859 static int width, node_width;
862 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
865 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
868 printk(KERN_INFO "x86: Booting SMP configuration:\n");
870 if (system_state == SYSTEM_BOOTING) {
871 if (node != current_node) {
872 if (current_node > (-1))
876 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
877 node_width - num_digits(node), " ", node);
880 /* Add padding for the BSP */
882 pr_cont("%*s", width + 1, " ");
884 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
887 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
891 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
895 cpu = smp_processor_id();
896 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
903 * Wake up AP by INIT, INIT, STARTUP sequence.
905 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
906 * boot-strap code which is not a desired behavior for waking up BSP. To
907 * void the boot-strap code, wake up CPU0 by NMI instead.
909 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
910 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
911 * We'll change this code in the future to wake up hard offlined CPU0 if
912 * real platform and request are available.
915 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
916 int *cpu0_nmi_registered)
924 * Wake up AP by INIT, INIT, STARTUP sequence.
927 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
932 * Wake up BSP by nmi.
934 * Register a NMI handler to help wake up CPU0.
936 boot_error = register_nmi_handler(NMI_LOCAL,
937 wakeup_cpu0_nmi, 0, "wake_cpu0");
940 enable_start_cpu0 = 1;
941 *cpu0_nmi_registered = 1;
942 if (apic->dest_logical == APIC_DEST_LOGICAL)
943 id = cpu0_logical_apicid;
946 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
955 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
957 /* Just in case we booted with a single CPU. */
958 alternatives_enable_smp();
960 per_cpu(current_task, cpu) = idle;
963 /* Stack for startup_32 can be just as for start_secondary onwards */
965 per_cpu(cpu_current_top_of_stack, cpu) =
966 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
968 initial_gs = per_cpu_offset(cpu);
973 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
974 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
975 * Returns zero if CPU booted OK, else error code from
976 * ->wakeup_secondary_cpu.
978 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
980 volatile u32 *trampoline_status =
981 (volatile u32 *) __va(real_mode_header->trampoline_status);
982 /* start_ip had better be page-aligned! */
983 unsigned long start_ip = real_mode_header->trampoline_start;
985 unsigned long boot_error = 0;
986 int cpu0_nmi_registered = 0;
987 unsigned long timeout;
989 idle->thread.sp = (unsigned long)task_pt_regs(idle);
990 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
991 initial_code = (unsigned long)start_secondary;
992 initial_stack = idle->thread.sp;
995 * Enable the espfix hack for this CPU
997 #ifdef CONFIG_X86_ESPFIX64
1001 /* So we see what's up */
1002 announce_cpu(cpu, apicid);
1005 * This grunge runs the startup process for
1006 * the targeted processor.
1009 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1011 pr_debug("Setting warm reset code and vector.\n");
1013 smpboot_setup_warm_reset_vector(start_ip);
1015 * Be paranoid about clearing APIC errors.
1017 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1018 apic_write(APIC_ESR, 0);
1019 apic_read(APIC_ESR);
1024 * AP might wait on cpu_callout_mask in cpu_init() with
1025 * cpu_initialized_mask set if previous attempt to online
1026 * it timed-out. Clear cpu_initialized_mask so that after
1027 * INIT/SIPI it could start with a clean state.
1029 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1033 * Wake up a CPU in difference cases:
1034 * - Use the method in the APIC driver if it's defined
1036 * - Use an INIT boot APIC message for APs or NMI for BSP.
1038 if (apic->wakeup_secondary_cpu)
1039 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1041 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1042 &cpu0_nmi_registered);
1046 * Wait 10s total for first sign of life from AP
1049 timeout = jiffies + 10*HZ;
1050 while (time_before(jiffies, timeout)) {
1051 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1053 * Tell AP to proceed with initialization
1055 cpumask_set_cpu(cpu, cpu_callout_mask);
1065 * Wait till AP completes initial initialization
1067 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1069 * Allow other tasks to run while we wait for the
1070 * AP to come online. This also gives a chance
1071 * for the MTRR work(triggered by the AP coming online)
1072 * to be completed in the stop machine context.
1078 /* mark "stuck" area as not stuck */
1079 *trampoline_status = 0;
1081 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1083 * Cleanup possible dangling ends...
1085 smpboot_restore_warm_reset_vector();
1088 * Clean up the nmi handler. Do this after the callin and callout sync
1089 * to avoid impact of possible long unregister time.
1091 if (cpu0_nmi_registered)
1092 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1097 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1099 int apicid = apic->cpu_present_to_apicid(cpu);
1100 unsigned long flags;
1103 WARN_ON(irqs_disabled());
1105 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1107 if (apicid == BAD_APICID ||
1108 !physid_isset(apicid, phys_cpu_present_map) ||
1109 !apic->apic_id_valid(apicid)) {
1110 pr_err("%s: bad cpu %d\n", __func__, cpu);
1115 * Already booted CPU?
1117 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1118 pr_debug("do_boot_cpu %d Already started\n", cpu);
1123 * Save current MTRR state in case it was changed since early boot
1124 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1128 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1129 err = cpu_check_up_prepare(cpu);
1130 if (err && err != -EBUSY)
1133 /* the FPU context is blank, nobody can own it */
1134 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1136 common_cpu_up(cpu, tidle);
1138 err = do_boot_cpu(apicid, cpu, tidle);
1140 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1145 * Check TSC synchronization with the AP (keep irqs disabled
1148 local_irq_save(flags);
1149 check_tsc_sync_source(cpu);
1150 local_irq_restore(flags);
1152 while (!cpu_online(cpu)) {
1154 touch_nmi_watchdog();
1161 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1163 void arch_disable_smp_support(void)
1165 disable_ioapic_support();
1169 * Fall back to non SMP mode after errors.
1171 * RED-PEN audit/test this more. I bet there is more state messed up here.
1173 static __init void disable_smp(void)
1175 pr_info("SMP disabled\n");
1177 disable_ioapic_support();
1179 init_cpu_present(cpumask_of(0));
1180 init_cpu_possible(cpumask_of(0));
1182 if (smp_found_config)
1183 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1185 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1186 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1187 cpumask_set_cpu(0, topology_core_cpumask(0));
1198 * Various sanity checks.
1200 static int __init smp_sanity_check(unsigned max_cpus)
1204 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1205 if (def_to_bigsmp && nr_cpu_ids > 8) {
1209 pr_warn("More than 8 CPUs detected - skipping them\n"
1210 "Use CONFIG_X86_BIGSMP\n");
1213 for_each_present_cpu(cpu) {
1215 set_cpu_present(cpu, false);
1220 for_each_possible_cpu(cpu) {
1222 set_cpu_possible(cpu, false);
1230 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1231 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1232 hard_smp_processor_id());
1234 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1238 * If we couldn't find an SMP configuration at boot time,
1239 * get out of here now!
1241 if (!smp_found_config && !acpi_lapic) {
1243 pr_notice("SMP motherboard not detected\n");
1244 return SMP_NO_CONFIG;
1248 * Should not be necessary because the MP table should list the boot
1249 * CPU too, but we do it for the sake of robustness anyway.
1251 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1252 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1253 boot_cpu_physical_apicid);
1254 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1259 * If we couldn't find a local APIC, then get out of here now!
1261 if (APIC_INTEGRATED(boot_cpu_apic_version) &&
1262 !boot_cpu_has(X86_FEATURE_APIC)) {
1263 if (!disable_apic) {
1264 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1265 boot_cpu_physical_apicid);
1266 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1272 * If SMP should be disabled, then really disable it!
1275 pr_info("SMP mode deactivated\n");
1276 return SMP_FORCE_UP;
1282 static void __init smp_cpu_index_default(void)
1285 struct cpuinfo_x86 *c;
1287 for_each_possible_cpu(i) {
1289 /* mark all to hotplug */
1290 c->cpu_index = nr_cpu_ids;
1295 * Prepare for SMP bootup. The MP table or ACPI has been read
1296 * earlier. Just do some sanity checking here and enable APIC mode.
1298 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1302 smp_cpu_index_default();
1305 * Setup boot CPU information
1307 smp_store_boot_cpu_info(); /* Final full version of the data */
1308 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1311 for_each_possible_cpu(i) {
1312 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1313 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1314 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1318 * Set 'default' x86 topology, this matches default_topology() in that
1319 * it has NUMA nodes as a topology level. See also
1320 * native_smp_cpus_done().
1322 * Must be done before set_cpus_sibling_map() is ran.
1324 set_sched_topology(x86_topology);
1326 set_cpu_sibling_map(0);
1328 switch (smp_sanity_check(max_cpus)) {
1331 if (APIC_init_uniprocessor())
1332 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1339 apic_bsp_setup(false);
1345 if (read_apic_id() != boot_cpu_physical_apicid) {
1346 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1347 read_apic_id(), boot_cpu_physical_apicid);
1348 /* Or can we switch back to PIC here? */
1351 default_setup_apic_routing();
1352 cpu0_logical_apicid = apic_bsp_setup(false);
1355 print_cpu_info(&cpu_data(0));
1360 set_mtrr_aps_delayed_init();
1362 smp_quirk_init_udelay();
1365 void arch_enable_nonboot_cpus_begin(void)
1367 set_mtrr_aps_delayed_init();
1370 void arch_enable_nonboot_cpus_end(void)
1376 * Early setup to make printk work.
1378 void __init native_smp_prepare_boot_cpu(void)
1380 int me = smp_processor_id();
1381 switch_to_new_gdt(me);
1382 /* already set me in cpu_online_mask in boot_cpu_init() */
1383 cpumask_set_cpu(me, cpu_callout_mask);
1384 cpu_set_state_online(me);
1387 void __init native_smp_cpus_done(unsigned int max_cpus)
1389 pr_debug("Boot done\n");
1391 if (x86_has_numa_in_package)
1392 set_sched_topology(x86_numa_in_package_topology);
1396 setup_ioapic_dest();
1400 static int __initdata setup_possible_cpus = -1;
1401 static int __init _setup_possible_cpus(char *str)
1403 get_option(&str, &setup_possible_cpus);
1406 early_param("possible_cpus", _setup_possible_cpus);
1410 * cpu_possible_mask should be static, it cannot change as cpu's
1411 * are onlined, or offlined. The reason is per-cpu data-structures
1412 * are allocated by some modules at init time, and dont expect to
1413 * do this dynamically on cpu arrival/departure.
1414 * cpu_present_mask on the other hand can change dynamically.
1415 * In case when cpu_hotplug is not compiled, then we resort to current
1416 * behaviour, which is cpu_possible == cpu_present.
1419 * Three ways to find out the number of additional hotplug CPUs:
1420 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1421 * - The user can overwrite it with possible_cpus=NUM
1422 * - Otherwise don't reserve additional CPUs.
1423 * We do this because additional CPUs waste a lot of memory.
1426 __init void prefill_possible_map(void)
1430 /* No boot processor was found in mptable or ACPI MADT */
1431 if (!num_processors) {
1432 if (boot_cpu_has(X86_FEATURE_APIC)) {
1433 int apicid = boot_cpu_physical_apicid;
1434 int cpu = hard_smp_processor_id();
1436 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1438 /* Make sure boot cpu is enumerated */
1439 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1440 apic->apic_id_valid(apicid))
1441 generic_processor_info(apicid, boot_cpu_apic_version);
1444 if (!num_processors)
1448 i = setup_max_cpus ?: 1;
1449 if (setup_possible_cpus == -1) {
1450 possible = num_processors;
1451 #ifdef CONFIG_HOTPLUG_CPU
1453 possible += disabled_cpus;
1459 possible = setup_possible_cpus;
1461 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1463 /* nr_cpu_ids could be reduced via nr_cpus= */
1464 if (possible > nr_cpu_ids) {
1465 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1466 possible, nr_cpu_ids);
1467 possible = nr_cpu_ids;
1470 #ifdef CONFIG_HOTPLUG_CPU
1471 if (!setup_max_cpus)
1474 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1475 possible, setup_max_cpus);
1479 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1480 possible, max_t(int, possible - num_processors, 0));
1482 for (i = 0; i < possible; i++)
1483 set_cpu_possible(i, true);
1484 for (; i < NR_CPUS; i++)
1485 set_cpu_possible(i, false);
1487 nr_cpu_ids = possible;
1490 #ifdef CONFIG_HOTPLUG_CPU
1492 /* Recompute SMT state for all CPUs on offline */
1493 static void recompute_smt_state(void)
1495 int max_threads, cpu;
1498 for_each_online_cpu (cpu) {
1499 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1501 if (threads > max_threads)
1502 max_threads = threads;
1504 __max_smt_threads = max_threads;
1507 static void remove_siblinginfo(int cpu)
1510 struct cpuinfo_x86 *c = &cpu_data(cpu);
1512 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1513 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1515 * last thread sibling in this cpu core going down
1517 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1518 cpu_data(sibling).booted_cores--;
1521 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1522 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1523 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1524 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1525 cpumask_clear(cpu_llc_shared_mask(cpu));
1526 cpumask_clear(topology_sibling_cpumask(cpu));
1527 cpumask_clear(topology_core_cpumask(cpu));
1528 c->phys_proc_id = 0;
1530 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1531 recompute_smt_state();
1534 static void remove_cpu_from_maps(int cpu)
1536 set_cpu_online(cpu, false);
1537 cpumask_clear_cpu(cpu, cpu_callout_mask);
1538 cpumask_clear_cpu(cpu, cpu_callin_mask);
1539 /* was set by cpu_init() */
1540 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1541 numa_remove_cpu(cpu);
1544 void cpu_disable_common(void)
1546 int cpu = smp_processor_id();
1548 remove_siblinginfo(cpu);
1550 /* It's now safe to remove this processor from the online map */
1552 remove_cpu_from_maps(cpu);
1553 unlock_vector_lock();
1557 int native_cpu_disable(void)
1561 ret = check_irq_vectors_for_cpu_disable();
1566 cpu_disable_common();
1571 int common_cpu_die(unsigned int cpu)
1575 /* We don't do anything here: idle task is faking death itself. */
1577 /* They ack this in play_dead() by setting CPU_DEAD */
1578 if (cpu_wait_death(cpu, 5)) {
1579 if (system_state == SYSTEM_RUNNING)
1580 pr_info("CPU %u is now offline\n", cpu);
1582 pr_err("CPU %u didn't die...\n", cpu);
1589 void native_cpu_die(unsigned int cpu)
1591 common_cpu_die(cpu);
1594 void play_dead_common(void)
1597 reset_lazy_tlbstate();
1600 (void)cpu_report_death();
1603 * With physical CPU hotplug, we should halt the cpu
1605 local_irq_disable();
1608 static bool wakeup_cpu0(void)
1610 if (smp_processor_id() == 0 && enable_start_cpu0)
1617 * We need to flush the caches before going to sleep, lest we have
1618 * dirty data in our caches when we come back up.
1620 static inline void mwait_play_dead(void)
1622 unsigned int eax, ebx, ecx, edx;
1623 unsigned int highest_cstate = 0;
1624 unsigned int highest_subcstate = 0;
1628 if (!this_cpu_has(X86_FEATURE_MWAIT))
1630 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1632 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1635 eax = CPUID_MWAIT_LEAF;
1637 native_cpuid(&eax, &ebx, &ecx, &edx);
1640 * eax will be 0 if EDX enumeration is not valid.
1641 * Initialized below to cstate, sub_cstate value when EDX is valid.
1643 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1646 edx >>= MWAIT_SUBSTATE_SIZE;
1647 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1648 if (edx & MWAIT_SUBSTATE_MASK) {
1650 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1653 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1654 (highest_subcstate - 1);
1658 * This should be a memory location in a cache line which is
1659 * unlikely to be touched by other processors. The actual
1660 * content is immaterial as it is not actually modified in any way.
1662 mwait_ptr = ¤t_thread_info()->flags;
1668 * The CLFLUSH is a workaround for erratum AAI65 for
1669 * the Xeon 7400 series. It's not clear it is actually
1670 * needed, but it should be harmless in either case.
1671 * The WBINVD is insufficient due to the spurious-wakeup
1672 * case where we return around the loop.
1677 __monitor(mwait_ptr, 0, 0);
1681 * If NMI wants to wake up CPU0, start CPU0.
1688 void hlt_play_dead(void)
1690 if (__this_cpu_read(cpu_info.x86) >= 4)
1696 * If NMI wants to wake up CPU0, start CPU0.
1703 void native_play_dead(void)
1706 tboot_shutdown(TB_SHUTDOWN_WFS);
1708 mwait_play_dead(); /* Only returns on failure */
1709 if (cpuidle_play_dead())
1713 #else /* ... !CONFIG_HOTPLUG_CPU */
1714 int native_cpu_disable(void)
1719 void native_cpu_die(unsigned int cpu)
1721 /* We said "no" in __cpu_disable */
1725 void native_play_dead(void)