2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
77 #include <asm/smpboot_hooks.h>
78 #include <asm/i8259.h>
80 #include <asm/realmode.h>
82 /* State of each CPU */
83 DEFINE_PER_CPU(int, cpu_state) = { 0 };
85 #ifdef CONFIG_HOTPLUG_CPU
87 * We need this for trampoline_base protection from concurrent accesses when
88 * off- and onlining cores wildly.
90 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
92 void cpu_hotplug_driver_lock(void)
94 mutex_lock(&x86_cpu_hotplug_driver_mutex);
97 void cpu_hotplug_driver_unlock(void)
99 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
102 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
103 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
106 /* Number of siblings per CPU package */
107 int smp_num_siblings = 1;
108 EXPORT_SYMBOL(smp_num_siblings);
110 /* Last level cache ID of each logical CPU */
111 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
113 /* representing HT siblings of each logical CPU */
114 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
115 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
117 /* representing HT and core siblings of each logical CPU */
118 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
119 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
121 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
123 /* Per CPU bogomips and other parameters */
124 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
125 EXPORT_PER_CPU_SYMBOL(cpu_info);
127 atomic_t init_deasserted;
130 * Report back to the Boot Processor during boot time or to the caller processor
133 static void smp_callin(void)
136 unsigned long timeout;
139 * If waken up by an INIT in an 82489DX configuration
140 * we may get here before an INIT-deassert IPI reaches
141 * our local APIC. We have to wait for the IPI or we'll
142 * lock up on an APIC access.
144 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
146 cpuid = smp_processor_id();
147 if (apic->wait_for_init_deassert && cpuid != 0)
148 apic->wait_for_init_deassert(&init_deasserted);
151 * (This works even if the APIC is not enabled.)
153 phys_id = read_apic_id();
154 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
155 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
158 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
161 * STARTUP IPIs are fragile beasts as they might sometimes
162 * trigger some glue motherboard logic. Complete APIC bus
163 * silence for 1 second, this overestimates the time the
164 * boot CPU is spending to send the up to 2 STARTUP IPIs
165 * by a factor of two. This should be enough.
169 * Waiting 2s total for startup (udelay is not yet working)
171 timeout = jiffies + 2*HZ;
172 while (time_before(jiffies, timeout)) {
174 * Has the boot CPU finished it's STARTUP sequence?
176 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
181 if (!time_before(jiffies, timeout)) {
182 panic("%s: CPU%d started up but did not get a callout!\n",
187 * the boot CPU has finished the init stage and is spinning
188 * on callin_map until we finish. We are free to set up this
189 * CPU, first the APIC. (this is probably redundant on most
193 pr_debug("CALLIN, before setup_local_APIC()\n");
194 if (apic->smp_callin_clear_local_apic)
195 apic->smp_callin_clear_local_apic();
197 end_local_APIC_setup();
200 * Need to setup vector mappings before we enable interrupts.
202 setup_vector_irq(smp_processor_id());
205 * Save our processor parameters. Note: this information
206 * is needed for clock calibration.
208 smp_store_cpu_info(cpuid);
212 * Update loops_per_jiffy in cpu_data. Previous call to
213 * smp_store_cpu_info() stored a value that is close but not as
214 * accurate as the value just calculated.
217 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
218 pr_debug("Stack at about %p\n", &cpuid);
221 * This must be done before setting cpu_online_mask
222 * or calling notify_cpu_starting.
224 set_cpu_sibling_map(raw_smp_processor_id());
227 notify_cpu_starting(cpuid);
230 * Allow the master to continue.
232 cpumask_set_cpu(cpuid, cpu_callin_mask);
235 static int cpu0_logical_apicid;
236 static int enable_start_cpu0;
238 * Activate a secondary processor.
240 static void notrace start_secondary(void *unused)
243 * Don't put *anything* before cpu_init(), SMP booting is too
244 * fragile that we want to limit the things done here to the
245 * most necessary things.
248 x86_cpuinit.early_percpu_clock_init();
252 enable_start_cpu0 = 0;
255 /* switch away from the initial page table */
256 load_cr3(swapper_pg_dir);
260 /* otherwise gcc will move up smp_processor_id before the cpu_init */
263 * Check TSC synchronization with the BP:
265 check_tsc_sync_target();
268 * We need to hold vector_lock so there the set of online cpus
269 * does not change while we are assigning vectors to cpus. Holding
270 * this lock ensures we don't half assign or remove an irq from a cpu.
273 set_cpu_online(smp_processor_id(), true);
274 unlock_vector_lock();
275 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
276 x86_platform.nmi_init();
278 /* enable local interrupts */
281 /* to prevent fake stack check failure in clock setup */
282 boot_init_stack_canary();
284 x86_cpuinit.setup_percpu_clockev();
287 cpu_startup_entry(CPUHP_ONLINE);
290 void __init smp_store_boot_cpu_info(void)
292 int id = 0; /* CPU 0 */
293 struct cpuinfo_x86 *c = &cpu_data(id);
300 * The bootstrap kernel entry code has set these up. Save them for
303 void smp_store_cpu_info(int id)
305 struct cpuinfo_x86 *c = &cpu_data(id);
310 * During boot time, CPU0 has this setup already. Save the info when
311 * bringing up AP or offlined CPU0.
313 identify_secondary_cpu(c);
317 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
319 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
321 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
322 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
323 "[node: %d != %d]. Ignoring dependency.\n",
324 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
327 #define link_mask(_m, c1, c2) \
329 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
330 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
333 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
335 if (cpu_has_topoext) {
336 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
338 if (c->phys_proc_id == o->phys_proc_id &&
339 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
340 c->compute_unit_id == o->compute_unit_id)
341 return topology_sane(c, o, "smt");
343 } else if (c->phys_proc_id == o->phys_proc_id &&
344 c->cpu_core_id == o->cpu_core_id) {
345 return topology_sane(c, o, "smt");
351 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
353 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
355 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
356 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
357 return topology_sane(c, o, "llc");
362 static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
364 if (c->phys_proc_id == o->phys_proc_id) {
365 if (cpu_has(c, X86_FEATURE_AMD_DCM))
368 return topology_sane(c, o, "mc");
373 void set_cpu_sibling_map(int cpu)
375 bool has_smt = smp_num_siblings > 1;
376 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
377 struct cpuinfo_x86 *c = &cpu_data(cpu);
378 struct cpuinfo_x86 *o;
381 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
384 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
385 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
386 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
391 for_each_cpu(i, cpu_sibling_setup_mask) {
394 if ((i == cpu) || (has_smt && match_smt(c, o)))
395 link_mask(sibling, cpu, i);
397 if ((i == cpu) || (has_mp && match_llc(c, o)))
398 link_mask(llc_shared, cpu, i);
403 * This needs a separate iteration over the cpus because we rely on all
404 * cpu_sibling_mask links to be set-up.
406 for_each_cpu(i, cpu_sibling_setup_mask) {
409 if ((i == cpu) || (has_mp && match_mc(c, o))) {
410 link_mask(core, cpu, i);
413 * Does this new cpu bringup a new core?
415 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
417 * for each core in package, increment
418 * the booted_cores for this new cpu
420 if (cpumask_first(cpu_sibling_mask(i)) == i)
423 * increment the core count for all
424 * the other cpus in this package
427 cpu_data(i).booted_cores++;
428 } else if (i != cpu && !c->booted_cores)
429 c->booted_cores = cpu_data(i).booted_cores;
434 /* maps the cpu to the sched domain representing multi-core */
435 const struct cpumask *cpu_coregroup_mask(int cpu)
437 return cpu_llc_shared_mask(cpu);
440 static void impress_friends(void)
443 unsigned long bogosum = 0;
445 * Allow the user to impress friends.
447 pr_debug("Before bogomips\n");
448 for_each_possible_cpu(cpu)
449 if (cpumask_test_cpu(cpu, cpu_callout_mask))
450 bogosum += cpu_data(cpu).loops_per_jiffy;
451 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
454 (bogosum/(5000/HZ))%100);
456 pr_debug("Before bogocount - setting activated=1\n");
459 void __inquire_remote_apic(int apicid)
461 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
462 const char * const names[] = { "ID", "VERSION", "SPIV" };
466 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
468 for (i = 0; i < ARRAY_SIZE(regs); i++) {
469 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
474 status = safe_apic_wait_icr_idle();
476 pr_cont("a previous APIC delivery may have failed\n");
478 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
483 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
484 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
487 case APIC_ICR_RR_VALID:
488 status = apic_read(APIC_RRR);
489 pr_cont("%08x\n", status);
498 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
499 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
500 * won't ... remember to clear down the APIC, etc later.
503 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
505 unsigned long send_status, accept_status = 0;
509 /* Boot on the stack */
510 /* Kick the second */
511 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
513 pr_debug("Waiting for send to finish...\n");
514 send_status = safe_apic_wait_icr_idle();
517 * Give the other CPU some time to accept the IPI.
520 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
521 maxlvt = lapic_get_maxlvt();
522 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
523 apic_write(APIC_ESR, 0);
524 accept_status = (apic_read(APIC_ESR) & 0xEF);
526 pr_debug("NMI sent\n");
529 pr_err("APIC never delivered???\n");
531 pr_err("APIC delivery error (%lx)\n", accept_status);
533 return (send_status | accept_status);
537 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
539 unsigned long send_status, accept_status = 0;
540 int maxlvt, num_starts, j;
542 maxlvt = lapic_get_maxlvt();
545 * Be paranoid about clearing APIC errors.
547 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
548 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
549 apic_write(APIC_ESR, 0);
553 pr_debug("Asserting INIT\n");
556 * Turn INIT on target chip
561 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
564 pr_debug("Waiting for send to finish...\n");
565 send_status = safe_apic_wait_icr_idle();
569 pr_debug("Deasserting INIT\n");
573 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
575 pr_debug("Waiting for send to finish...\n");
576 send_status = safe_apic_wait_icr_idle();
579 atomic_set(&init_deasserted, 1);
582 * Should we send STARTUP IPIs ?
584 * Determine this based on the APIC version.
585 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
587 if (APIC_INTEGRATED(apic_version[phys_apicid]))
593 * Paravirt / VMI wants a startup IPI hook here to set up the
594 * target processor state.
596 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
600 * Run STARTUP IPI loop.
602 pr_debug("#startup loops: %d\n", num_starts);
604 for (j = 1; j <= num_starts; j++) {
605 pr_debug("Sending STARTUP #%d\n", j);
606 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
607 apic_write(APIC_ESR, 0);
609 pr_debug("After apic_write\n");
616 /* Boot on the stack */
617 /* Kick the second */
618 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
622 * Give the other CPU some time to accept the IPI.
626 pr_debug("Startup point 1\n");
628 pr_debug("Waiting for send to finish...\n");
629 send_status = safe_apic_wait_icr_idle();
632 * Give the other CPU some time to accept the IPI.
635 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
636 apic_write(APIC_ESR, 0);
637 accept_status = (apic_read(APIC_ESR) & 0xEF);
638 if (send_status || accept_status)
641 pr_debug("After Startup\n");
644 pr_err("APIC never delivered???\n");
646 pr_err("APIC delivery error (%lx)\n", accept_status);
648 return (send_status | accept_status);
651 /* reduce the number of lines printed when booting a large cpu count system */
652 static void announce_cpu(int cpu, int apicid)
654 static int current_node = -1;
655 int node = early_cpu_to_node(cpu);
656 int max_cpu_present = find_last_bit(cpumask_bits(cpu_present_mask), NR_CPUS);
658 if (system_state == SYSTEM_BOOTING) {
659 if (node != current_node) {
660 if (current_node > (-1))
663 pr_info("Booting Node %3d, Processors ", node);
665 pr_cont(" #%4d%s", cpu, cpu == max_cpu_present ? " OK\n" : "");
668 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
672 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
676 cpu = smp_processor_id();
677 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
684 * Wake up AP by INIT, INIT, STARTUP sequence.
686 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
687 * boot-strap code which is not a desired behavior for waking up BSP. To
688 * void the boot-strap code, wake up CPU0 by NMI instead.
690 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
691 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
692 * We'll change this code in the future to wake up hard offlined CPU0 if
693 * real platform and request are available.
696 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
697 int *cpu0_nmi_registered)
703 * Wake up AP by INIT, INIT, STARTUP sequence.
706 return wakeup_secondary_cpu_via_init(apicid, start_ip);
709 * Wake up BSP by nmi.
711 * Register a NMI handler to help wake up CPU0.
713 boot_error = register_nmi_handler(NMI_LOCAL,
714 wakeup_cpu0_nmi, 0, "wake_cpu0");
717 enable_start_cpu0 = 1;
718 *cpu0_nmi_registered = 1;
719 if (apic->dest_logical == APIC_DEST_LOGICAL)
720 id = cpu0_logical_apicid;
723 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
730 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
731 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
732 * Returns zero if CPU booted OK, else error code from
733 * ->wakeup_secondary_cpu.
735 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
737 volatile u32 *trampoline_status =
738 (volatile u32 *) __va(real_mode_header->trampoline_status);
739 /* start_ip had better be page-aligned! */
740 unsigned long start_ip = real_mode_header->trampoline_start;
742 unsigned long boot_error = 0;
744 int cpu0_nmi_registered = 0;
746 /* Just in case we booted with a single CPU. */
747 alternatives_enable_smp();
749 idle->thread.sp = (unsigned long) (((struct pt_regs *)
750 (THREAD_SIZE + task_stack_page(idle))) - 1);
751 per_cpu(current_task, cpu) = idle;
754 /* Stack for startup_32 can be just as for start_secondary onwards */
757 clear_tsk_thread_flag(idle, TIF_FORK);
758 initial_gs = per_cpu_offset(cpu);
759 per_cpu(kernel_stack, cpu) =
760 (unsigned long)task_stack_page(idle) -
761 KERNEL_STACK_OFFSET + THREAD_SIZE;
763 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
764 initial_code = (unsigned long)start_secondary;
765 stack_start = idle->thread.sp;
767 /* So we see what's up */
768 announce_cpu(cpu, apicid);
771 * This grunge runs the startup process for
772 * the targeted processor.
775 atomic_set(&init_deasserted, 0);
777 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
779 pr_debug("Setting warm reset code and vector.\n");
781 smpboot_setup_warm_reset_vector(start_ip);
783 * Be paranoid about clearing APIC errors.
785 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
786 apic_write(APIC_ESR, 0);
792 * Wake up a CPU in difference cases:
793 * - Use the method in the APIC driver if it's defined
795 * - Use an INIT boot APIC message for APs or NMI for BSP.
797 if (apic->wakeup_secondary_cpu)
798 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
800 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
801 &cpu0_nmi_registered);
805 * allow APs to start initializing.
807 pr_debug("Before Callout %d\n", cpu);
808 cpumask_set_cpu(cpu, cpu_callout_mask);
809 pr_debug("After Callout %d\n", cpu);
812 * Wait 5s total for a response
814 for (timeout = 0; timeout < 50000; timeout++) {
815 if (cpumask_test_cpu(cpu, cpu_callin_mask))
816 break; /* It has booted */
819 * Allow other tasks to run while we wait for the
820 * AP to come online. This also gives a chance
821 * for the MTRR work(triggered by the AP coming online)
822 * to be completed in the stop machine context.
827 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
828 print_cpu_msr(&cpu_data(cpu));
829 pr_debug("CPU%d: has booted.\n", cpu);
832 if (*trampoline_status == 0xA5A5A5A5)
833 /* trampoline started but...? */
834 pr_err("CPU%d: Stuck ??\n", cpu);
836 /* trampoline code not run */
837 pr_err("CPU%d: Not responding\n", cpu);
838 if (apic->inquire_remote_apic)
839 apic->inquire_remote_apic(apicid);
844 /* Try to put things back the way they were before ... */
845 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
847 /* was set by do_boot_cpu() */
848 cpumask_clear_cpu(cpu, cpu_callout_mask);
850 /* was set by cpu_init() */
851 cpumask_clear_cpu(cpu, cpu_initialized_mask);
853 set_cpu_present(cpu, false);
854 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
857 /* mark "stuck" area as not stuck */
858 *trampoline_status = 0;
860 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
862 * Cleanup possible dangling ends...
864 smpboot_restore_warm_reset_vector();
867 * Clean up the nmi handler. Do this after the callin and callout sync
868 * to avoid impact of possible long unregister time.
870 if (cpu0_nmi_registered)
871 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
876 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
878 int apicid = apic->cpu_present_to_apicid(cpu);
882 WARN_ON(irqs_disabled());
884 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
886 if (apicid == BAD_APICID ||
887 !physid_isset(apicid, phys_cpu_present_map) ||
888 !apic->apic_id_valid(apicid)) {
889 pr_err("%s: bad cpu %d\n", __func__, cpu);
894 * Already booted CPU?
896 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
897 pr_debug("do_boot_cpu %d Already started\n", cpu);
902 * Save current MTRR state in case it was changed since early boot
903 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
907 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
909 /* the FPU context is blank, nobody can own it */
910 __cpu_disable_lazy_restore(cpu);
912 err = do_boot_cpu(apicid, cpu, tidle);
914 pr_debug("do_boot_cpu failed %d\n", err);
919 * Check TSC synchronization with the AP (keep irqs disabled
922 local_irq_save(flags);
923 check_tsc_sync_source(cpu);
924 local_irq_restore(flags);
926 while (!cpu_online(cpu)) {
928 touch_nmi_watchdog();
935 * arch_disable_smp_support() - disables SMP support for x86 at runtime
937 void arch_disable_smp_support(void)
939 disable_ioapic_support();
943 * Fall back to non SMP mode after errors.
945 * RED-PEN audit/test this more. I bet there is more state messed up here.
947 static __init void disable_smp(void)
949 init_cpu_present(cpumask_of(0));
950 init_cpu_possible(cpumask_of(0));
951 smpboot_clear_io_apic_irqs();
953 if (smp_found_config)
954 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
956 physid_set_mask_of_physid(0, &phys_cpu_present_map);
957 cpumask_set_cpu(0, cpu_sibling_mask(0));
958 cpumask_set_cpu(0, cpu_core_mask(0));
962 * Various sanity checks.
964 static int __init smp_sanity_check(unsigned max_cpus)
968 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
969 if (def_to_bigsmp && nr_cpu_ids > 8) {
973 pr_warn("More than 8 CPUs detected - skipping them\n"
974 "Use CONFIG_X86_BIGSMP\n");
977 for_each_present_cpu(cpu) {
979 set_cpu_present(cpu, false);
984 for_each_possible_cpu(cpu) {
986 set_cpu_possible(cpu, false);
994 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
995 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
996 hard_smp_processor_id());
998 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1002 * If we couldn't find an SMP configuration at boot time,
1003 * get out of here now!
1005 if (!smp_found_config && !acpi_lapic) {
1007 pr_notice("SMP motherboard not detected\n");
1009 if (APIC_init_uniprocessor())
1010 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1015 * Should not be necessary because the MP table should list the boot
1016 * CPU too, but we do it for the sake of robustness anyway.
1018 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1019 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1020 boot_cpu_physical_apicid);
1021 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1026 * If we couldn't find a local APIC, then get out of here now!
1028 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1030 if (!disable_apic) {
1031 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1032 boot_cpu_physical_apicid);
1033 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1035 smpboot_clear_io_apic();
1036 disable_ioapic_support();
1040 verify_local_APIC();
1043 * If SMP should be disabled, then really disable it!
1046 pr_info("SMP mode deactivated\n");
1047 smpboot_clear_io_apic();
1051 bsp_end_local_APIC_setup();
1058 static void __init smp_cpu_index_default(void)
1061 struct cpuinfo_x86 *c;
1063 for_each_possible_cpu(i) {
1065 /* mark all to hotplug */
1066 c->cpu_index = nr_cpu_ids;
1071 * Prepare for SMP bootup. The MP table or ACPI has been read
1072 * earlier. Just do some sanity checking here and enable APIC mode.
1074 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1079 smp_cpu_index_default();
1082 * Setup boot CPU information
1084 smp_store_boot_cpu_info(); /* Final full version of the data */
1085 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1088 current_thread_info()->cpu = 0; /* needed? */
1089 for_each_possible_cpu(i) {
1090 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1091 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1092 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1094 set_cpu_sibling_map(0);
1097 if (smp_sanity_check(max_cpus) < 0) {
1098 pr_info("SMP disabled\n");
1103 default_setup_apic_routing();
1106 if (read_apic_id() != boot_cpu_physical_apicid) {
1107 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1108 read_apic_id(), boot_cpu_physical_apicid);
1109 /* Or can we switch back to PIC here? */
1116 * Switch from PIC to APIC mode.
1121 cpu0_logical_apicid = apic_read(APIC_LDR);
1123 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1126 * Enable IO APIC before setting up error vector
1128 if (!skip_ioapic_setup && nr_ioapics)
1131 bsp_end_local_APIC_setup();
1133 if (apic->setup_portio_remap)
1134 apic->setup_portio_remap();
1136 smpboot_setup_io_apic();
1138 * Set up local APIC timer on boot CPU.
1141 pr_info("CPU%d: ", 0);
1142 print_cpu_info(&cpu_data(0));
1143 x86_init.timers.setup_percpu_clockev();
1148 set_mtrr_aps_delayed_init();
1153 void arch_enable_nonboot_cpus_begin(void)
1155 set_mtrr_aps_delayed_init();
1158 void arch_enable_nonboot_cpus_end(void)
1164 * Early setup to make printk work.
1166 void __init native_smp_prepare_boot_cpu(void)
1168 int me = smp_processor_id();
1169 switch_to_new_gdt(me);
1170 /* already set me in cpu_online_mask in boot_cpu_init() */
1171 cpumask_set_cpu(me, cpu_callout_mask);
1172 per_cpu(cpu_state, me) = CPU_ONLINE;
1175 void __init native_smp_cpus_done(unsigned int max_cpus)
1177 pr_debug("Boot done\n");
1181 #ifdef CONFIG_X86_IO_APIC
1182 setup_ioapic_dest();
1187 static int __initdata setup_possible_cpus = -1;
1188 static int __init _setup_possible_cpus(char *str)
1190 get_option(&str, &setup_possible_cpus);
1193 early_param("possible_cpus", _setup_possible_cpus);
1197 * cpu_possible_mask should be static, it cannot change as cpu's
1198 * are onlined, or offlined. The reason is per-cpu data-structures
1199 * are allocated by some modules at init time, and dont expect to
1200 * do this dynamically on cpu arrival/departure.
1201 * cpu_present_mask on the other hand can change dynamically.
1202 * In case when cpu_hotplug is not compiled, then we resort to current
1203 * behaviour, which is cpu_possible == cpu_present.
1206 * Three ways to find out the number of additional hotplug CPUs:
1207 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1208 * - The user can overwrite it with possible_cpus=NUM
1209 * - Otherwise don't reserve additional CPUs.
1210 * We do this because additional CPUs waste a lot of memory.
1213 __init void prefill_possible_map(void)
1217 /* no processor from mptable or madt */
1218 if (!num_processors)
1221 i = setup_max_cpus ?: 1;
1222 if (setup_possible_cpus == -1) {
1223 possible = num_processors;
1224 #ifdef CONFIG_HOTPLUG_CPU
1226 possible += disabled_cpus;
1232 possible = setup_possible_cpus;
1234 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1236 /* nr_cpu_ids could be reduced via nr_cpus= */
1237 if (possible > nr_cpu_ids) {
1238 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1239 possible, nr_cpu_ids);
1240 possible = nr_cpu_ids;
1243 #ifdef CONFIG_HOTPLUG_CPU
1244 if (!setup_max_cpus)
1247 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1248 possible, setup_max_cpus);
1252 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1253 possible, max_t(int, possible - num_processors, 0));
1255 for (i = 0; i < possible; i++)
1256 set_cpu_possible(i, true);
1257 for (; i < NR_CPUS; i++)
1258 set_cpu_possible(i, false);
1260 nr_cpu_ids = possible;
1263 #ifdef CONFIG_HOTPLUG_CPU
1265 static void remove_siblinginfo(int cpu)
1268 struct cpuinfo_x86 *c = &cpu_data(cpu);
1270 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1271 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1273 * last thread sibling in this cpu core going down
1275 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1276 cpu_data(sibling).booted_cores--;
1279 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1280 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1281 cpumask_clear(cpu_sibling_mask(cpu));
1282 cpumask_clear(cpu_core_mask(cpu));
1283 c->phys_proc_id = 0;
1285 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1288 static void __ref remove_cpu_from_maps(int cpu)
1290 set_cpu_online(cpu, false);
1291 cpumask_clear_cpu(cpu, cpu_callout_mask);
1292 cpumask_clear_cpu(cpu, cpu_callin_mask);
1293 /* was set by cpu_init() */
1294 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1295 numa_remove_cpu(cpu);
1298 void cpu_disable_common(void)
1300 int cpu = smp_processor_id();
1302 remove_siblinginfo(cpu);
1304 /* It's now safe to remove this processor from the online map */
1306 remove_cpu_from_maps(cpu);
1307 unlock_vector_lock();
1311 int native_cpu_disable(void)
1315 cpu_disable_common();
1319 void native_cpu_die(unsigned int cpu)
1321 /* We don't do anything here: idle task is faking death itself. */
1324 for (i = 0; i < 10; i++) {
1325 /* They ack this in play_dead by setting CPU_DEAD */
1326 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1327 if (system_state == SYSTEM_RUNNING)
1328 pr_info("CPU %u is now offline\n", cpu);
1333 pr_err("CPU %u didn't die...\n", cpu);
1336 void play_dead_common(void)
1339 reset_lazy_tlbstate();
1340 amd_e400_remove_cpu(raw_smp_processor_id());
1344 __this_cpu_write(cpu_state, CPU_DEAD);
1347 * With physical CPU hotplug, we should halt the cpu
1349 local_irq_disable();
1352 static bool wakeup_cpu0(void)
1354 if (smp_processor_id() == 0 && enable_start_cpu0)
1361 * We need to flush the caches before going to sleep, lest we have
1362 * dirty data in our caches when we come back up.
1364 static inline void mwait_play_dead(void)
1366 unsigned int eax, ebx, ecx, edx;
1367 unsigned int highest_cstate = 0;
1368 unsigned int highest_subcstate = 0;
1372 if (!this_cpu_has(X86_FEATURE_MWAIT))
1374 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1376 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1379 eax = CPUID_MWAIT_LEAF;
1381 native_cpuid(&eax, &ebx, &ecx, &edx);
1384 * eax will be 0 if EDX enumeration is not valid.
1385 * Initialized below to cstate, sub_cstate value when EDX is valid.
1387 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1390 edx >>= MWAIT_SUBSTATE_SIZE;
1391 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1392 if (edx & MWAIT_SUBSTATE_MASK) {
1394 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1397 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1398 (highest_subcstate - 1);
1402 * This should be a memory location in a cache line which is
1403 * unlikely to be touched by other processors. The actual
1404 * content is immaterial as it is not actually modified in any way.
1406 mwait_ptr = ¤t_thread_info()->flags;
1412 * The CLFLUSH is a workaround for erratum AAI65 for
1413 * the Xeon 7400 series. It's not clear it is actually
1414 * needed, but it should be harmless in either case.
1415 * The WBINVD is insufficient due to the spurious-wakeup
1416 * case where we return around the loop.
1419 __monitor(mwait_ptr, 0, 0);
1423 * If NMI wants to wake up CPU0, start CPU0.
1430 static inline void hlt_play_dead(void)
1432 if (__this_cpu_read(cpu_info.x86) >= 4)
1438 * If NMI wants to wake up CPU0, start CPU0.
1445 void native_play_dead(void)
1448 tboot_shutdown(TB_SHUTDOWN_WFS);
1450 mwait_play_dead(); /* Only returns on failure */
1451 if (cpuidle_play_dead())
1455 #else /* ... !CONFIG_HOTPLUG_CPU */
1456 int native_cpu_disable(void)
1461 void native_cpu_die(unsigned int cpu)
1463 /* We said "no" in __cpu_disable */
1467 void native_play_dead(void)