2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
77 #include <asm/realmode.h>
80 /* State of each CPU */
81 DEFINE_PER_CPU(int, cpu_state) = { 0 };
83 /* Number of siblings per CPU package */
84 int smp_num_siblings = 1;
85 EXPORT_SYMBOL(smp_num_siblings);
87 /* Last level cache ID of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
90 /* representing HT siblings of each logical CPU */
91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
94 /* representing HT and core siblings of each logical CPU */
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
96 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
98 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
100 /* Per CPU bogomips and other parameters */
101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
102 EXPORT_PER_CPU_SYMBOL(cpu_info);
104 atomic_t init_deasserted;
106 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
110 spin_lock_irqsave(&rtc_lock, flags);
111 CMOS_WRITE(0xa, 0xf);
112 spin_unlock_irqrestore(&rtc_lock, flags);
115 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
118 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
123 static inline void smpboot_restore_warm_reset_vector(void)
128 * Install writable page 0 entry to set BIOS data area.
133 * Paranoid: Set warm reset code and vector here back
136 spin_lock_irqsave(&rtc_lock, flags);
138 spin_unlock_irqrestore(&rtc_lock, flags);
140 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
144 * Report back to the Boot Processor during boot time or to the caller processor
147 static void smp_callin(void)
152 * If waken up by an INIT in an 82489DX configuration
153 * we may get here before an INIT-deassert IPI reaches
154 * our local APIC. We have to wait for the IPI or we'll
155 * lock up on an APIC access.
157 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
159 cpuid = smp_processor_id();
160 if (apic->wait_for_init_deassert && cpuid)
161 while (!atomic_read(&init_deasserted))
165 * (This works even if the APIC is not enabled.)
167 phys_id = read_apic_id();
170 * the boot CPU has finished the init stage and is spinning
171 * on callin_map until we finish. We are free to set up this
172 * CPU, first the APIC. (this is probably redundant on most
176 end_local_APIC_setup();
179 * Need to setup vector mappings before we enable interrupts.
181 setup_vector_irq(smp_processor_id());
184 * Save our processor parameters. Note: this information
185 * is needed for clock calibration.
187 smp_store_cpu_info(cpuid);
191 * Update loops_per_jiffy in cpu_data. Previous call to
192 * smp_store_cpu_info() stored a value that is close but not as
193 * accurate as the value just calculated.
196 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
197 pr_debug("Stack at about %p\n", &cpuid);
200 * This must be done before setting cpu_online_mask
201 * or calling notify_cpu_starting.
203 set_cpu_sibling_map(raw_smp_processor_id());
206 notify_cpu_starting(cpuid);
209 * Allow the master to continue.
211 cpumask_set_cpu(cpuid, cpu_callin_mask);
214 static int cpu0_logical_apicid;
215 static int enable_start_cpu0;
217 * Activate a secondary processor.
219 static void notrace start_secondary(void *unused)
222 * Don't put *anything* before cpu_init(), SMP booting is too
223 * fragile that we want to limit the things done here to the
224 * most necessary things.
227 x86_cpuinit.early_percpu_clock_init();
231 enable_start_cpu0 = 0;
234 /* switch away from the initial page table */
235 load_cr3(swapper_pg_dir);
239 /* otherwise gcc will move up smp_processor_id before the cpu_init */
242 * Check TSC synchronization with the BP:
244 check_tsc_sync_target();
247 * Enable the espfix hack for this CPU
249 #ifdef CONFIG_X86_ESPFIX64
254 * We need to hold vector_lock so there the set of online cpus
255 * does not change while we are assigning vectors to cpus. Holding
256 * this lock ensures we don't half assign or remove an irq from a cpu.
259 set_cpu_online(smp_processor_id(), true);
260 unlock_vector_lock();
261 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
262 x86_platform.nmi_init();
264 /* enable local interrupts */
267 /* to prevent fake stack check failure in clock setup */
268 boot_init_stack_canary();
270 x86_cpuinit.setup_percpu_clockev();
273 cpu_startup_entry(CPUHP_ONLINE);
276 void __init smp_store_boot_cpu_info(void)
278 int id = 0; /* CPU 0 */
279 struct cpuinfo_x86 *c = &cpu_data(id);
286 * The bootstrap kernel entry code has set these up. Save them for
289 void smp_store_cpu_info(int id)
291 struct cpuinfo_x86 *c = &cpu_data(id);
296 * During boot time, CPU0 has this setup already. Save the info when
297 * bringing up AP or offlined CPU0.
299 identify_secondary_cpu(c);
303 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
305 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
307 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
311 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
313 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
315 return !WARN_ONCE(!topology_same_node(c, o),
316 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
317 "[node: %d != %d]. Ignoring dependency.\n",
318 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
321 #define link_mask(_m, c1, c2) \
323 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
324 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
327 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
329 if (cpu_has_topoext) {
330 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
332 if (c->phys_proc_id == o->phys_proc_id &&
333 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
334 c->compute_unit_id == o->compute_unit_id)
335 return topology_sane(c, o, "smt");
337 } else if (c->phys_proc_id == o->phys_proc_id &&
338 c->cpu_core_id == o->cpu_core_id) {
339 return topology_sane(c, o, "smt");
345 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
347 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
349 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
350 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
351 return topology_sane(c, o, "llc");
357 * Unlike the other levels, we do not enforce keeping a
358 * multicore group inside a NUMA node. If this happens, we will
359 * discard the MC level of the topology later.
361 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
363 if (c->phys_proc_id == o->phys_proc_id)
368 static struct sched_domain_topology_level numa_inside_package_topology[] = {
369 #ifdef CONFIG_SCHED_SMT
370 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
372 #ifdef CONFIG_SCHED_MC
373 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
378 * set_sched_topology() sets the topology internal to a CPU. The
379 * NUMA topologies are layered on top of it to build the full
382 * If NUMA nodes are observed to occur within a CPU package, this
383 * function should be called. It forces the sched domain code to
384 * only use the SMT level for the CPU portion of the topology.
385 * This essentially falls back to relying on NUMA information
386 * from the SRAT table to describe the entire system topology
387 * (except for hyperthreads).
389 static void primarily_use_numa_for_topology(void)
391 set_sched_topology(numa_inside_package_topology);
394 void set_cpu_sibling_map(int cpu)
396 bool has_smt = smp_num_siblings > 1;
397 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
398 struct cpuinfo_x86 *c = &cpu_data(cpu);
399 struct cpuinfo_x86 *o;
402 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
405 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
406 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
407 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
412 for_each_cpu(i, cpu_sibling_setup_mask) {
415 if ((i == cpu) || (has_smt && match_smt(c, o)))
416 link_mask(sibling, cpu, i);
418 if ((i == cpu) || (has_mp && match_llc(c, o)))
419 link_mask(llc_shared, cpu, i);
424 * This needs a separate iteration over the cpus because we rely on all
425 * cpu_sibling_mask links to be set-up.
427 for_each_cpu(i, cpu_sibling_setup_mask) {
430 if ((i == cpu) || (has_mp && match_die(c, o))) {
431 link_mask(core, cpu, i);
434 * Does this new cpu bringup a new core?
436 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
438 * for each core in package, increment
439 * the booted_cores for this new cpu
441 if (cpumask_first(cpu_sibling_mask(i)) == i)
444 * increment the core count for all
445 * the other cpus in this package
448 cpu_data(i).booted_cores++;
449 } else if (i != cpu && !c->booted_cores)
450 c->booted_cores = cpu_data(i).booted_cores;
452 if (match_die(c, o) && !topology_same_node(c, o))
453 primarily_use_numa_for_topology();
457 /* maps the cpu to the sched domain representing multi-core */
458 const struct cpumask *cpu_coregroup_mask(int cpu)
460 return cpu_llc_shared_mask(cpu);
463 static void impress_friends(void)
466 unsigned long bogosum = 0;
468 * Allow the user to impress friends.
470 pr_debug("Before bogomips\n");
471 for_each_possible_cpu(cpu)
472 if (cpumask_test_cpu(cpu, cpu_callout_mask))
473 bogosum += cpu_data(cpu).loops_per_jiffy;
474 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
477 (bogosum/(5000/HZ))%100);
479 pr_debug("Before bogocount - setting activated=1\n");
482 void __inquire_remote_apic(int apicid)
484 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
485 const char * const names[] = { "ID", "VERSION", "SPIV" };
489 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
491 for (i = 0; i < ARRAY_SIZE(regs); i++) {
492 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
497 status = safe_apic_wait_icr_idle();
499 pr_cont("a previous APIC delivery may have failed\n");
501 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
506 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
507 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
510 case APIC_ICR_RR_VALID:
511 status = apic_read(APIC_RRR);
512 pr_cont("%08x\n", status);
521 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
522 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
523 * won't ... remember to clear down the APIC, etc later.
526 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
528 unsigned long send_status, accept_status = 0;
532 /* Boot on the stack */
533 /* Kick the second */
534 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
536 pr_debug("Waiting for send to finish...\n");
537 send_status = safe_apic_wait_icr_idle();
540 * Give the other CPU some time to accept the IPI.
543 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
544 maxlvt = lapic_get_maxlvt();
545 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
546 apic_write(APIC_ESR, 0);
547 accept_status = (apic_read(APIC_ESR) & 0xEF);
549 pr_debug("NMI sent\n");
552 pr_err("APIC never delivered???\n");
554 pr_err("APIC delivery error (%lx)\n", accept_status);
556 return (send_status | accept_status);
560 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
562 unsigned long send_status, accept_status = 0;
563 int maxlvt, num_starts, j;
565 maxlvt = lapic_get_maxlvt();
568 * Be paranoid about clearing APIC errors.
570 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
571 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
572 apic_write(APIC_ESR, 0);
576 pr_debug("Asserting INIT\n");
579 * Turn INIT on target chip
584 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
587 pr_debug("Waiting for send to finish...\n");
588 send_status = safe_apic_wait_icr_idle();
592 pr_debug("Deasserting INIT\n");
596 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
598 pr_debug("Waiting for send to finish...\n");
599 send_status = safe_apic_wait_icr_idle();
602 atomic_set(&init_deasserted, 1);
605 * Should we send STARTUP IPIs ?
607 * Determine this based on the APIC version.
608 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
610 if (APIC_INTEGRATED(apic_version[phys_apicid]))
616 * Paravirt / VMI wants a startup IPI hook here to set up the
617 * target processor state.
619 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
623 * Run STARTUP IPI loop.
625 pr_debug("#startup loops: %d\n", num_starts);
627 for (j = 1; j <= num_starts; j++) {
628 pr_debug("Sending STARTUP #%d\n", j);
629 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
630 apic_write(APIC_ESR, 0);
632 pr_debug("After apic_write\n");
639 /* Boot on the stack */
640 /* Kick the second */
641 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
645 * Give the other CPU some time to accept the IPI.
649 pr_debug("Startup point 1\n");
651 pr_debug("Waiting for send to finish...\n");
652 send_status = safe_apic_wait_icr_idle();
655 * Give the other CPU some time to accept the IPI.
658 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
659 apic_write(APIC_ESR, 0);
660 accept_status = (apic_read(APIC_ESR) & 0xEF);
661 if (send_status || accept_status)
664 pr_debug("After Startup\n");
667 pr_err("APIC never delivered???\n");
669 pr_err("APIC delivery error (%lx)\n", accept_status);
671 return (send_status | accept_status);
674 void smp_announce(void)
676 int num_nodes = num_online_nodes();
678 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
679 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
682 /* reduce the number of lines printed when booting a large cpu count system */
683 static void announce_cpu(int cpu, int apicid)
685 static int current_node = -1;
686 int node = early_cpu_to_node(cpu);
687 static int width, node_width;
690 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
693 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
696 printk(KERN_INFO "x86: Booting SMP configuration:\n");
698 if (system_state == SYSTEM_BOOTING) {
699 if (node != current_node) {
700 if (current_node > (-1))
704 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
705 node_width - num_digits(node), " ", node);
708 /* Add padding for the BSP */
710 pr_cont("%*s", width + 1, " ");
712 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
715 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
719 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
723 cpu = smp_processor_id();
724 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
731 * Wake up AP by INIT, INIT, STARTUP sequence.
733 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
734 * boot-strap code which is not a desired behavior for waking up BSP. To
735 * void the boot-strap code, wake up CPU0 by NMI instead.
737 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
738 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
739 * We'll change this code in the future to wake up hard offlined CPU0 if
740 * real platform and request are available.
743 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
744 int *cpu0_nmi_registered)
752 * Wake up AP by INIT, INIT, STARTUP sequence.
755 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
760 * Wake up BSP by nmi.
762 * Register a NMI handler to help wake up CPU0.
764 boot_error = register_nmi_handler(NMI_LOCAL,
765 wakeup_cpu0_nmi, 0, "wake_cpu0");
768 enable_start_cpu0 = 1;
769 *cpu0_nmi_registered = 1;
770 if (apic->dest_logical == APIC_DEST_LOGICAL)
771 id = cpu0_logical_apicid;
774 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
784 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
785 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
786 * Returns zero if CPU booted OK, else error code from
787 * ->wakeup_secondary_cpu.
789 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
791 volatile u32 *trampoline_status =
792 (volatile u32 *) __va(real_mode_header->trampoline_status);
793 /* start_ip had better be page-aligned! */
794 unsigned long start_ip = real_mode_header->trampoline_start;
796 unsigned long boot_error = 0;
797 int cpu0_nmi_registered = 0;
798 unsigned long timeout;
800 /* Just in case we booted with a single CPU. */
801 alternatives_enable_smp();
803 idle->thread.sp = (unsigned long) (((struct pt_regs *)
804 (THREAD_SIZE + task_stack_page(idle))) - 1);
805 per_cpu(current_task, cpu) = idle;
808 /* Stack for startup_32 can be just as for start_secondary onwards */
811 clear_tsk_thread_flag(idle, TIF_FORK);
812 initial_gs = per_cpu_offset(cpu);
814 per_cpu(kernel_stack, cpu) =
815 (unsigned long)task_stack_page(idle) -
816 KERNEL_STACK_OFFSET + THREAD_SIZE;
817 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
818 initial_code = (unsigned long)start_secondary;
819 stack_start = idle->thread.sp;
821 /* So we see what's up */
822 announce_cpu(cpu, apicid);
825 * This grunge runs the startup process for
826 * the targeted processor.
829 atomic_set(&init_deasserted, 0);
831 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
833 pr_debug("Setting warm reset code and vector.\n");
835 smpboot_setup_warm_reset_vector(start_ip);
837 * Be paranoid about clearing APIC errors.
839 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
840 apic_write(APIC_ESR, 0);
846 * AP might wait on cpu_callout_mask in cpu_init() with
847 * cpu_initialized_mask set if previous attempt to online
848 * it timed-out. Clear cpu_initialized_mask so that after
849 * INIT/SIPI it could start with a clean state.
851 cpumask_clear_cpu(cpu, cpu_initialized_mask);
855 * Wake up a CPU in difference cases:
856 * - Use the method in the APIC driver if it's defined
858 * - Use an INIT boot APIC message for APs or NMI for BSP.
860 if (apic->wakeup_secondary_cpu)
861 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
863 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
864 &cpu0_nmi_registered);
868 * Wait 10s total for a response from AP
871 timeout = jiffies + 10*HZ;
872 while (time_before(jiffies, timeout)) {
873 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
875 * Tell AP to proceed with initialization
877 cpumask_set_cpu(cpu, cpu_callout_mask);
888 * Wait till AP completes initial initialization
890 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
892 * Allow other tasks to run while we wait for the
893 * AP to come online. This also gives a chance
894 * for the MTRR work(triggered by the AP coming online)
895 * to be completed in the stop machine context.
902 /* mark "stuck" area as not stuck */
903 *trampoline_status = 0;
905 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
907 * Cleanup possible dangling ends...
909 smpboot_restore_warm_reset_vector();
912 * Clean up the nmi handler. Do this after the callin and callout sync
913 * to avoid impact of possible long unregister time.
915 if (cpu0_nmi_registered)
916 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
921 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
923 int apicid = apic->cpu_present_to_apicid(cpu);
927 WARN_ON(irqs_disabled());
929 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
931 if (apicid == BAD_APICID ||
932 !physid_isset(apicid, phys_cpu_present_map) ||
933 !apic->apic_id_valid(apicid)) {
934 pr_err("%s: bad cpu %d\n", __func__, cpu);
939 * Already booted CPU?
941 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
942 pr_debug("do_boot_cpu %d Already started\n", cpu);
947 * Save current MTRR state in case it was changed since early boot
948 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
952 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
954 /* the FPU context is blank, nobody can own it */
955 __cpu_disable_lazy_restore(cpu);
957 err = do_boot_cpu(apicid, cpu, tidle);
959 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
964 * Check TSC synchronization with the AP (keep irqs disabled
967 local_irq_save(flags);
968 check_tsc_sync_source(cpu);
969 local_irq_restore(flags);
971 while (!cpu_online(cpu)) {
973 touch_nmi_watchdog();
980 * arch_disable_smp_support() - disables SMP support for x86 at runtime
982 void arch_disable_smp_support(void)
984 disable_ioapic_support();
988 * Fall back to non SMP mode after errors.
990 * RED-PEN audit/test this more. I bet there is more state messed up here.
992 static __init void disable_smp(void)
994 disable_ioapic_support();
996 init_cpu_present(cpumask_of(0));
997 init_cpu_possible(cpumask_of(0));
999 if (smp_found_config)
1000 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1002 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1003 cpumask_set_cpu(0, cpu_sibling_mask(0));
1004 cpumask_set_cpu(0, cpu_core_mask(0));
1008 * Various sanity checks.
1010 static int __init smp_sanity_check(unsigned max_cpus)
1014 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1015 if (def_to_bigsmp && nr_cpu_ids > 8) {
1019 pr_warn("More than 8 CPUs detected - skipping them\n"
1020 "Use CONFIG_X86_BIGSMP\n");
1023 for_each_present_cpu(cpu) {
1025 set_cpu_present(cpu, false);
1030 for_each_possible_cpu(cpu) {
1032 set_cpu_possible(cpu, false);
1040 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1041 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1042 hard_smp_processor_id());
1044 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1048 * If we couldn't find an SMP configuration at boot time,
1049 * get out of here now!
1051 if (!smp_found_config && !acpi_lapic) {
1053 pr_notice("SMP motherboard not detected\n");
1055 if (APIC_init_uniprocessor())
1056 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1061 * Should not be necessary because the MP table should list the boot
1062 * CPU too, but we do it for the sake of robustness anyway.
1064 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1065 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1066 boot_cpu_physical_apicid);
1067 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1072 * If we couldn't find a local APIC, then get out of here now!
1074 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1076 if (!disable_apic) {
1077 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1078 boot_cpu_physical_apicid);
1079 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1081 disable_ioapic_support();
1085 verify_local_APIC();
1088 * If SMP should be disabled, then really disable it!
1091 pr_info("SMP mode deactivated\n");
1092 disable_ioapic_support();
1096 bsp_end_local_APIC_setup();
1103 static void __init smp_cpu_index_default(void)
1106 struct cpuinfo_x86 *c;
1108 for_each_possible_cpu(i) {
1110 /* mark all to hotplug */
1111 c->cpu_index = nr_cpu_ids;
1116 * Prepare for SMP bootup. The MP table or ACPI has been read
1117 * earlier. Just do some sanity checking here and enable APIC mode.
1119 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1123 smp_cpu_index_default();
1126 * Setup boot CPU information
1128 smp_store_boot_cpu_info(); /* Final full version of the data */
1129 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1132 current_thread_info()->cpu = 0; /* needed? */
1133 for_each_possible_cpu(i) {
1134 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1135 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1136 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1138 set_cpu_sibling_map(0);
1140 if (smp_sanity_check(max_cpus) < 0) {
1141 pr_info("SMP disabled\n");
1146 default_setup_apic_routing();
1148 if (read_apic_id() != boot_cpu_physical_apicid) {
1149 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1150 read_apic_id(), boot_cpu_physical_apicid);
1151 /* Or can we switch back to PIC here? */
1157 * Switch from PIC to APIC mode.
1162 cpu0_logical_apicid = apic_read(APIC_LDR);
1164 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1166 /* Enable IO APIC before setting up error vector */
1169 bsp_end_local_APIC_setup();
1173 * Set up local APIC timer on boot CPU.
1175 pr_info("CPU%d: ", 0);
1176 print_cpu_info(&cpu_data(0));
1177 x86_init.timers.setup_percpu_clockev();
1182 set_mtrr_aps_delayed_init();
1185 void arch_enable_nonboot_cpus_begin(void)
1187 set_mtrr_aps_delayed_init();
1190 void arch_enable_nonboot_cpus_end(void)
1196 * Early setup to make printk work.
1198 void __init native_smp_prepare_boot_cpu(void)
1200 int me = smp_processor_id();
1201 switch_to_new_gdt(me);
1202 /* already set me in cpu_online_mask in boot_cpu_init() */
1203 cpumask_set_cpu(me, cpu_callout_mask);
1204 per_cpu(cpu_state, me) = CPU_ONLINE;
1207 void __init native_smp_cpus_done(unsigned int max_cpus)
1209 pr_debug("Boot done\n");
1213 setup_ioapic_dest();
1217 static int __initdata setup_possible_cpus = -1;
1218 static int __init _setup_possible_cpus(char *str)
1220 get_option(&str, &setup_possible_cpus);
1223 early_param("possible_cpus", _setup_possible_cpus);
1227 * cpu_possible_mask should be static, it cannot change as cpu's
1228 * are onlined, or offlined. The reason is per-cpu data-structures
1229 * are allocated by some modules at init time, and dont expect to
1230 * do this dynamically on cpu arrival/departure.
1231 * cpu_present_mask on the other hand can change dynamically.
1232 * In case when cpu_hotplug is not compiled, then we resort to current
1233 * behaviour, which is cpu_possible == cpu_present.
1236 * Three ways to find out the number of additional hotplug CPUs:
1237 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1238 * - The user can overwrite it with possible_cpus=NUM
1239 * - Otherwise don't reserve additional CPUs.
1240 * We do this because additional CPUs waste a lot of memory.
1243 __init void prefill_possible_map(void)
1247 /* no processor from mptable or madt */
1248 if (!num_processors)
1251 i = setup_max_cpus ?: 1;
1252 if (setup_possible_cpus == -1) {
1253 possible = num_processors;
1254 #ifdef CONFIG_HOTPLUG_CPU
1256 possible += disabled_cpus;
1262 possible = setup_possible_cpus;
1264 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1266 /* nr_cpu_ids could be reduced via nr_cpus= */
1267 if (possible > nr_cpu_ids) {
1268 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1269 possible, nr_cpu_ids);
1270 possible = nr_cpu_ids;
1273 #ifdef CONFIG_HOTPLUG_CPU
1274 if (!setup_max_cpus)
1277 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1278 possible, setup_max_cpus);
1282 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1283 possible, max_t(int, possible - num_processors, 0));
1285 for (i = 0; i < possible; i++)
1286 set_cpu_possible(i, true);
1287 for (; i < NR_CPUS; i++)
1288 set_cpu_possible(i, false);
1290 nr_cpu_ids = possible;
1293 #ifdef CONFIG_HOTPLUG_CPU
1295 static void remove_siblinginfo(int cpu)
1298 struct cpuinfo_x86 *c = &cpu_data(cpu);
1300 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1301 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1303 * last thread sibling in this cpu core going down
1305 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1306 cpu_data(sibling).booted_cores--;
1309 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1310 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1311 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1312 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1313 cpumask_clear(cpu_llc_shared_mask(cpu));
1314 cpumask_clear(cpu_sibling_mask(cpu));
1315 cpumask_clear(cpu_core_mask(cpu));
1316 c->phys_proc_id = 0;
1318 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1321 static void __ref remove_cpu_from_maps(int cpu)
1323 set_cpu_online(cpu, false);
1324 cpumask_clear_cpu(cpu, cpu_callout_mask);
1325 cpumask_clear_cpu(cpu, cpu_callin_mask);
1326 /* was set by cpu_init() */
1327 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1328 numa_remove_cpu(cpu);
1331 static DEFINE_PER_CPU(struct completion, die_complete);
1333 void cpu_disable_common(void)
1335 int cpu = smp_processor_id();
1337 init_completion(&per_cpu(die_complete, smp_processor_id()));
1339 remove_siblinginfo(cpu);
1341 /* It's now safe to remove this processor from the online map */
1343 remove_cpu_from_maps(cpu);
1344 unlock_vector_lock();
1348 int native_cpu_disable(void)
1352 ret = check_irq_vectors_for_cpu_disable();
1357 cpu_disable_common();
1362 void cpu_die_common(unsigned int cpu)
1364 wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ);
1367 void native_cpu_die(unsigned int cpu)
1369 /* We don't do anything here: idle task is faking death itself. */
1371 cpu_die_common(cpu);
1373 /* They ack this in play_dead() by setting CPU_DEAD */
1374 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1375 if (system_state == SYSTEM_RUNNING)
1376 pr_info("CPU %u is now offline\n", cpu);
1378 pr_err("CPU %u didn't die...\n", cpu);
1382 void play_dead_common(void)
1385 reset_lazy_tlbstate();
1386 amd_e400_remove_cpu(raw_smp_processor_id());
1390 __this_cpu_write(cpu_state, CPU_DEAD);
1391 complete(&per_cpu(die_complete, smp_processor_id()));
1394 * With physical CPU hotplug, we should halt the cpu
1396 local_irq_disable();
1399 static bool wakeup_cpu0(void)
1401 if (smp_processor_id() == 0 && enable_start_cpu0)
1408 * We need to flush the caches before going to sleep, lest we have
1409 * dirty data in our caches when we come back up.
1411 static inline void mwait_play_dead(void)
1413 unsigned int eax, ebx, ecx, edx;
1414 unsigned int highest_cstate = 0;
1415 unsigned int highest_subcstate = 0;
1419 if (!this_cpu_has(X86_FEATURE_MWAIT))
1421 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1423 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1426 eax = CPUID_MWAIT_LEAF;
1428 native_cpuid(&eax, &ebx, &ecx, &edx);
1431 * eax will be 0 if EDX enumeration is not valid.
1432 * Initialized below to cstate, sub_cstate value when EDX is valid.
1434 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1437 edx >>= MWAIT_SUBSTATE_SIZE;
1438 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1439 if (edx & MWAIT_SUBSTATE_MASK) {
1441 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1444 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1445 (highest_subcstate - 1);
1449 * This should be a memory location in a cache line which is
1450 * unlikely to be touched by other processors. The actual
1451 * content is immaterial as it is not actually modified in any way.
1453 mwait_ptr = ¤t_thread_info()->flags;
1459 * The CLFLUSH is a workaround for erratum AAI65 for
1460 * the Xeon 7400 series. It's not clear it is actually
1461 * needed, but it should be harmless in either case.
1462 * The WBINVD is insufficient due to the spurious-wakeup
1463 * case where we return around the loop.
1468 __monitor(mwait_ptr, 0, 0);
1472 * If NMI wants to wake up CPU0, start CPU0.
1479 static inline void hlt_play_dead(void)
1481 if (__this_cpu_read(cpu_info.x86) >= 4)
1487 * If NMI wants to wake up CPU0, start CPU0.
1494 void native_play_dead(void)
1497 tboot_shutdown(TB_SHUTDOWN_WFS);
1499 mwait_play_dead(); /* Only returns on failure */
1500 if (cpuidle_play_dead())
1504 #else /* ... !CONFIG_HOTPLUG_CPU */
1505 int native_cpu_disable(void)
1510 void native_cpu_die(unsigned int cpu)
1512 /* We said "no" in __cpu_disable */
1516 void native_play_dead(void)