2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
5 * Pentium III FXSR, SSE support
6 * Gareth Hughes <gareth@valinux.com>, May 2000
10 * Handle hardware traps and faults.
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/context_tracking.h>
16 #include <linux/interrupt.h>
17 #include <linux/kallsyms.h>
18 #include <linux/spinlock.h>
19 #include <linux/kprobes.h>
20 #include <linux/uaccess.h>
21 #include <linux/kdebug.h>
22 #include <linux/kgdb.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/ptrace.h>
26 #include <linux/uprobes.h>
27 #include <linux/string.h>
28 #include <linux/delay.h>
29 #include <linux/errno.h>
30 #include <linux/kexec.h>
31 #include <linux/sched.h>
32 #include <linux/timer.h>
33 #include <linux/init.h>
34 #include <linux/bug.h>
35 #include <linux/nmi.h>
37 #include <linux/smp.h>
41 #include <linux/ioport.h>
42 #include <linux/eisa.h>
45 #if defined(CONFIG_EDAC)
46 #include <linux/edac.h>
49 #include <asm/kmemcheck.h>
50 #include <asm/stacktrace.h>
51 #include <asm/processor.h>
52 #include <asm/debugreg.h>
53 #include <linux/atomic.h>
54 #include <asm/ftrace.h>
55 #include <asm/traps.h>
58 #include <asm/fpu-internal.h>
60 #include <asm/fixmap.h>
61 #include <asm/mach_traps.h>
62 #include <asm/alternative.h>
66 #include <asm/x86_init.h>
67 #include <asm/pgalloc.h>
68 #include <asm/proto.h>
70 /* No need to be aligned, but done to keep all IDTs defined the same way. */
71 gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss;
73 #include <asm/processor-flags.h>
74 #include <asm/setup.h>
76 asmlinkage int system_call(void);
79 /* Must be page-aligned because the real IDT is used in a fixmap. */
80 gate_desc idt_table[NR_VECTORS] __page_aligned_bss;
82 DECLARE_BITMAP(used_vectors, NR_VECTORS);
83 EXPORT_SYMBOL_GPL(used_vectors);
85 static inline void conditional_sti(struct pt_regs *regs)
87 if (regs->flags & X86_EFLAGS_IF)
91 static inline void preempt_conditional_sti(struct pt_regs *regs)
94 if (regs->flags & X86_EFLAGS_IF)
98 static inline void conditional_cli(struct pt_regs *regs)
100 if (regs->flags & X86_EFLAGS_IF)
104 static inline void preempt_conditional_cli(struct pt_regs *regs)
106 if (regs->flags & X86_EFLAGS_IF)
111 enum ctx_state ist_enter(struct pt_regs *regs)
114 * We are atomic because we're on the IST stack (or we're on x86_32,
115 * in which case we still shouldn't schedule.
117 preempt_count_add(HARDIRQ_OFFSET);
119 if (user_mode_vm(regs)) {
120 /* Other than that, we're just an exception. */
121 return exception_enter();
124 * We might have interrupted pretty much anything. In
125 * fact, if we're a machine check, we can even interrupt
126 * NMI processing. We don't want in_nmi() to return true,
127 * but we need to notify RCU.
130 return IN_KERNEL; /* the value is irrelevant. */
134 void ist_exit(struct pt_regs *regs, enum ctx_state prev_state)
136 preempt_count_sub(HARDIRQ_OFFSET);
138 if (user_mode_vm(regs))
139 return exception_exit(prev_state);
145 * ist_begin_non_atomic() - begin a non-atomic section in an IST exception
146 * @regs: regs passed to the IST exception handler
148 * IST exception handlers normally cannot schedule. As a special
149 * exception, if the exception interrupted userspace code (i.e.
150 * user_mode_vm(regs) would return true) and the exception was not
151 * a double fault, it can be safe to schedule. ist_begin_non_atomic()
152 * begins a non-atomic section within an ist_enter()/ist_exit() region.
153 * Callers are responsible for enabling interrupts themselves inside
154 * the non-atomic section, and callers must call is_end_non_atomic()
157 void ist_begin_non_atomic(struct pt_regs *regs)
159 BUG_ON(!user_mode_vm(regs));
162 * Sanity check: we need to be on the normal thread stack. This
163 * will catch asm bugs and any attempt to use ist_preempt_enable
166 BUG_ON(((current_stack_pointer() ^ this_cpu_read_stable(kernel_stack))
167 & ~(THREAD_SIZE - 1)) != 0);
169 preempt_count_sub(HARDIRQ_OFFSET);
173 * ist_end_non_atomic() - begin a non-atomic section in an IST exception
175 * Ends a non-atomic section started with ist_begin_non_atomic().
177 void ist_end_non_atomic(void)
179 preempt_count_add(HARDIRQ_OFFSET);
182 static nokprobe_inline int
183 do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str,
184 struct pt_regs *regs, long error_code)
187 if (regs->flags & X86_VM_MASK) {
189 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86.
190 * On nmi (interrupt 2), do_trap should not be called.
192 if (trapnr < X86_TRAP_UD) {
193 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs,
200 if (!user_mode(regs)) {
201 if (!fixup_exception(regs)) {
202 tsk->thread.error_code = error_code;
203 tsk->thread.trap_nr = trapnr;
204 die(str, regs, error_code);
212 static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr,
215 unsigned long siaddr;
220 return SEND_SIG_PRIV;
224 siaddr = uprobe_get_trap_addr(regs);
228 siaddr = uprobe_get_trap_addr(regs);
236 info->si_signo = signr;
238 info->si_code = sicode;
239 info->si_addr = (void __user *)siaddr;
244 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
245 long error_code, siginfo_t *info)
247 struct task_struct *tsk = current;
250 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
253 * We want error_code and trap_nr set for userspace faults and
254 * kernelspace faults which result in die(), but not
255 * kernelspace faults which are fixed up. die() gives the
256 * process no chance to handle the signal and notice the
257 * kernel fault information, so that won't result in polluting
258 * the information about previously queued, but not yet
259 * delivered, faults. See also do_general_protection below.
261 tsk->thread.error_code = error_code;
262 tsk->thread.trap_nr = trapnr;
265 if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
266 printk_ratelimit()) {
267 pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx",
268 tsk->comm, tsk->pid, str,
269 regs->ip, regs->sp, error_code);
270 print_vma_addr(" in ", regs->ip);
275 force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk);
277 NOKPROBE_SYMBOL(do_trap);
279 static void do_error_trap(struct pt_regs *regs, long error_code, char *str,
280 unsigned long trapnr, int signr)
282 enum ctx_state prev_state = exception_enter();
285 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) !=
287 conditional_sti(regs);
288 do_trap(trapnr, signr, str, regs, error_code,
289 fill_trap_info(regs, signr, trapnr, &info));
292 exception_exit(prev_state);
295 #define DO_ERROR(trapnr, signr, str, name) \
296 dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \
298 do_error_trap(regs, error_code, str, trapnr, signr); \
301 DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error)
302 DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow)
303 DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op)
304 DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun)
305 DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS)
306 DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present)
307 DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment)
308 DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check)
311 /* Runs on IST stack */
312 dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
314 static const char str[] = "double fault";
315 struct task_struct *tsk = current;
317 #ifdef CONFIG_X86_ESPFIX64
318 extern unsigned char native_irq_return_iret[];
321 * If IRET takes a non-IST fault on the espfix64 stack, then we
322 * end up promoting it to a doublefault. In that case, modify
323 * the stack to make it look like we just entered the #GP
324 * handler from user space, similar to bad_iret.
326 * No need for ist_enter here because we don't use RCU.
328 if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY &&
329 regs->cs == __KERNEL_CS &&
330 regs->ip == (unsigned long)native_irq_return_iret)
332 struct pt_regs *normal_regs = task_pt_regs(current);
334 /* Fake a #GP(0) from userspace. */
335 memmove(&normal_regs->ip, (void *)regs->sp, 5*8);
336 normal_regs->orig_ax = 0; /* Missing (lost) #GP error code */
337 regs->ip = (unsigned long)general_protection;
338 regs->sp = (unsigned long)&normal_regs->orig_ax;
344 ist_enter(regs); /* Discard prev_state because we won't return. */
345 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV);
347 tsk->thread.error_code = error_code;
348 tsk->thread.trap_nr = X86_TRAP_DF;
350 #ifdef CONFIG_DOUBLEFAULT
351 df_debug(regs, error_code);
354 * This is always a kernel trap and never fixable (and thus must
358 die(str, regs, error_code);
362 dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
364 struct task_struct *tsk = current;
365 struct xsave_struct *xsave_buf;
366 enum ctx_state prev_state;
367 struct bndcsr *bndcsr;
370 prev_state = exception_enter();
371 if (notify_die(DIE_TRAP, "bounds", regs, error_code,
372 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP)
374 conditional_sti(regs);
376 if (!user_mode(regs))
377 die("bounds", regs, error_code);
379 if (!cpu_feature_enabled(X86_FEATURE_MPX)) {
380 /* The exception is not from Intel MPX */
385 * We need to look at BNDSTATUS to resolve this exception.
386 * It is not directly accessible, though, so we need to
387 * do an xsave and then pull it out of the xsave buffer.
389 fpu_save_init(&tsk->thread.fpu);
390 xsave_buf = &(tsk->thread.fpu.state->xsave);
391 bndcsr = get_xsave_addr(xsave_buf, XSTATE_BNDCSR);
396 * The error code field of the BNDSTATUS register communicates status
397 * information of a bound range exception #BR or operation involving
400 switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) {
401 case 2: /* Bound directory has invalid entry. */
402 if (mpx_handle_bd_fault(xsave_buf))
404 break; /* Success, it was handled */
405 case 1: /* Bound violation. */
406 info = mpx_generate_siginfo(regs, xsave_buf);
409 * We failed to decode the MPX instruction. Act as if
410 * the exception was not caused by MPX.
415 * Success, we decoded the instruction and retrieved
416 * an 'info' containing the address being accessed
417 * which caused the exception. This information
418 * allows and application to possibly handle the
419 * #BR exception itself.
421 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info);
424 case 0: /* No exception caused by Intel MPX operations. */
427 die("bounds", regs, error_code);
431 exception_exit(prev_state);
435 * This path out is for all the cases where we could not
436 * handle the exception in some way (like allocating a
437 * table or telling userspace about it. We will also end
438 * up here if the kernel has MPX turned off at compile
441 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL);
442 exception_exit(prev_state);
446 do_general_protection(struct pt_regs *regs, long error_code)
448 struct task_struct *tsk;
449 enum ctx_state prev_state;
451 prev_state = exception_enter();
452 conditional_sti(regs);
455 if (regs->flags & X86_VM_MASK) {
457 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code);
463 if (!user_mode(regs)) {
464 if (fixup_exception(regs))
467 tsk->thread.error_code = error_code;
468 tsk->thread.trap_nr = X86_TRAP_GP;
469 if (notify_die(DIE_GPF, "general protection fault", regs, error_code,
470 X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP)
471 die("general protection fault", regs, error_code);
475 tsk->thread.error_code = error_code;
476 tsk->thread.trap_nr = X86_TRAP_GP;
478 if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
479 printk_ratelimit()) {
480 pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx",
481 tsk->comm, task_pid_nr(tsk),
482 regs->ip, regs->sp, error_code);
483 print_vma_addr(" in ", regs->ip);
487 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
489 exception_exit(prev_state);
491 NOKPROBE_SYMBOL(do_general_protection);
493 /* May run on IST stack. */
494 dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code)
496 enum ctx_state prev_state;
498 #ifdef CONFIG_DYNAMIC_FTRACE
500 * ftrace must be first, everything else may cause a recursive crash.
501 * See note by declaration of modifying_ftrace_code in ftrace.c
503 if (unlikely(atomic_read(&modifying_ftrace_code)) &&
504 ftrace_int3_handler(regs))
507 if (poke_int3_handler(regs))
510 prev_state = ist_enter(regs);
511 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
512 if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
513 SIGTRAP) == NOTIFY_STOP)
515 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
517 #ifdef CONFIG_KPROBES
518 if (kprobe_int3_handler(regs))
522 if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
523 SIGTRAP) == NOTIFY_STOP)
527 * Let others (NMI) know that the debug stack is in use
528 * as we may switch to the interrupt stack.
530 debug_stack_usage_inc();
531 preempt_conditional_sti(regs);
532 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL);
533 preempt_conditional_cli(regs);
534 debug_stack_usage_dec();
536 ist_exit(regs, prev_state);
538 NOKPROBE_SYMBOL(do_int3);
542 * Help handler running on IST stack to switch off the IST stack if the
543 * interrupted code was in user mode. The actual stack switch is done in
546 asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs)
548 struct pt_regs *regs = task_pt_regs(current);
552 NOKPROBE_SYMBOL(sync_regs);
554 struct bad_iret_stack {
555 void *error_entry_ret;
559 asmlinkage __visible notrace
560 struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s)
563 * This is called from entry_64.S early in handling a fault
564 * caused by a bad iret to user mode. To handle the fault
565 * correctly, we want move our stack frame to task_pt_regs
566 * and we want to pretend that the exception came from the
569 struct bad_iret_stack *new_stack =
570 container_of(task_pt_regs(current),
571 struct bad_iret_stack, regs);
573 /* Copy the IRET target to the new stack. */
574 memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8);
576 /* Copy the remainder of the stack from the current stack. */
577 memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip));
579 BUG_ON(!user_mode_vm(&new_stack->regs));
582 NOKPROBE_SYMBOL(fixup_bad_iret);
586 * Our handling of the processor debug registers is non-trivial.
587 * We do not clear them on entry and exit from the kernel. Therefore
588 * it is possible to get a watchpoint trap here from inside the kernel.
589 * However, the code in ./ptrace.c has ensured that the user can
590 * only set watchpoints on userspace addresses. Therefore the in-kernel
591 * watchpoint trap can only occur in code which is reading/writing
592 * from user space. Such code must not hold kernel locks (since it
593 * can equally take a page fault), therefore it is safe to call
594 * force_sig_info even though that claims and releases locks.
596 * Code in ./signal.c ensures that the debug control register
597 * is restored before we deliver any signal, and therefore that
598 * user code runs with the correct debug control register even though
601 * Being careful here means that we don't have to be as careful in a
602 * lot of more complicated places (task switching can be a bit lazy
603 * about restoring all the debug state, and ptrace doesn't have to
604 * find every occurrence of the TF bit that could be saved away even
607 * May run on IST stack.
609 dotraplinkage void do_debug(struct pt_regs *regs, long error_code)
611 struct task_struct *tsk = current;
612 enum ctx_state prev_state;
617 prev_state = ist_enter(regs);
619 get_debugreg(dr6, 6);
621 /* Filter out all the reserved bits which are preset to 1 */
622 dr6 &= ~DR6_RESERVED;
625 * If dr6 has no reason to give us about the origin of this trap,
626 * then it's very likely the result of an icebp/int01 trap.
627 * User wants a sigtrap for that.
629 if (!dr6 && user_mode(regs))
632 /* Catch kmemcheck conditions first of all! */
633 if ((dr6 & DR_STEP) && kmemcheck_trap(regs))
636 /* DR6 may or may not be cleared by the CPU */
640 * The processor cleared BTF, so don't mark that we need it set.
642 clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP);
644 /* Store the virtualized DR6 value */
645 tsk->thread.debugreg6 = dr6;
647 #ifdef CONFIG_KPROBES
648 if (kprobe_debug_handler(regs))
652 if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
653 SIGTRAP) == NOTIFY_STOP)
657 * Let others (NMI) know that the debug stack is in use
658 * as we may switch to the interrupt stack.
660 debug_stack_usage_inc();
662 /* It's safe to allow irq's after DR6 has been saved */
663 preempt_conditional_sti(regs);
665 if (regs->flags & X86_VM_MASK) {
666 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code,
668 preempt_conditional_cli(regs);
669 debug_stack_usage_dec();
674 * Single-stepping through system calls: ignore any exceptions in
675 * kernel space, but re-enable TF when returning to user mode.
677 * We already checked v86 mode above, so we can check for kernel mode
678 * by just checking the CPL of CS.
680 if ((dr6 & DR_STEP) && !user_mode(regs)) {
681 tsk->thread.debugreg6 &= ~DR_STEP;
682 set_tsk_thread_flag(tsk, TIF_SINGLESTEP);
683 regs->flags &= ~X86_EFLAGS_TF;
685 si_code = get_si_code(tsk->thread.debugreg6);
686 if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp)
687 send_sigtrap(tsk, regs, error_code, si_code);
688 preempt_conditional_cli(regs);
689 debug_stack_usage_dec();
692 ist_exit(regs, prev_state);
694 NOKPROBE_SYMBOL(do_debug);
697 * Note that we play around with the 'TS' bit in an attempt to get
698 * the correct behaviour even in the presence of the asynchronous
701 static void math_error(struct pt_regs *regs, int error_code, int trapnr)
703 struct task_struct *task = current;
706 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" :
709 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP)
711 conditional_sti(regs);
713 if (!user_mode_vm(regs))
715 if (!fixup_exception(regs)) {
716 task->thread.error_code = error_code;
717 task->thread.trap_nr = trapnr;
718 die(str, regs, error_code);
724 * Save the info for the exception handler and clear the error.
727 task->thread.trap_nr = trapnr;
728 task->thread.error_code = error_code;
729 info.si_signo = SIGFPE;
731 info.si_addr = (void __user *)uprobe_get_trap_addr(regs);
732 if (trapnr == X86_TRAP_MF) {
733 unsigned short cwd, swd;
735 * (~cwd & swd) will mask out exceptions that are not set to unmasked
736 * status. 0x3f is the exception bits in these regs, 0x200 is the
737 * C1 reg you need in case of a stack fault, 0x040 is the stack
738 * fault bit. We should only be taking one exception at a time,
739 * so if this combination doesn't produce any single exception,
740 * then we have a bad program that isn't synchronizing its FPU usage
741 * and it will suffer the consequences since we won't be able to
742 * fully reproduce the context of the exception
744 cwd = get_fpu_cwd(task);
745 swd = get_fpu_swd(task);
750 * The SIMD FPU exceptions are handled a little differently, as there
751 * is only a single status/control register. Thus, to determine which
752 * unmasked exception was caught we must mask the exception mask bits
753 * at 0x1f80, and then use these to mask the exception bits at 0x3f.
755 unsigned short mxcsr = get_fpu_mxcsr(task);
756 err = ~(mxcsr >> 7) & mxcsr;
759 if (err & 0x001) { /* Invalid op */
761 * swd & 0x240 == 0x040: Stack Underflow
762 * swd & 0x240 == 0x240: Stack Overflow
763 * User must clear the SF bit (0x40) if set
765 info.si_code = FPE_FLTINV;
766 } else if (err & 0x004) { /* Divide by Zero */
767 info.si_code = FPE_FLTDIV;
768 } else if (err & 0x008) { /* Overflow */
769 info.si_code = FPE_FLTOVF;
770 } else if (err & 0x012) { /* Denormal, Underflow */
771 info.si_code = FPE_FLTUND;
772 } else if (err & 0x020) { /* Precision */
773 info.si_code = FPE_FLTRES;
776 * If we're using IRQ 13, or supposedly even some trap
777 * X86_TRAP_MF implementations, it's possible
778 * we get a spurious trap, which is not an error.
782 force_sig_info(SIGFPE, &info, task);
785 dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code)
787 enum ctx_state prev_state;
789 prev_state = exception_enter();
790 math_error(regs, error_code, X86_TRAP_MF);
791 exception_exit(prev_state);
795 do_simd_coprocessor_error(struct pt_regs *regs, long error_code)
797 enum ctx_state prev_state;
799 prev_state = exception_enter();
800 math_error(regs, error_code, X86_TRAP_XF);
801 exception_exit(prev_state);
805 do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
807 conditional_sti(regs);
809 /* No need to warn about this any longer. */
810 pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
814 asmlinkage __visible void __attribute__((weak)) smp_thermal_interrupt(void)
818 asmlinkage __visible void __attribute__((weak)) smp_threshold_interrupt(void)
823 * 'math_state_restore()' saves the current math information in the
824 * old math state array, and gets the new ones from the current task
826 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
827 * Don't touch unless you *really* know how it works.
829 * Must be called with kernel preemption disabled (eg with local
830 * local interrupts as in the case of do_device_not_available).
832 void math_state_restore(void)
834 struct task_struct *tsk = current;
836 if (!tsk_used_math(tsk)) {
839 * does a slab alloc which can sleep
845 do_group_exit(SIGKILL);
851 __thread_fpu_begin(tsk);
854 * Paranoid restore. send a SIGSEGV if we fail to restore the state.
856 if (unlikely(restore_fpu_checking(tsk))) {
858 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
862 tsk->thread.fpu_counter++;
864 EXPORT_SYMBOL_GPL(math_state_restore);
867 do_device_not_available(struct pt_regs *regs, long error_code)
869 enum ctx_state prev_state;
871 prev_state = exception_enter();
872 BUG_ON(use_eager_fpu());
874 #ifdef CONFIG_MATH_EMULATION
875 if (read_cr0() & X86_CR0_EM) {
876 struct math_emu_info info = { };
878 conditional_sti(regs);
882 exception_exit(prev_state);
886 math_state_restore(); /* interrupts still off */
888 conditional_sti(regs);
890 exception_exit(prev_state);
892 NOKPROBE_SYMBOL(do_device_not_available);
895 dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code)
898 enum ctx_state prev_state;
900 prev_state = exception_enter();
903 info.si_signo = SIGILL;
905 info.si_code = ILL_BADSTK;
907 if (notify_die(DIE_TRAP, "iret exception", regs, error_code,
908 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) {
909 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code,
912 exception_exit(prev_state);
916 /* Set of traps needed for early debugging. */
917 void __init early_trap_init(void)
919 set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
920 /* int3 can be called from all */
921 set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
923 set_intr_gate(X86_TRAP_PF, page_fault);
925 load_idt(&idt_descr);
928 void __init early_trap_pf_init(void)
931 set_intr_gate(X86_TRAP_PF, page_fault);
935 void __init trap_init(void)
940 void __iomem *p = early_ioremap(0x0FFFD9, 4);
942 if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24))
947 set_intr_gate(X86_TRAP_DE, divide_error);
948 set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK);
949 /* int4 can be called from all */
950 set_system_intr_gate(X86_TRAP_OF, &overflow);
951 set_intr_gate(X86_TRAP_BR, bounds);
952 set_intr_gate(X86_TRAP_UD, invalid_op);
953 set_intr_gate(X86_TRAP_NM, device_not_available);
955 set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS);
957 set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK);
959 set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun);
960 set_intr_gate(X86_TRAP_TS, invalid_TSS);
961 set_intr_gate(X86_TRAP_NP, segment_not_present);
962 set_intr_gate(X86_TRAP_SS, stack_segment);
963 set_intr_gate(X86_TRAP_GP, general_protection);
964 set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug);
965 set_intr_gate(X86_TRAP_MF, coprocessor_error);
966 set_intr_gate(X86_TRAP_AC, alignment_check);
967 #ifdef CONFIG_X86_MCE
968 set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK);
970 set_intr_gate(X86_TRAP_XF, simd_coprocessor_error);
972 /* Reserve all the builtin and the syscall vector: */
973 for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++)
974 set_bit(i, used_vectors);
976 #ifdef CONFIG_IA32_EMULATION
977 set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall);
978 set_bit(IA32_SYSCALL_VECTOR, used_vectors);
982 set_system_trap_gate(SYSCALL_VECTOR, &system_call);
983 set_bit(SYSCALL_VECTOR, used_vectors);
987 * Set the IDT descriptor to a fixed read-only location, so that the
988 * "sidt" instruction will not leak the location of the kernel, and
989 * to defend the IDT against arbitrary memory write vulnerabilities.
990 * It will be reloaded in cpu_init() */
991 __set_fixmap(FIX_RO_IDT, __pa_symbol(idt_table), PAGE_KERNEL_RO);
992 idt_descr.address = fix_to_virt(FIX_RO_IDT);
995 * Should be a barrier for any external CPU state:
999 x86_init.irqs.trap_init();
1001 #ifdef CONFIG_X86_64
1002 memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16);
1003 set_nmi_gate(X86_TRAP_DB, &debug);
1004 set_nmi_gate(X86_TRAP_BP, &int3);