1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <linux/init.h>
6 #include <linux/export.h>
7 #include <linux/timer.h>
8 #include <linux/acpi_pmtmr.h>
9 #include <linux/cpufreq.h>
10 #include <linux/delay.h>
11 #include <linux/clocksource.h>
12 #include <linux/percpu.h>
13 #include <linux/timex.h>
14 #include <linux/static_key.h>
17 #include <asm/timer.h>
18 #include <asm/vgtod.h>
20 #include <asm/delay.h>
21 #include <asm/hypervisor.h>
23 #include <asm/x86_init.h>
24 #include <asm/geode.h>
26 #include <asm/intel-family.h>
28 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
29 EXPORT_SYMBOL(cpu_khz);
31 unsigned int __read_mostly tsc_khz;
32 EXPORT_SYMBOL(tsc_khz);
35 * TSC can be unstable due to cpufreq or due to unsynced TSCs
37 static int __read_mostly tsc_unstable;
39 /* native_sched_clock() is called before tsc_init(), so
40 we must start with the TSC soft disabled to prevent
41 erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
42 static int __read_mostly tsc_disabled = -1;
44 static DEFINE_STATIC_KEY_FALSE(__use_tsc);
46 int tsc_clocksource_reliable;
48 static u32 art_to_tsc_numerator;
49 static u32 art_to_tsc_denominator;
50 static u64 art_to_tsc_offset;
51 struct clocksource *art_related_clocksource;
54 * Use a ring-buffer like data structure, where a writer advances the head by
55 * writing a new data entry and a reader advances the tail when it observes a
58 * Writers are made to wait on readers until there's space to write a new
61 * This means that we can always use an {offset, mul} pair to compute a ns
62 * value that is 'roughly' in the right direction, even if we're writing a new
63 * {offset, mul} pair during the clock read.
65 * The down-side is that we can no longer guarantee strict monotonicity anymore
66 * (assuming the TSC was that to begin with), because while we compute the
67 * intersection point of the two clock slopes and make sure the time is
68 * continuous at the point of switching; we can no longer guarantee a reader is
69 * strictly before or after the switch point.
71 * It does mean a reader no longer needs to disable IRQs in order to avoid
72 * CPU-Freq updates messing with his times, and similarly an NMI reader will
73 * no longer run the risk of hitting half-written state.
77 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
78 struct cyc2ns_data *head; /* 48 + 8 = 56 */
79 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
80 }; /* exactly fits one cacheline */
82 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
84 struct cyc2ns_data *cyc2ns_read_begin(void)
86 struct cyc2ns_data *head;
90 head = this_cpu_read(cyc2ns.head);
92 * Ensure we observe the entry when we observe the pointer to it.
93 * matches the wmb from cyc2ns_write_end().
95 smp_read_barrier_depends();
102 void cyc2ns_read_end(struct cyc2ns_data *head)
106 * If we're the outer most nested read; update the tail pointer
107 * when we're done. This notifies possible pending writers
108 * that we've observed the head pointer and that the other
111 if (!--head->__count) {
113 * x86-TSO does not reorder writes with older reads;
114 * therefore once this write becomes visible to another
115 * cpu, we must be finished reading the cyc2ns_data.
117 * matches with cyc2ns_write_begin().
119 this_cpu_write(cyc2ns.tail, head);
125 * Begin writing a new @data entry for @cpu.
127 * Assumes some sort of write side lock; currently 'provided' by the assumption
128 * that cpufreq will call its notifiers sequentially.
130 static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
132 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
133 struct cyc2ns_data *data = c2n->data;
135 if (data == c2n->head)
138 /* XXX send an IPI to @cpu in order to guarantee a read? */
141 * When we observe the tail write from cyc2ns_read_end(),
142 * the cpu must be done with that entry and its safe
143 * to start writing to it.
145 while (c2n->tail == data)
151 static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
153 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
156 * Ensure the @data writes are visible before we publish the
157 * entry. Matches the data-depencency in cyc2ns_read_begin().
161 ACCESS_ONCE(c2n->head) = data;
165 * Accelerators for sched_clock()
166 * convert from cycles(64bits) => nanoseconds (64bits)
168 * ns = cycles / (freq / ns_per_sec)
169 * ns = cycles * (ns_per_sec / freq)
170 * ns = cycles * (10^9 / (cpu_khz * 10^3))
171 * ns = cycles * (10^6 / cpu_khz)
173 * Then we use scaling math (suggested by george@mvista.com) to get:
174 * ns = cycles * (10^6 * SC / cpu_khz) / SC
175 * ns = cycles * cyc2ns_scale / SC
177 * And since SC is a constant power of two, we can convert the div
178 * into a shift. The larger SC is, the more accurate the conversion, but
179 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
180 * (64-bit result) can be used.
182 * We can use khz divisor instead of mhz to keep a better precision.
183 * (mathieu.desnoyers@polymtl.ca)
185 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
188 static void cyc2ns_data_init(struct cyc2ns_data *data)
190 data->cyc2ns_mul = 0;
191 data->cyc2ns_shift = 0;
192 data->cyc2ns_offset = 0;
196 static void cyc2ns_init(int cpu)
198 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
200 cyc2ns_data_init(&c2n->data[0]);
201 cyc2ns_data_init(&c2n->data[1]);
203 c2n->head = c2n->data;
204 c2n->tail = c2n->data;
207 static inline unsigned long long cycles_2_ns(unsigned long long cyc)
209 struct cyc2ns_data *data, *tail;
210 unsigned long long ns;
213 * See cyc2ns_read_*() for details; replicated in order to avoid
214 * an extra few instructions that came with the abstraction.
215 * Notable, it allows us to only do the __count and tail update
216 * dance when its actually needed.
219 preempt_disable_notrace();
220 data = this_cpu_read(cyc2ns.head);
221 tail = this_cpu_read(cyc2ns.tail);
223 if (likely(data == tail)) {
224 ns = data->cyc2ns_offset;
225 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
231 ns = data->cyc2ns_offset;
232 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
236 if (!--data->__count)
237 this_cpu_write(cyc2ns.tail, data);
239 preempt_enable_notrace();
244 static void set_cyc2ns_scale(unsigned long khz, int cpu)
246 unsigned long long tsc_now, ns_now;
247 struct cyc2ns_data *data;
250 local_irq_save(flags);
251 sched_clock_idle_sleep_event();
256 data = cyc2ns_write_begin(cpu);
259 ns_now = cycles_2_ns(tsc_now);
262 * Compute a new multiplier as per the above comment and ensure our
263 * time function is continuous; see the comment near struct
266 clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, khz,
270 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is
271 * not expected to be greater than 31 due to the original published
272 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit
273 * value) - refer perf_event_mmap_page documentation in perf_event.h.
275 if (data->cyc2ns_shift == 32) {
276 data->cyc2ns_shift = 31;
277 data->cyc2ns_mul >>= 1;
280 data->cyc2ns_offset = ns_now -
281 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
283 cyc2ns_write_end(cpu, data);
286 sched_clock_idle_wakeup_event(0);
287 local_irq_restore(flags);
290 * Scheduler clock - returns current time in nanosec units.
292 u64 native_sched_clock(void)
294 if (static_branch_likely(&__use_tsc)) {
295 u64 tsc_now = rdtsc();
297 /* return the value in ns */
298 return cycles_2_ns(tsc_now);
302 * Fall back to jiffies if there's no TSC available:
303 * ( But note that we still use it if the TSC is marked
304 * unstable. We do this because unlike Time Of Day,
305 * the scheduler clock tolerates small errors and it's
306 * very important for it to be as fast as the platform
310 /* No locking but a rare wrong value is not a big deal: */
311 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
315 * Generate a sched_clock if you already have a TSC value.
317 u64 native_sched_clock_from_tsc(u64 tsc)
319 return cycles_2_ns(tsc);
322 /* We need to define a real function for sched_clock, to override the
323 weak default version */
324 #ifdef CONFIG_PARAVIRT
325 unsigned long long sched_clock(void)
327 return paravirt_sched_clock();
331 sched_clock(void) __attribute__((alias("native_sched_clock")));
334 int check_tsc_unstable(void)
338 EXPORT_SYMBOL_GPL(check_tsc_unstable);
340 #ifdef CONFIG_X86_TSC
341 int __init notsc_setup(char *str)
343 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
349 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
352 int __init notsc_setup(char *str)
354 setup_clear_cpu_cap(X86_FEATURE_TSC);
359 __setup("notsc", notsc_setup);
361 static int no_sched_irq_time;
363 static int __init tsc_setup(char *str)
365 if (!strcmp(str, "reliable"))
366 tsc_clocksource_reliable = 1;
367 if (!strncmp(str, "noirqtime", 9))
368 no_sched_irq_time = 1;
372 __setup("tsc=", tsc_setup);
374 #define MAX_RETRIES 5
375 #define SMI_TRESHOLD 50000
378 * Read TSC and the reference counters. Take care of SMI disturbance
380 static u64 tsc_read_refs(u64 *p, int hpet)
385 for (i = 0; i < MAX_RETRIES; i++) {
388 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
390 *p = acpi_pm_read_early();
392 if ((t2 - t1) < SMI_TRESHOLD)
399 * Calculate the TSC frequency from HPET reference
401 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
406 hpet2 += 0x100000000ULL;
408 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
409 do_div(tmp, 1000000);
410 do_div(deltatsc, tmp);
412 return (unsigned long) deltatsc;
416 * Calculate the TSC frequency from PMTimer reference
418 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
426 pm2 += (u64)ACPI_PM_OVRRUN;
428 tmp = pm2 * 1000000000LL;
429 do_div(tmp, PMTMR_TICKS_PER_SEC);
430 do_div(deltatsc, tmp);
432 return (unsigned long) deltatsc;
436 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
437 #define CAL_PIT_LOOPS 1000
440 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
441 #define CAL2_PIT_LOOPS 5000
445 * Try to calibrate the TSC against the Programmable
446 * Interrupt Timer and return the frequency of the TSC
449 * Return ULONG_MAX on failure to calibrate.
451 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
453 u64 tsc, t1, t2, delta;
454 unsigned long tscmin, tscmax;
457 /* Set the Gate high, disable speaker */
458 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
461 * Setup CTC channel 2* for mode 0, (interrupt on terminal
462 * count mode), binary count. Set the latch register to 50ms
463 * (LSB then MSB) to begin countdown.
466 outb(latch & 0xff, 0x42);
467 outb(latch >> 8, 0x42);
469 tsc = t1 = t2 = get_cycles();
474 while ((inb(0x61) & 0x20) == 0) {
478 if ((unsigned long) delta < tscmin)
479 tscmin = (unsigned int) delta;
480 if ((unsigned long) delta > tscmax)
481 tscmax = (unsigned int) delta;
488 * If we were not able to read the PIT more than loopmin
489 * times, then we have been hit by a massive SMI
491 * If the maximum is 10 times larger than the minimum,
492 * then we got hit by an SMI as well.
494 if (pitcnt < loopmin || tscmax > 10 * tscmin)
497 /* Calculate the PIT value */
504 * This reads the current MSB of the PIT counter, and
505 * checks if we are running on sufficiently fast and
506 * non-virtualized hardware.
508 * Our expectations are:
510 * - the PIT is running at roughly 1.19MHz
512 * - each IO is going to take about 1us on real hardware,
513 * but we allow it to be much faster (by a factor of 10) or
514 * _slightly_ slower (ie we allow up to a 2us read+counter
515 * update - anything else implies a unacceptably slow CPU
516 * or PIT for the fast calibration to work.
518 * - with 256 PIT ticks to read the value, we have 214us to
519 * see the same MSB (and overhead like doing a single TSC
520 * read per MSB value etc).
522 * - We're doing 2 reads per loop (LSB, MSB), and we expect
523 * them each to take about a microsecond on real hardware.
524 * So we expect a count value of around 100. But we'll be
525 * generous, and accept anything over 50.
527 * - if the PIT is stuck, and we see *many* more reads, we
528 * return early (and the next caller of pit_expect_msb()
529 * then consider it a failure when they don't see the
530 * next expected value).
532 * These expectations mean that we know that we have seen the
533 * transition from one expected value to another with a fairly
534 * high accuracy, and we didn't miss any events. We can thus
535 * use the TSC value at the transitions to calculate a pretty
536 * good value for the TSC frequencty.
538 static inline int pit_verify_msb(unsigned char val)
542 return inb(0x42) == val;
545 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
548 u64 tsc = 0, prev_tsc = 0;
550 for (count = 0; count < 50000; count++) {
551 if (!pit_verify_msb(val))
556 *deltap = get_cycles() - prev_tsc;
560 * We require _some_ success, but the quality control
561 * will be based on the error terms on the TSC values.
567 * How many MSB values do we want to see? We aim for
568 * a maximum error rate of 500ppm (in practice the
569 * real error is much smaller), but refuse to spend
570 * more than 50ms on it.
572 #define MAX_QUICK_PIT_MS 50
573 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
575 static unsigned long quick_pit_calibrate(void)
579 unsigned long d1, d2;
581 /* Set the Gate high, disable speaker */
582 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
585 * Counter 2, mode 0 (one-shot), binary count
587 * NOTE! Mode 2 decrements by two (and then the
588 * output is flipped each time, giving the same
589 * final output frequency as a decrement-by-one),
590 * so mode 0 is much better when looking at the
595 /* Start at 0xffff */
600 * The PIT starts counting at the next edge, so we
601 * need to delay for a microsecond. The easiest way
602 * to do that is to just read back the 16-bit counter
607 if (pit_expect_msb(0xff, &tsc, &d1)) {
608 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
609 if (!pit_expect_msb(0xff-i, &delta, &d2))
615 * Extrapolate the error and fail fast if the error will
616 * never be below 500 ppm.
619 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
623 * Iterate until the error is less than 500 ppm
625 if (d1+d2 >= delta >> 11)
629 * Check the PIT one more time to verify that
630 * all TSC reads were stable wrt the PIT.
632 * This also guarantees serialization of the
633 * last cycle read ('d2') in pit_expect_msb.
635 if (!pit_verify_msb(0xfe - i))
640 pr_info("Fast TSC calibration failed\n");
645 * Ok, if we get here, then we've seen the
646 * MSB of the PIT decrement 'i' times, and the
647 * error has shrunk to less than 500 ppm.
649 * As a result, we can depend on there not being
650 * any odd delays anywhere, and the TSC reads are
651 * reliable (within the error).
653 * kHz = ticks / time-in-seconds / 1000;
654 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
655 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
657 delta *= PIT_TICK_RATE;
658 do_div(delta, i*256*1000);
659 pr_info("Fast TSC calibration using PIT\n");
664 * native_calibrate_tsc
665 * Determine TSC frequency via CPUID, else return 0.
667 unsigned long native_calibrate_tsc(void)
669 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
670 unsigned int crystal_khz;
672 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
675 if (boot_cpu_data.cpuid_level < 0x15)
678 eax_denominator = ebx_numerator = ecx_hz = edx = 0;
680 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
681 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
683 if (ebx_numerator == 0 || eax_denominator == 0)
686 crystal_khz = ecx_hz / 1000;
688 if (crystal_khz == 0) {
689 switch (boot_cpu_data.x86_model) {
690 case INTEL_FAM6_SKYLAKE_MOBILE:
691 case INTEL_FAM6_SKYLAKE_DESKTOP:
692 case INTEL_FAM6_KABYLAKE_MOBILE:
693 case INTEL_FAM6_KABYLAKE_DESKTOP:
694 crystal_khz = 24000; /* 24.0 MHz */
696 case INTEL_FAM6_SKYLAKE_X:
697 crystal_khz = 25000; /* 25.0 MHz */
699 case INTEL_FAM6_ATOM_GOLDMONT:
700 crystal_khz = 19200; /* 19.2 MHz */
706 * TSC frequency determined by CPUID is a "hardware reported"
707 * frequency and is the most accurate one so far we have. This
708 * is considered a known frequency.
710 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
713 * For Atom SoCs TSC is the only reliable clocksource.
714 * Mark TSC reliable so no watchdog on it.
716 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
717 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
719 return crystal_khz * ebx_numerator / eax_denominator;
722 static unsigned long cpu_khz_from_cpuid(void)
724 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
726 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
729 if (boot_cpu_data.cpuid_level < 0x16)
732 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
734 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
736 return eax_base_mhz * 1000;
740 * native_calibrate_cpu - calibrate the cpu on boot
742 unsigned long native_calibrate_cpu(void)
744 u64 tsc1, tsc2, delta, ref1, ref2;
745 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
746 unsigned long flags, latch, ms, fast_calibrate;
747 int hpet = is_hpet_enabled(), i, loopmin;
749 fast_calibrate = cpu_khz_from_cpuid();
751 return fast_calibrate;
753 fast_calibrate = cpu_khz_from_msr();
755 return fast_calibrate;
757 local_irq_save(flags);
758 fast_calibrate = quick_pit_calibrate();
759 local_irq_restore(flags);
761 return fast_calibrate;
764 * Run 5 calibration loops to get the lowest frequency value
765 * (the best estimate). We use two different calibration modes
768 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
769 * load a timeout of 50ms. We read the time right after we
770 * started the timer and wait until the PIT count down reaches
771 * zero. In each wait loop iteration we read the TSC and check
772 * the delta to the previous read. We keep track of the min
773 * and max values of that delta. The delta is mostly defined
774 * by the IO time of the PIT access, so we can detect when a
775 * SMI/SMM disturbance happened between the two reads. If the
776 * maximum time is significantly larger than the minimum time,
777 * then we discard the result and have another try.
779 * 2) Reference counter. If available we use the HPET or the
780 * PMTIMER as a reference to check the sanity of that value.
781 * We use separate TSC readouts and check inside of the
782 * reference read for a SMI/SMM disturbance. We dicard
783 * disturbed values here as well. We do that around the PIT
784 * calibration delay loop as we have to wait for a certain
785 * amount of time anyway.
788 /* Preset PIT loop values */
791 loopmin = CAL_PIT_LOOPS;
793 for (i = 0; i < 3; i++) {
794 unsigned long tsc_pit_khz;
797 * Read the start value and the reference count of
798 * hpet/pmtimer when available. Then do the PIT
799 * calibration, which will take at least 50ms, and
800 * read the end value.
802 local_irq_save(flags);
803 tsc1 = tsc_read_refs(&ref1, hpet);
804 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
805 tsc2 = tsc_read_refs(&ref2, hpet);
806 local_irq_restore(flags);
808 /* Pick the lowest PIT TSC calibration so far */
809 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
811 /* hpet or pmtimer available ? */
815 /* Check, whether the sampling was disturbed by an SMI */
816 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
819 tsc2 = (tsc2 - tsc1) * 1000000LL;
821 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
823 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
825 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
827 /* Check the reference deviation */
828 delta = ((u64) tsc_pit_min) * 100;
829 do_div(delta, tsc_ref_min);
832 * If both calibration results are inside a 10% window
833 * then we can be sure, that the calibration
834 * succeeded. We break out of the loop right away. We
835 * use the reference value, as it is more precise.
837 if (delta >= 90 && delta <= 110) {
838 pr_info("PIT calibration matches %s. %d loops\n",
839 hpet ? "HPET" : "PMTIMER", i + 1);
844 * Check whether PIT failed more than once. This
845 * happens in virtualized environments. We need to
846 * give the virtual PC a slightly longer timeframe for
847 * the HPET/PMTIMER to make the result precise.
849 if (i == 1 && tsc_pit_min == ULONG_MAX) {
852 loopmin = CAL2_PIT_LOOPS;
857 * Now check the results.
859 if (tsc_pit_min == ULONG_MAX) {
860 /* PIT gave no useful value */
861 pr_warn("Unable to calibrate against PIT\n");
863 /* We don't have an alternative source, disable TSC */
864 if (!hpet && !ref1 && !ref2) {
865 pr_notice("No reference (HPET/PMTIMER) available\n");
869 /* The alternative source failed as well, disable TSC */
870 if (tsc_ref_min == ULONG_MAX) {
871 pr_warn("HPET/PMTIMER calibration failed\n");
875 /* Use the alternative source */
876 pr_info("using %s reference calibration\n",
877 hpet ? "HPET" : "PMTIMER");
882 /* We don't have an alternative source, use the PIT calibration value */
883 if (!hpet && !ref1 && !ref2) {
884 pr_info("Using PIT calibration value\n");
888 /* The alternative source failed, use the PIT calibration value */
889 if (tsc_ref_min == ULONG_MAX) {
890 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
895 * The calibration values differ too much. In doubt, we use
896 * the PIT value as we know that there are PMTIMERs around
897 * running at double speed. At least we let the user know:
899 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
900 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
901 pr_info("Using PIT calibration value\n");
905 int recalibrate_cpu_khz(void)
908 unsigned long cpu_khz_old = cpu_khz;
910 if (!boot_cpu_has(X86_FEATURE_TSC))
913 cpu_khz = x86_platform.calibrate_cpu();
914 tsc_khz = x86_platform.calibrate_tsc();
917 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
919 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
920 cpu_khz_old, cpu_khz);
928 EXPORT_SYMBOL(recalibrate_cpu_khz);
931 static unsigned long long cyc2ns_suspend;
933 void tsc_save_sched_clock_state(void)
935 if (!sched_clock_stable())
938 cyc2ns_suspend = sched_clock();
942 * Even on processors with invariant TSC, TSC gets reset in some the
943 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
944 * arbitrary value (still sync'd across cpu's) during resume from such sleep
945 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
946 * that sched_clock() continues from the point where it was left off during
949 void tsc_restore_sched_clock_state(void)
951 unsigned long long offset;
955 if (!sched_clock_stable())
958 local_irq_save(flags);
961 * We're coming out of suspend, there's no concurrency yet; don't
962 * bother being nice about the RCU stuff, just write to both
966 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
967 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
969 offset = cyc2ns_suspend - sched_clock();
971 for_each_possible_cpu(cpu) {
972 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
973 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
976 local_irq_restore(flags);
979 #ifdef CONFIG_CPU_FREQ
981 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
984 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
985 * not that important because current Opteron setups do not support
986 * scaling on SMP anyroads.
988 * Should fix up last_tsc too. Currently gettimeofday in the
989 * first tick after the change will be slightly wrong.
992 static unsigned int ref_freq;
993 static unsigned long loops_per_jiffy_ref;
994 static unsigned long tsc_khz_ref;
996 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
999 struct cpufreq_freqs *freq = data;
1002 lpj = &boot_cpu_data.loops_per_jiffy;
1004 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1005 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
1009 ref_freq = freq->old;
1010 loops_per_jiffy_ref = *lpj;
1011 tsc_khz_ref = tsc_khz;
1013 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1014 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
1015 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
1017 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
1018 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
1019 mark_tsc_unstable("cpufreq changes");
1021 set_cyc2ns_scale(tsc_khz, freq->cpu);
1027 static struct notifier_block time_cpufreq_notifier_block = {
1028 .notifier_call = time_cpufreq_notifier
1031 static int __init cpufreq_register_tsc_scaling(void)
1033 if (!boot_cpu_has(X86_FEATURE_TSC))
1035 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1037 cpufreq_register_notifier(&time_cpufreq_notifier_block,
1038 CPUFREQ_TRANSITION_NOTIFIER);
1042 core_initcall(cpufreq_register_tsc_scaling);
1044 #endif /* CONFIG_CPU_FREQ */
1046 #define ART_CPUID_LEAF (0x15)
1047 #define ART_MIN_DENOMINATOR (1)
1051 * If ART is present detect the numerator:denominator to convert to TSC
1053 static void detect_art(void)
1055 unsigned int unused[2];
1057 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
1060 /* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */
1061 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
1062 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
1063 !boot_cpu_has(X86_FEATURE_TSC_ADJUST))
1066 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
1067 &art_to_tsc_numerator, unused, unused+1);
1069 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR)
1072 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset);
1074 /* Make this sticky over multiple CPU init calls */
1075 setup_force_cpu_cap(X86_FEATURE_ART);
1079 /* clocksource code */
1081 static struct clocksource clocksource_tsc;
1083 static void tsc_resume(struct clocksource *cs)
1085 tsc_verify_tsc_adjust(true);
1089 * We used to compare the TSC to the cycle_last value in the clocksource
1090 * structure to avoid a nasty time-warp. This can be observed in a
1091 * very small window right after one CPU updated cycle_last under
1092 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1093 * is smaller than the cycle_last reference value due to a TSC which
1094 * is slighty behind. This delta is nowhere else observable, but in
1095 * that case it results in a forward time jump in the range of hours
1096 * due to the unsigned delta calculation of the time keeping core
1097 * code, which is necessary to support wrapping clocksources like pm
1100 * This sanity check is now done in the core timekeeping code.
1101 * checking the result of read_tsc() - cycle_last for being negative.
1102 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
1104 static u64 read_tsc(struct clocksource *cs)
1106 return (u64)rdtsc_ordered();
1110 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
1112 static struct clocksource clocksource_tsc = {
1116 .mask = CLOCKSOURCE_MASK(64),
1117 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
1118 CLOCK_SOURCE_MUST_VERIFY,
1119 .archdata = { .vclock_mode = VCLOCK_TSC },
1120 .resume = tsc_resume,
1123 void mark_tsc_unstable(char *reason)
1125 if (!tsc_unstable) {
1127 clear_sched_clock_stable();
1128 disable_sched_clock_irqtime();
1129 pr_info("Marking TSC unstable due to %s\n", reason);
1130 /* Change only the rating, when not registered */
1131 if (clocksource_tsc.mult)
1132 clocksource_mark_unstable(&clocksource_tsc);
1134 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1135 clocksource_tsc.rating = 0;
1140 EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1142 static void __init check_system_tsc_reliable(void)
1144 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
1145 if (is_geode_lx()) {
1146 /* RTSC counts during suspend */
1147 #define RTSC_SUSP 0x100
1148 unsigned long res_low, res_high;
1150 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1151 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1152 if (res_low & RTSC_SUSP)
1153 tsc_clocksource_reliable = 1;
1156 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1157 tsc_clocksource_reliable = 1;
1161 * Make an educated guess if the TSC is trustworthy and synchronized
1164 int unsynchronized_tsc(void)
1166 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
1170 if (apic_is_clustered_box())
1174 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1177 if (tsc_clocksource_reliable)
1180 * Intel systems are normally all synchronized.
1181 * Exceptions must mark TSC as unstable:
1183 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1184 /* assume multi socket systems are not synchronized: */
1185 if (num_possible_cpus() > 1)
1193 * Convert ART to TSC given numerator/denominator found in detect_art()
1195 struct system_counterval_t convert_art_to_tsc(u64 art)
1199 rem = do_div(art, art_to_tsc_denominator);
1201 res = art * art_to_tsc_numerator;
1202 tmp = rem * art_to_tsc_numerator;
1204 do_div(tmp, art_to_tsc_denominator);
1205 res += tmp + art_to_tsc_offset;
1207 return (struct system_counterval_t) {.cs = art_related_clocksource,
1210 EXPORT_SYMBOL(convert_art_to_tsc);
1212 static void tsc_refine_calibration_work(struct work_struct *work);
1213 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1215 * tsc_refine_calibration_work - Further refine tsc freq calibration
1218 * This functions uses delayed work over a period of a
1219 * second to further refine the TSC freq value. Since this is
1220 * timer based, instead of loop based, we don't block the boot
1221 * process while this longer calibration is done.
1223 * If there are any calibration anomalies (too many SMIs, etc),
1224 * or the refined calibration is off by 1% of the fast early
1225 * calibration, we throw out the new calibration and use the
1226 * early calibration.
1228 static void tsc_refine_calibration_work(struct work_struct *work)
1230 static u64 tsc_start = -1, ref_start;
1232 u64 tsc_stop, ref_stop, delta;
1235 /* Don't bother refining TSC on unstable systems */
1236 if (check_tsc_unstable())
1240 * Since the work is started early in boot, we may be
1241 * delayed the first time we expire. So set the workqueue
1242 * again once we know timers are working.
1244 if (tsc_start == -1) {
1246 * Only set hpet once, to avoid mixing hardware
1247 * if the hpet becomes enabled later.
1249 hpet = is_hpet_enabled();
1250 schedule_delayed_work(&tsc_irqwork, HZ);
1251 tsc_start = tsc_read_refs(&ref_start, hpet);
1255 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1257 /* hpet or pmtimer available ? */
1258 if (ref_start == ref_stop)
1261 /* Check, whether the sampling was disturbed by an SMI */
1262 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1265 delta = tsc_stop - tsc_start;
1268 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1270 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1272 /* Make sure we're within 1% */
1273 if (abs(tsc_khz - freq) > tsc_khz/100)
1277 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1278 (unsigned long)tsc_khz / 1000,
1279 (unsigned long)tsc_khz % 1000);
1281 /* Inform the TSC deadline clockevent devices about the recalibration */
1282 lapic_update_tsc_freq();
1285 if (boot_cpu_has(X86_FEATURE_ART))
1286 art_related_clocksource = &clocksource_tsc;
1287 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1291 static int __init init_tsc_clocksource(void)
1293 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
1296 if (tsc_clocksource_reliable)
1297 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1298 /* lower the rating if we already know its unstable: */
1299 if (check_tsc_unstable()) {
1300 clocksource_tsc.rating = 0;
1301 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1304 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1305 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1308 * When TSC frequency is known (retrieved via MSR or CPUID), we skip
1309 * the refined calibration and directly register it as a clocksource.
1311 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) {
1312 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1316 schedule_delayed_work(&tsc_irqwork, 0);
1320 * We use device_initcall here, to ensure we run after the hpet
1321 * is fully initialized, which may occur at fs_initcall time.
1323 device_initcall(init_tsc_clocksource);
1325 void __init tsc_init(void)
1330 if (!boot_cpu_has(X86_FEATURE_TSC)) {
1331 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1335 cpu_khz = x86_platform.calibrate_cpu();
1336 tsc_khz = x86_platform.calibrate_tsc();
1339 * Trust non-zero tsc_khz as authorative,
1340 * and use it to sanity check cpu_khz,
1341 * which will be off if system timer is off.
1345 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
1349 mark_tsc_unstable("could not calculate TSC khz");
1350 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
1354 pr_info("Detected %lu.%03lu MHz processor\n",
1355 (unsigned long)cpu_khz / 1000,
1356 (unsigned long)cpu_khz % 1000);
1359 * Secondary CPUs do not run through tsc_init(), so set up
1360 * all the scale factors for all CPUs, assuming the same
1361 * speed as the bootup CPU. (cpufreq notifiers will fix this
1362 * up if their speed diverges)
1364 for_each_possible_cpu(cpu) {
1366 set_cyc2ns_scale(tsc_khz, cpu);
1369 if (tsc_disabled > 0)
1372 /* now allow native_sched_clock() to use rdtsc */
1375 static_branch_enable(&__use_tsc);
1377 if (!no_sched_irq_time)
1378 enable_sched_clock_irqtime();
1380 lpj = ((u64)tsc_khz * 1000);
1386 if (unsynchronized_tsc())
1387 mark_tsc_unstable("TSCs unsynchronized");
1389 tsc_store_and_check_tsc_adjust(true);
1391 check_system_tsc_reliable();
1398 * If we have a constant TSC and are using the TSC for the delay loop,
1399 * we can skip clock calibration if another cpu in the same socket has already
1400 * been calibrated. This assumes that CONSTANT_TSC applies to all
1401 * cpus in the socket - this should be a safe assumption.
1403 unsigned long calibrate_delay_is_known(void)
1405 int sibling, cpu = smp_processor_id();
1406 struct cpumask *mask = topology_core_cpumask(cpu);
1408 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1414 sibling = cpumask_any_but(mask, cpu);
1415 if (sibling < nr_cpu_ids)
1416 return cpu_data(sibling).loops_per_jiffy;