1 /******************************************************************************
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 * Copyright (c) 2005 Keir Fraser
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27 #include <linux/stringify.h>
28 #include <asm/debugreg.h>
37 #define OpImplicit 1ull /* No generic decode */
38 #define OpReg 2ull /* Register */
39 #define OpMem 3ull /* Memory */
40 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */
41 #define OpDI 5ull /* ES:DI/EDI/RDI */
42 #define OpMem64 6ull /* Memory, 64-bit */
43 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */
44 #define OpDX 8ull /* DX register */
45 #define OpCL 9ull /* CL register (for shifts) */
46 #define OpImmByte 10ull /* 8-bit sign extended immediate */
47 #define OpOne 11ull /* Implied 1 */
48 #define OpImm 12ull /* Sign extended up to 32-bit immediate */
49 #define OpMem16 13ull /* Memory operand (16-bit). */
50 #define OpMem32 14ull /* Memory operand (32-bit). */
51 #define OpImmU 15ull /* Immediate operand, zero extended */
52 #define OpSI 16ull /* SI/ESI/RSI */
53 #define OpImmFAddr 17ull /* Immediate far address */
54 #define OpMemFAddr 18ull /* Far address in memory */
55 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
56 #define OpES 20ull /* ES */
57 #define OpCS 21ull /* CS */
58 #define OpSS 22ull /* SS */
59 #define OpDS 23ull /* DS */
60 #define OpFS 24ull /* FS */
61 #define OpGS 25ull /* GS */
62 #define OpMem8 26ull /* 8-bit zero extended memory operand */
63 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */
64 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */
65 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */
66 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */
68 #define OpBits 5 /* Width of operand field */
69 #define OpMask ((1ull << OpBits) - 1)
72 * Opcode effective-address decode tables.
73 * Note that we only emulate instructions that have at least one memory
74 * operand (excluding implicit stack references). We assume that stack
75 * references and instruction fetches will never occur in special memory
76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
80 /* Operand sizes: 8-bit operands or specified/overridden size. */
81 #define ByteOp (1<<0) /* 8-bit operands. */
82 /* Destination operand type. */
84 #define ImplicitOps (OpImplicit << DstShift)
85 #define DstReg (OpReg << DstShift)
86 #define DstMem (OpMem << DstShift)
87 #define DstAcc (OpAcc << DstShift)
88 #define DstDI (OpDI << DstShift)
89 #define DstMem64 (OpMem64 << DstShift)
90 #define DstMem16 (OpMem16 << DstShift)
91 #define DstImmUByte (OpImmUByte << DstShift)
92 #define DstDX (OpDX << DstShift)
93 #define DstAccLo (OpAccLo << DstShift)
94 #define DstMask (OpMask << DstShift)
95 /* Source operand type. */
97 #define SrcNone (OpNone << SrcShift)
98 #define SrcReg (OpReg << SrcShift)
99 #define SrcMem (OpMem << SrcShift)
100 #define SrcMem16 (OpMem16 << SrcShift)
101 #define SrcMem32 (OpMem32 << SrcShift)
102 #define SrcImm (OpImm << SrcShift)
103 #define SrcImmByte (OpImmByte << SrcShift)
104 #define SrcOne (OpOne << SrcShift)
105 #define SrcImmUByte (OpImmUByte << SrcShift)
106 #define SrcImmU (OpImmU << SrcShift)
107 #define SrcSI (OpSI << SrcShift)
108 #define SrcXLat (OpXLat << SrcShift)
109 #define SrcImmFAddr (OpImmFAddr << SrcShift)
110 #define SrcMemFAddr (OpMemFAddr << SrcShift)
111 #define SrcAcc (OpAcc << SrcShift)
112 #define SrcImmU16 (OpImmU16 << SrcShift)
113 #define SrcImm64 (OpImm64 << SrcShift)
114 #define SrcDX (OpDX << SrcShift)
115 #define SrcMem8 (OpMem8 << SrcShift)
116 #define SrcAccHi (OpAccHi << SrcShift)
117 #define SrcMask (OpMask << SrcShift)
118 #define BitOp (1<<11)
119 #define MemAbs (1<<12) /* Memory operand is absolute displacement */
120 #define String (1<<13) /* String instruction (rep capable) */
121 #define Stack (1<<14) /* Stack instruction (push/pop) */
122 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */
123 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */
124 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */
125 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */
126 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */
127 #define Escape (5<<15) /* Escape to coprocessor instruction */
128 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */
129 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */
130 #define Sse (1<<18) /* SSE Vector instruction */
131 /* Generic ModRM decode. */
132 #define ModRM (1<<19)
133 /* Destination is only written; never read. */
136 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
137 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
138 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
139 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
140 #define Undefined (1<<25) /* No Such Instruction */
141 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
142 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
144 #define PageTable (1 << 29) /* instruction used to write page table */
145 #define NotImpl (1 << 30) /* instruction is not implemented */
146 /* Source 2 operand type */
147 #define Src2Shift (31)
148 #define Src2None (OpNone << Src2Shift)
149 #define Src2Mem (OpMem << Src2Shift)
150 #define Src2CL (OpCL << Src2Shift)
151 #define Src2ImmByte (OpImmByte << Src2Shift)
152 #define Src2One (OpOne << Src2Shift)
153 #define Src2Imm (OpImm << Src2Shift)
154 #define Src2ES (OpES << Src2Shift)
155 #define Src2CS (OpCS << Src2Shift)
156 #define Src2SS (OpSS << Src2Shift)
157 #define Src2DS (OpDS << Src2Shift)
158 #define Src2FS (OpFS << Src2Shift)
159 #define Src2GS (OpGS << Src2Shift)
160 #define Src2Mask (OpMask << Src2Shift)
161 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */
162 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */
163 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */
164 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */
165 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */
166 #define NoWrite ((u64)1 << 45) /* No writeback */
167 #define SrcWrite ((u64)1 << 46) /* Write back src operand */
168 #define NoMod ((u64)1 << 47) /* Mod field is ignored */
169 #define Intercept ((u64)1 << 48) /* Has valid intercept field */
170 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */
171 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */
172 #define NearBranch ((u64)1 << 52) /* Near branches */
173 #define No16 ((u64)1 << 53) /* No 16 bit operand */
174 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */
176 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite)
178 #define X2(x...) x, x
179 #define X3(x...) X2(x), x
180 #define X4(x...) X2(x), X2(x)
181 #define X5(x...) X4(x), x
182 #define X6(x...) X4(x), X2(x)
183 #define X7(x...) X4(x), X3(x)
184 #define X8(x...) X4(x), X4(x)
185 #define X16(x...) X8(x), X8(x)
187 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
188 #define FASTOP_SIZE 8
191 * fastop functions have a special calling convention:
196 * flags: rflags (in/out)
197 * ex: rsi (in:fastop pointer, out:zero if exception)
199 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
200 * different operand sizes can be reached by calculation, rather than a jump
201 * table (which would be bigger than the code).
203 * fastop functions are declared as taking a never-defined fastop parameter,
204 * so they can't be called from C directly.
213 int (*execute)(struct x86_emulate_ctxt *ctxt);
214 const struct opcode *group;
215 const struct group_dual *gdual;
216 const struct gprefix *gprefix;
217 const struct escape *esc;
218 const struct instr_dual *idual;
219 const struct mode_dual *mdual;
220 void (*fastop)(struct fastop *fake);
222 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
226 struct opcode mod012[8];
227 struct opcode mod3[8];
231 struct opcode pfx_no;
232 struct opcode pfx_66;
233 struct opcode pfx_f2;
234 struct opcode pfx_f3;
239 struct opcode high[64];
243 struct opcode mod012;
248 struct opcode mode32;
249 struct opcode mode64;
252 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
254 enum x86_transfer_type {
256 X86_TRANSFER_CALL_JMP,
258 X86_TRANSFER_TASK_SWITCH,
261 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
263 if (!(ctxt->regs_valid & (1 << nr))) {
264 ctxt->regs_valid |= 1 << nr;
265 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
267 return ctxt->_regs[nr];
270 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
272 ctxt->regs_valid |= 1 << nr;
273 ctxt->regs_dirty |= 1 << nr;
274 return &ctxt->_regs[nr];
277 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
280 return reg_write(ctxt, nr);
283 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
287 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
288 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
291 static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
293 ctxt->regs_dirty = 0;
294 ctxt->regs_valid = 0;
298 * These EFLAGS bits are restored from saved value during emulation, and
299 * any changes are written back to the saved value after emulation.
301 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
302 X86_EFLAGS_PF|X86_EFLAGS_CF)
310 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
312 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
313 #define FOP_RET "ret \n\t"
315 #define FOP_START(op) \
316 extern void em_##op(struct fastop *fake); \
317 asm(".pushsection .text, \"ax\" \n\t" \
318 ".global em_" #op " \n\t" \
325 #define FOPNOP() FOP_ALIGN FOP_RET
327 #define FOP1E(op, dst) \
328 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
330 #define FOP1EEX(op, dst) \
331 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
333 #define FASTOP1(op) \
338 ON64(FOP1E(op##q, rax)) \
341 /* 1-operand, using src2 (for MUL/DIV r/m) */
342 #define FASTOP1SRC2(op, name) \
347 ON64(FOP1E(op, rcx)) \
350 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
351 #define FASTOP1SRC2EX(op, name) \
356 ON64(FOP1EEX(op, rcx)) \
359 #define FOP2E(op, dst, src) \
360 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
362 #define FASTOP2(op) \
364 FOP2E(op##b, al, dl) \
365 FOP2E(op##w, ax, dx) \
366 FOP2E(op##l, eax, edx) \
367 ON64(FOP2E(op##q, rax, rdx)) \
370 /* 2 operand, word only */
371 #define FASTOP2W(op) \
374 FOP2E(op##w, ax, dx) \
375 FOP2E(op##l, eax, edx) \
376 ON64(FOP2E(op##q, rax, rdx)) \
379 /* 2 operand, src is CL */
380 #define FASTOP2CL(op) \
382 FOP2E(op##b, al, cl) \
383 FOP2E(op##w, ax, cl) \
384 FOP2E(op##l, eax, cl) \
385 ON64(FOP2E(op##q, rax, cl)) \
388 /* 2 operand, src and dest are reversed */
389 #define FASTOP2R(op, name) \
391 FOP2E(op##b, dl, al) \
392 FOP2E(op##w, dx, ax) \
393 FOP2E(op##l, edx, eax) \
394 ON64(FOP2E(op##q, rdx, rax)) \
397 #define FOP3E(op, dst, src, src2) \
398 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
400 /* 3-operand, word-only, src2=cl */
401 #define FASTOP3WCL(op) \
404 FOP3E(op##w, ax, dx, cl) \
405 FOP3E(op##l, eax, edx, cl) \
406 ON64(FOP3E(op##q, rax, rdx, cl)) \
409 /* Special case for SETcc - 1 instruction per cc */
410 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
412 asm(".global kvm_fastop_exception \n"
413 "kvm_fastop_exception: xor %esi, %esi; ret");
434 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
437 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
438 enum x86_intercept intercept,
439 enum x86_intercept_stage stage)
441 struct x86_instruction_info info = {
442 .intercept = intercept,
443 .rep_prefix = ctxt->rep_prefix,
444 .modrm_mod = ctxt->modrm_mod,
445 .modrm_reg = ctxt->modrm_reg,
446 .modrm_rm = ctxt->modrm_rm,
447 .src_val = ctxt->src.val64,
448 .dst_val = ctxt->dst.val64,
449 .src_bytes = ctxt->src.bytes,
450 .dst_bytes = ctxt->dst.bytes,
451 .ad_bytes = ctxt->ad_bytes,
452 .next_rip = ctxt->eip,
455 return ctxt->ops->intercept(ctxt, &info, stage);
458 static void assign_masked(ulong *dest, ulong src, ulong mask)
460 *dest = (*dest & ~mask) | (src & mask);
463 static void assign_register(unsigned long *reg, u64 val, int bytes)
465 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
468 *(u8 *)reg = (u8)val;
471 *(u16 *)reg = (u16)val;
475 break; /* 64b: zero-extend */
482 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
484 return (1UL << (ctxt->ad_bytes << 3)) - 1;
487 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
490 struct desc_struct ss;
492 if (ctxt->mode == X86EMUL_MODE_PROT64)
494 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
495 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */
498 static int stack_size(struct x86_emulate_ctxt *ctxt)
500 return (__fls(stack_mask(ctxt)) + 1) >> 3;
503 /* Access/update address held in a register, based on addressing mode. */
504 static inline unsigned long
505 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
507 if (ctxt->ad_bytes == sizeof(unsigned long))
510 return reg & ad_mask(ctxt);
513 static inline unsigned long
514 register_address(struct x86_emulate_ctxt *ctxt, int reg)
516 return address_mask(ctxt, reg_read(ctxt, reg));
519 static void masked_increment(ulong *reg, ulong mask, int inc)
521 assign_masked(reg, *reg + inc, mask);
525 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
527 ulong *preg = reg_rmw(ctxt, reg);
529 assign_register(preg, *preg + inc, ctxt->ad_bytes);
532 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
534 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
537 static u32 desc_limit_scaled(struct desc_struct *desc)
539 u32 limit = get_desc_limit(desc);
541 return desc->g ? (limit << 12) | 0xfff : limit;
544 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
546 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
549 return ctxt->ops->get_cached_segment_base(ctxt, seg);
552 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
553 u32 error, bool valid)
556 ctxt->exception.vector = vec;
557 ctxt->exception.error_code = error;
558 ctxt->exception.error_code_valid = valid;
559 return X86EMUL_PROPAGATE_FAULT;
562 static int emulate_db(struct x86_emulate_ctxt *ctxt)
564 return emulate_exception(ctxt, DB_VECTOR, 0, false);
567 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
569 return emulate_exception(ctxt, GP_VECTOR, err, true);
572 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
574 return emulate_exception(ctxt, SS_VECTOR, err, true);
577 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
579 return emulate_exception(ctxt, UD_VECTOR, 0, false);
582 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
584 return emulate_exception(ctxt, TS_VECTOR, err, true);
587 static int emulate_de(struct x86_emulate_ctxt *ctxt)
589 return emulate_exception(ctxt, DE_VECTOR, 0, false);
592 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
594 return emulate_exception(ctxt, NM_VECTOR, 0, false);
597 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
600 struct desc_struct desc;
602 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
606 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
611 struct desc_struct desc;
613 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
614 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
618 * x86 defines three classes of vector instructions: explicitly
619 * aligned, explicitly unaligned, and the rest, which change behaviour
620 * depending on whether they're AVX encoded or not.
622 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
623 * subject to the same check.
625 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
627 if (likely(size < 16))
630 if (ctxt->d & Aligned)
632 else if (ctxt->d & Unaligned)
634 else if (ctxt->d & Avx)
640 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
641 struct segmented_address addr,
642 unsigned *max_size, unsigned size,
643 bool write, bool fetch,
644 enum x86emul_mode mode, ulong *linear)
646 struct desc_struct desc;
652 la = seg_base(ctxt, addr.seg) + addr.ea;
655 case X86EMUL_MODE_PROT64:
656 if (is_noncanonical_address(la))
659 *max_size = min_t(u64, ~0u, (1ull << 48) - la);
660 if (size > *max_size)
664 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
668 /* code segment in protected mode or read-only data segment */
669 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
670 || !(desc.type & 2)) && write)
672 /* unreadable code segment */
673 if (!fetch && (desc.type & 8) && !(desc.type & 2))
675 lim = desc_limit_scaled(&desc);
676 if (!(desc.type & 8) && (desc.type & 4)) {
677 /* expand-down segment */
680 lim = desc.d ? 0xffffffff : 0xffff;
684 if (lim == 0xffffffff)
687 *max_size = (u64)lim + 1 - addr.ea;
688 if (size > *max_size)
694 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
695 return emulate_gp(ctxt, 0);
697 return X86EMUL_CONTINUE;
699 if (addr.seg == VCPU_SREG_SS)
700 return emulate_ss(ctxt, 0);
702 return emulate_gp(ctxt, 0);
705 static int linearize(struct x86_emulate_ctxt *ctxt,
706 struct segmented_address addr,
707 unsigned size, bool write,
711 return __linearize(ctxt, addr, &max_size, size, write, false,
715 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
716 enum x86emul_mode mode)
721 struct segmented_address addr = { .seg = VCPU_SREG_CS,
724 if (ctxt->op_bytes != sizeof(unsigned long))
725 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
726 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
727 if (rc == X86EMUL_CONTINUE)
728 ctxt->_eip = addr.ea;
732 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
734 return assign_eip(ctxt, dst, ctxt->mode);
737 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
738 const struct desc_struct *cs_desc)
740 enum x86emul_mode mode = ctxt->mode;
744 if (ctxt->mode >= X86EMUL_MODE_PROT16) {
748 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
750 mode = X86EMUL_MODE_PROT64;
752 mode = X86EMUL_MODE_PROT32; /* temporary value */
755 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
756 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
757 rc = assign_eip(ctxt, dst, mode);
758 if (rc == X86EMUL_CONTINUE)
763 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
765 return assign_eip_near(ctxt, ctxt->_eip + rel);
768 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
769 struct segmented_address addr,
776 rc = linearize(ctxt, addr, size, false, &linear);
777 if (rc != X86EMUL_CONTINUE)
779 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
783 * Prefetch the remaining bytes of the instruction without crossing page
784 * boundary if they are not in fetch_cache yet.
786 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
789 unsigned size, max_size;
790 unsigned long linear;
791 int cur_size = ctxt->fetch.end - ctxt->fetch.data;
792 struct segmented_address addr = { .seg = VCPU_SREG_CS,
793 .ea = ctxt->eip + cur_size };
796 * We do not know exactly how many bytes will be needed, and
797 * __linearize is expensive, so fetch as much as possible. We
798 * just have to avoid going beyond the 15 byte limit, the end
799 * of the segment, or the end of the page.
801 * __linearize is called with size 0 so that it does not do any
802 * boundary check itself. Instead, we use max_size to check
805 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
807 if (unlikely(rc != X86EMUL_CONTINUE))
810 size = min_t(unsigned, 15UL ^ cur_size, max_size);
811 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
814 * One instruction can only straddle two pages,
815 * and one has been loaded at the beginning of
816 * x86_decode_insn. So, if not enough bytes
817 * still, we must have hit the 15-byte boundary.
819 if (unlikely(size < op_size))
820 return emulate_gp(ctxt, 0);
822 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
823 size, &ctxt->exception);
824 if (unlikely(rc != X86EMUL_CONTINUE))
826 ctxt->fetch.end += size;
827 return X86EMUL_CONTINUE;
830 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
833 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
835 if (unlikely(done_size < size))
836 return __do_insn_fetch_bytes(ctxt, size - done_size);
838 return X86EMUL_CONTINUE;
841 /* Fetch next part of the instruction being emulated. */
842 #define insn_fetch(_type, _ctxt) \
845 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \
846 if (rc != X86EMUL_CONTINUE) \
848 ctxt->_eip += sizeof(_type); \
849 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \
850 ctxt->fetch.ptr += sizeof(_type); \
854 #define insn_fetch_arr(_arr, _size, _ctxt) \
856 rc = do_insn_fetch_bytes(_ctxt, _size); \
857 if (rc != X86EMUL_CONTINUE) \
859 ctxt->_eip += (_size); \
860 memcpy(_arr, ctxt->fetch.ptr, _size); \
861 ctxt->fetch.ptr += (_size); \
865 * Given the 'reg' portion of a ModRM byte, and a register block, return a
866 * pointer into the block that addresses the relevant register.
867 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
869 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
873 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
875 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
876 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
878 p = reg_rmw(ctxt, modrm_reg);
882 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
883 struct segmented_address addr,
884 u16 *size, unsigned long *address, int op_bytes)
891 rc = segmented_read_std(ctxt, addr, size, 2);
892 if (rc != X86EMUL_CONTINUE)
895 rc = segmented_read_std(ctxt, addr, address, op_bytes);
909 FASTOP1SRC2(mul, mul_ex);
910 FASTOP1SRC2(imul, imul_ex);
911 FASTOP1SRC2EX(div, div_ex);
912 FASTOP1SRC2EX(idiv, idiv_ex);
941 FASTOP2R(cmp, cmp_r);
943 static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
945 /* If src is zero, do not writeback, but update flags */
946 if (ctxt->src.val == 0)
947 ctxt->dst.type = OP_NONE;
948 return fastop(ctxt, em_bsf);
951 static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
953 /* If src is zero, do not writeback, but update flags */
954 if (ctxt->src.val == 0)
955 ctxt->dst.type = OP_NONE;
956 return fastop(ctxt, em_bsr);
959 static u8 test_cc(unsigned int condition, unsigned long flags)
962 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
964 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
965 asm("push %[flags]; popf; call *%[fastop]"
966 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
970 static void fetch_register_operand(struct operand *op)
974 op->val = *(u8 *)op->addr.reg;
977 op->val = *(u16 *)op->addr.reg;
980 op->val = *(u32 *)op->addr.reg;
983 op->val = *(u64 *)op->addr.reg;
988 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
990 ctxt->ops->get_fpu(ctxt);
992 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
993 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
994 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
995 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
996 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
997 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
998 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
999 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1000 #ifdef CONFIG_X86_64
1001 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1002 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1003 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1004 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1005 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1006 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1007 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1008 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1012 ctxt->ops->put_fpu(ctxt);
1015 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1018 ctxt->ops->get_fpu(ctxt);
1020 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1021 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1022 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1023 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1024 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1025 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1026 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1027 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1028 #ifdef CONFIG_X86_64
1029 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1030 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1031 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1032 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1033 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1034 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1035 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1036 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1040 ctxt->ops->put_fpu(ctxt);
1043 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1045 ctxt->ops->get_fpu(ctxt);
1047 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1048 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1049 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1050 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1051 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1052 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1053 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1054 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1057 ctxt->ops->put_fpu(ctxt);
1060 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1062 ctxt->ops->get_fpu(ctxt);
1064 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1065 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1066 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1067 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1068 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1069 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1070 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1071 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1074 ctxt->ops->put_fpu(ctxt);
1077 static int em_fninit(struct x86_emulate_ctxt *ctxt)
1079 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1080 return emulate_nm(ctxt);
1082 ctxt->ops->get_fpu(ctxt);
1083 asm volatile("fninit");
1084 ctxt->ops->put_fpu(ctxt);
1085 return X86EMUL_CONTINUE;
1088 static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1092 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1093 return emulate_nm(ctxt);
1095 ctxt->ops->get_fpu(ctxt);
1096 asm volatile("fnstcw %0": "+m"(fcw));
1097 ctxt->ops->put_fpu(ctxt);
1099 ctxt->dst.val = fcw;
1101 return X86EMUL_CONTINUE;
1104 static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1108 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1109 return emulate_nm(ctxt);
1111 ctxt->ops->get_fpu(ctxt);
1112 asm volatile("fnstsw %0": "+m"(fsw));
1113 ctxt->ops->put_fpu(ctxt);
1115 ctxt->dst.val = fsw;
1117 return X86EMUL_CONTINUE;
1120 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1123 unsigned reg = ctxt->modrm_reg;
1125 if (!(ctxt->d & ModRM))
1126 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1128 if (ctxt->d & Sse) {
1132 read_sse_reg(ctxt, &op->vec_val, reg);
1135 if (ctxt->d & Mmx) {
1144 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1145 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1147 fetch_register_operand(op);
1148 op->orig_val = op->val;
1151 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1153 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1154 ctxt->modrm_seg = VCPU_SREG_SS;
1157 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1161 int index_reg, base_reg, scale;
1162 int rc = X86EMUL_CONTINUE;
1165 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1166 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1167 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1169 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1170 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1171 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1172 ctxt->modrm_seg = VCPU_SREG_DS;
1174 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1176 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1177 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1179 if (ctxt->d & Sse) {
1182 op->addr.xmm = ctxt->modrm_rm;
1183 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1186 if (ctxt->d & Mmx) {
1189 op->addr.mm = ctxt->modrm_rm & 7;
1192 fetch_register_operand(op);
1198 if (ctxt->ad_bytes == 2) {
1199 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1200 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1201 unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1202 unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1204 /* 16-bit ModR/M decode. */
1205 switch (ctxt->modrm_mod) {
1207 if (ctxt->modrm_rm == 6)
1208 modrm_ea += insn_fetch(u16, ctxt);
1211 modrm_ea += insn_fetch(s8, ctxt);
1214 modrm_ea += insn_fetch(u16, ctxt);
1217 switch (ctxt->modrm_rm) {
1219 modrm_ea += bx + si;
1222 modrm_ea += bx + di;
1225 modrm_ea += bp + si;
1228 modrm_ea += bp + di;
1237 if (ctxt->modrm_mod != 0)
1244 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1245 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1246 ctxt->modrm_seg = VCPU_SREG_SS;
1247 modrm_ea = (u16)modrm_ea;
1249 /* 32/64-bit ModR/M decode. */
1250 if ((ctxt->modrm_rm & 7) == 4) {
1251 sib = insn_fetch(u8, ctxt);
1252 index_reg |= (sib >> 3) & 7;
1253 base_reg |= sib & 7;
1256 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1257 modrm_ea += insn_fetch(s32, ctxt);
1259 modrm_ea += reg_read(ctxt, base_reg);
1260 adjust_modrm_seg(ctxt, base_reg);
1261 /* Increment ESP on POP [ESP] */
1262 if ((ctxt->d & IncSP) &&
1263 base_reg == VCPU_REGS_RSP)
1264 modrm_ea += ctxt->op_bytes;
1267 modrm_ea += reg_read(ctxt, index_reg) << scale;
1268 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1269 modrm_ea += insn_fetch(s32, ctxt);
1270 if (ctxt->mode == X86EMUL_MODE_PROT64)
1271 ctxt->rip_relative = 1;
1273 base_reg = ctxt->modrm_rm;
1274 modrm_ea += reg_read(ctxt, base_reg);
1275 adjust_modrm_seg(ctxt, base_reg);
1277 switch (ctxt->modrm_mod) {
1279 modrm_ea += insn_fetch(s8, ctxt);
1282 modrm_ea += insn_fetch(s32, ctxt);
1286 op->addr.mem.ea = modrm_ea;
1287 if (ctxt->ad_bytes != 8)
1288 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1294 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1297 int rc = X86EMUL_CONTINUE;
1300 switch (ctxt->ad_bytes) {
1302 op->addr.mem.ea = insn_fetch(u16, ctxt);
1305 op->addr.mem.ea = insn_fetch(u32, ctxt);
1308 op->addr.mem.ea = insn_fetch(u64, ctxt);
1315 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1319 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1320 mask = ~((long)ctxt->dst.bytes * 8 - 1);
1322 if (ctxt->src.bytes == 2)
1323 sv = (s16)ctxt->src.val & (s16)mask;
1324 else if (ctxt->src.bytes == 4)
1325 sv = (s32)ctxt->src.val & (s32)mask;
1327 sv = (s64)ctxt->src.val & (s64)mask;
1329 ctxt->dst.addr.mem.ea = address_mask(ctxt,
1330 ctxt->dst.addr.mem.ea + (sv >> 3));
1333 /* only subword offset */
1334 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1337 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1338 unsigned long addr, void *dest, unsigned size)
1341 struct read_cache *mc = &ctxt->mem_read;
1343 if (mc->pos < mc->end)
1346 WARN_ON((mc->end + size) >= sizeof(mc->data));
1348 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1350 if (rc != X86EMUL_CONTINUE)
1356 memcpy(dest, mc->data + mc->pos, size);
1358 return X86EMUL_CONTINUE;
1361 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1362 struct segmented_address addr,
1369 rc = linearize(ctxt, addr, size, false, &linear);
1370 if (rc != X86EMUL_CONTINUE)
1372 return read_emulated(ctxt, linear, data, size);
1375 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1376 struct segmented_address addr,
1383 rc = linearize(ctxt, addr, size, true, &linear);
1384 if (rc != X86EMUL_CONTINUE)
1386 return ctxt->ops->write_emulated(ctxt, linear, data, size,
1390 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1391 struct segmented_address addr,
1392 const void *orig_data, const void *data,
1398 rc = linearize(ctxt, addr, size, true, &linear);
1399 if (rc != X86EMUL_CONTINUE)
1401 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1402 size, &ctxt->exception);
1405 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1406 unsigned int size, unsigned short port,
1409 struct read_cache *rc = &ctxt->io_read;
1411 if (rc->pos == rc->end) { /* refill pio read ahead */
1412 unsigned int in_page, n;
1413 unsigned int count = ctxt->rep_prefix ?
1414 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1415 in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
1416 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1417 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1418 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1421 rc->pos = rc->end = 0;
1422 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1427 if (ctxt->rep_prefix && (ctxt->d & String) &&
1428 !(ctxt->eflags & X86_EFLAGS_DF)) {
1429 ctxt->dst.data = rc->data + rc->pos;
1430 ctxt->dst.type = OP_MEM_STR;
1431 ctxt->dst.count = (rc->end - rc->pos) / size;
1434 memcpy(dest, rc->data + rc->pos, size);
1440 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1441 u16 index, struct desc_struct *desc)
1446 ctxt->ops->get_idt(ctxt, &dt);
1448 if (dt.size < index * 8 + 7)
1449 return emulate_gp(ctxt, index << 3 | 0x2);
1451 addr = dt.address + index * 8;
1452 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1456 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1457 u16 selector, struct desc_ptr *dt)
1459 const struct x86_emulate_ops *ops = ctxt->ops;
1462 if (selector & 1 << 2) {
1463 struct desc_struct desc;
1466 memset (dt, 0, sizeof *dt);
1467 if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1471 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1472 dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1474 ops->get_gdt(ctxt, dt);
1477 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1478 u16 selector, ulong *desc_addr_p)
1481 u16 index = selector >> 3;
1484 get_descriptor_table_ptr(ctxt, selector, &dt);
1486 if (dt.size < index * 8 + 7)
1487 return emulate_gp(ctxt, selector & 0xfffc);
1489 addr = dt.address + index * 8;
1491 #ifdef CONFIG_X86_64
1492 if (addr >> 32 != 0) {
1495 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1496 if (!(efer & EFER_LMA))
1501 *desc_addr_p = addr;
1502 return X86EMUL_CONTINUE;
1505 /* allowed just for 8 bytes segments */
1506 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1507 u16 selector, struct desc_struct *desc,
1512 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1513 if (rc != X86EMUL_CONTINUE)
1516 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
1520 /* allowed just for 8 bytes segments */
1521 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1522 u16 selector, struct desc_struct *desc)
1527 rc = get_descriptor_ptr(ctxt, selector, &addr);
1528 if (rc != X86EMUL_CONTINUE)
1531 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1535 /* Does not support long mode */
1536 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1537 u16 selector, int seg, u8 cpl,
1538 enum x86_transfer_type transfer,
1539 struct desc_struct *desc)
1541 struct desc_struct seg_desc, old_desc;
1543 unsigned err_vec = GP_VECTOR;
1545 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1551 memset(&seg_desc, 0, sizeof seg_desc);
1553 if (ctxt->mode == X86EMUL_MODE_REAL) {
1554 /* set real mode segment descriptor (keep limit etc. for
1556 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1557 set_desc_base(&seg_desc, selector << 4);
1559 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1560 /* VM86 needs a clean new segment descriptor */
1561 set_desc_base(&seg_desc, selector << 4);
1562 set_desc_limit(&seg_desc, 0xffff);
1572 /* NULL selector is not valid for TR, CS and SS (except for long mode) */
1573 if ((seg == VCPU_SREG_CS
1574 || (seg == VCPU_SREG_SS
1575 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
1576 || seg == VCPU_SREG_TR)
1580 /* TR should be in GDT only */
1581 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1584 if (null_selector) /* for NULL selector skip all following checks */
1587 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1588 if (ret != X86EMUL_CONTINUE)
1591 err_code = selector & 0xfffc;
1592 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1595 /* can't load system descriptor into segment selector */
1596 if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1597 if (transfer == X86_TRANSFER_CALL_JMP)
1598 return X86EMUL_UNHANDLEABLE;
1603 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1612 * segment is not a writable data segment or segment
1613 * selector's RPL != CPL or segment selector's RPL != CPL
1615 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1619 if (!(seg_desc.type & 8))
1622 if (seg_desc.type & 4) {
1628 if (rpl > cpl || dpl != cpl)
1631 /* in long-mode d/b must be clear if l is set */
1632 if (seg_desc.d && seg_desc.l) {
1635 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1636 if (efer & EFER_LMA)
1640 /* CS(RPL) <- CPL */
1641 selector = (selector & 0xfffc) | cpl;
1644 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1646 old_desc = seg_desc;
1647 seg_desc.type |= 2; /* busy */
1648 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1649 sizeof(seg_desc), &ctxt->exception);
1650 if (ret != X86EMUL_CONTINUE)
1653 case VCPU_SREG_LDTR:
1654 if (seg_desc.s || seg_desc.type != 2)
1657 default: /* DS, ES, FS, or GS */
1659 * segment is not a data or readable code segment or
1660 * ((segment is a data or nonconforming code segment)
1661 * and (both RPL and CPL > DPL))
1663 if ((seg_desc.type & 0xa) == 0x8 ||
1664 (((seg_desc.type & 0xc) != 0xc) &&
1665 (rpl > dpl && cpl > dpl)))
1671 /* mark segment as accessed */
1672 if (!(seg_desc.type & 1)) {
1674 ret = write_segment_descriptor(ctxt, selector,
1676 if (ret != X86EMUL_CONTINUE)
1679 } else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1680 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1681 sizeof(base3), &ctxt->exception);
1682 if (ret != X86EMUL_CONTINUE)
1684 if (is_noncanonical_address(get_desc_base(&seg_desc) |
1685 ((u64)base3 << 32)))
1686 return emulate_gp(ctxt, 0);
1689 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1692 return X86EMUL_CONTINUE;
1694 return emulate_exception(ctxt, err_vec, err_code, true);
1697 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1698 u16 selector, int seg)
1700 u8 cpl = ctxt->ops->cpl(ctxt);
1701 return __load_segment_descriptor(ctxt, selector, seg, cpl,
1702 X86_TRANSFER_NONE, NULL);
1705 static void write_register_operand(struct operand *op)
1707 return assign_register(op->addr.reg, op->val, op->bytes);
1710 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1714 write_register_operand(op);
1717 if (ctxt->lock_prefix)
1718 return segmented_cmpxchg(ctxt,
1724 return segmented_write(ctxt,
1730 return segmented_write(ctxt,
1733 op->bytes * op->count);
1736 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1739 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1747 return X86EMUL_CONTINUE;
1750 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1752 struct segmented_address addr;
1754 rsp_increment(ctxt, -bytes);
1755 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1756 addr.seg = VCPU_SREG_SS;
1758 return segmented_write(ctxt, addr, data, bytes);
1761 static int em_push(struct x86_emulate_ctxt *ctxt)
1763 /* Disable writeback. */
1764 ctxt->dst.type = OP_NONE;
1765 return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1768 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1769 void *dest, int len)
1772 struct segmented_address addr;
1774 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1775 addr.seg = VCPU_SREG_SS;
1776 rc = segmented_read(ctxt, addr, dest, len);
1777 if (rc != X86EMUL_CONTINUE)
1780 rsp_increment(ctxt, len);
1784 static int em_pop(struct x86_emulate_ctxt *ctxt)
1786 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1789 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1790 void *dest, int len)
1793 unsigned long val, change_mask;
1794 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
1795 int cpl = ctxt->ops->cpl(ctxt);
1797 rc = emulate_pop(ctxt, &val, len);
1798 if (rc != X86EMUL_CONTINUE)
1801 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1802 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1803 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1804 X86_EFLAGS_AC | X86_EFLAGS_ID;
1806 switch(ctxt->mode) {
1807 case X86EMUL_MODE_PROT64:
1808 case X86EMUL_MODE_PROT32:
1809 case X86EMUL_MODE_PROT16:
1811 change_mask |= X86_EFLAGS_IOPL;
1813 change_mask |= X86_EFLAGS_IF;
1815 case X86EMUL_MODE_VM86:
1817 return emulate_gp(ctxt, 0);
1818 change_mask |= X86_EFLAGS_IF;
1820 default: /* real mode */
1821 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
1825 *(unsigned long *)dest =
1826 (ctxt->eflags & ~change_mask) | (val & change_mask);
1831 static int em_popf(struct x86_emulate_ctxt *ctxt)
1833 ctxt->dst.type = OP_REG;
1834 ctxt->dst.addr.reg = &ctxt->eflags;
1835 ctxt->dst.bytes = ctxt->op_bytes;
1836 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1839 static int em_enter(struct x86_emulate_ctxt *ctxt)
1842 unsigned frame_size = ctxt->src.val;
1843 unsigned nesting_level = ctxt->src2.val & 31;
1847 return X86EMUL_UNHANDLEABLE;
1849 rbp = reg_read(ctxt, VCPU_REGS_RBP);
1850 rc = push(ctxt, &rbp, stack_size(ctxt));
1851 if (rc != X86EMUL_CONTINUE)
1853 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1855 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1856 reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1858 return X86EMUL_CONTINUE;
1861 static int em_leave(struct x86_emulate_ctxt *ctxt)
1863 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1865 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1868 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1870 int seg = ctxt->src2.val;
1872 ctxt->src.val = get_segment_selector(ctxt, seg);
1873 if (ctxt->op_bytes == 4) {
1874 rsp_increment(ctxt, -2);
1878 return em_push(ctxt);
1881 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1883 int seg = ctxt->src2.val;
1884 unsigned long selector;
1887 rc = emulate_pop(ctxt, &selector, 2);
1888 if (rc != X86EMUL_CONTINUE)
1891 if (ctxt->modrm_reg == VCPU_SREG_SS)
1892 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1893 if (ctxt->op_bytes > 2)
1894 rsp_increment(ctxt, ctxt->op_bytes - 2);
1896 rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1900 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1902 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1903 int rc = X86EMUL_CONTINUE;
1904 int reg = VCPU_REGS_RAX;
1906 while (reg <= VCPU_REGS_RDI) {
1907 (reg == VCPU_REGS_RSP) ?
1908 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1911 if (rc != X86EMUL_CONTINUE)
1920 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1922 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
1923 return em_push(ctxt);
1926 static int em_popa(struct x86_emulate_ctxt *ctxt)
1928 int rc = X86EMUL_CONTINUE;
1929 int reg = VCPU_REGS_RDI;
1932 while (reg >= VCPU_REGS_RAX) {
1933 if (reg == VCPU_REGS_RSP) {
1934 rsp_increment(ctxt, ctxt->op_bytes);
1938 rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
1939 if (rc != X86EMUL_CONTINUE)
1941 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
1947 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1949 const struct x86_emulate_ops *ops = ctxt->ops;
1956 /* TODO: Add limit checks */
1957 ctxt->src.val = ctxt->eflags;
1959 if (rc != X86EMUL_CONTINUE)
1962 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
1964 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1966 if (rc != X86EMUL_CONTINUE)
1969 ctxt->src.val = ctxt->_eip;
1971 if (rc != X86EMUL_CONTINUE)
1974 ops->get_idt(ctxt, &dt);
1976 eip_addr = dt.address + (irq << 2);
1977 cs_addr = dt.address + (irq << 2) + 2;
1979 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1980 if (rc != X86EMUL_CONTINUE)
1983 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1984 if (rc != X86EMUL_CONTINUE)
1987 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1988 if (rc != X86EMUL_CONTINUE)
1996 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2000 invalidate_registers(ctxt);
2001 rc = __emulate_int_real(ctxt, irq);
2002 if (rc == X86EMUL_CONTINUE)
2003 writeback_registers(ctxt);
2007 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2009 switch(ctxt->mode) {
2010 case X86EMUL_MODE_REAL:
2011 return __emulate_int_real(ctxt, irq);
2012 case X86EMUL_MODE_VM86:
2013 case X86EMUL_MODE_PROT16:
2014 case X86EMUL_MODE_PROT32:
2015 case X86EMUL_MODE_PROT64:
2017 /* Protected mode interrupts unimplemented yet */
2018 return X86EMUL_UNHANDLEABLE;
2022 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2024 int rc = X86EMUL_CONTINUE;
2025 unsigned long temp_eip = 0;
2026 unsigned long temp_eflags = 0;
2027 unsigned long cs = 0;
2028 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2029 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2030 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2031 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2032 X86_EFLAGS_AC | X86_EFLAGS_ID |
2034 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2037 /* TODO: Add stack limit check */
2039 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2041 if (rc != X86EMUL_CONTINUE)
2044 if (temp_eip & ~0xffff)
2045 return emulate_gp(ctxt, 0);
2047 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2049 if (rc != X86EMUL_CONTINUE)
2052 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2054 if (rc != X86EMUL_CONTINUE)
2057 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2059 if (rc != X86EMUL_CONTINUE)
2062 ctxt->_eip = temp_eip;
2064 if (ctxt->op_bytes == 4)
2065 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2066 else if (ctxt->op_bytes == 2) {
2067 ctxt->eflags &= ~0xffff;
2068 ctxt->eflags |= temp_eflags;
2071 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2072 ctxt->eflags |= X86_EFLAGS_FIXED;
2073 ctxt->ops->set_nmi_mask(ctxt, false);
2078 static int em_iret(struct x86_emulate_ctxt *ctxt)
2080 switch(ctxt->mode) {
2081 case X86EMUL_MODE_REAL:
2082 return emulate_iret_real(ctxt);
2083 case X86EMUL_MODE_VM86:
2084 case X86EMUL_MODE_PROT16:
2085 case X86EMUL_MODE_PROT32:
2086 case X86EMUL_MODE_PROT64:
2088 /* iret from protected mode unimplemented yet */
2089 return X86EMUL_UNHANDLEABLE;
2093 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2096 unsigned short sel, old_sel;
2097 struct desc_struct old_desc, new_desc;
2098 const struct x86_emulate_ops *ops = ctxt->ops;
2099 u8 cpl = ctxt->ops->cpl(ctxt);
2101 /* Assignment of RIP may only fail in 64-bit mode */
2102 if (ctxt->mode == X86EMUL_MODE_PROT64)
2103 ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
2106 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2108 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2109 X86_TRANSFER_CALL_JMP,
2111 if (rc != X86EMUL_CONTINUE)
2114 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2115 if (rc != X86EMUL_CONTINUE) {
2116 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2117 /* assigning eip failed; restore the old cs */
2118 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
2124 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2126 return assign_eip_near(ctxt, ctxt->src.val);
2129 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2134 old_eip = ctxt->_eip;
2135 rc = assign_eip_near(ctxt, ctxt->src.val);
2136 if (rc != X86EMUL_CONTINUE)
2138 ctxt->src.val = old_eip;
2143 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2145 u64 old = ctxt->dst.orig_val64;
2147 if (ctxt->dst.bytes == 16)
2148 return X86EMUL_UNHANDLEABLE;
2150 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2151 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2152 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2153 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2154 ctxt->eflags &= ~X86_EFLAGS_ZF;
2156 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2157 (u32) reg_read(ctxt, VCPU_REGS_RBX);
2159 ctxt->eflags |= X86_EFLAGS_ZF;
2161 return X86EMUL_CONTINUE;
2164 static int em_ret(struct x86_emulate_ctxt *ctxt)
2169 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2170 if (rc != X86EMUL_CONTINUE)
2173 return assign_eip_near(ctxt, eip);
2176 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2179 unsigned long eip, cs;
2181 int cpl = ctxt->ops->cpl(ctxt);
2182 struct desc_struct old_desc, new_desc;
2183 const struct x86_emulate_ops *ops = ctxt->ops;
2185 if (ctxt->mode == X86EMUL_MODE_PROT64)
2186 ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
2189 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2190 if (rc != X86EMUL_CONTINUE)
2192 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2193 if (rc != X86EMUL_CONTINUE)
2195 /* Outer-privilege level return is not implemented */
2196 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2197 return X86EMUL_UNHANDLEABLE;
2198 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2201 if (rc != X86EMUL_CONTINUE)
2203 rc = assign_eip_far(ctxt, eip, &new_desc);
2204 if (rc != X86EMUL_CONTINUE) {
2205 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2206 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
2211 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2215 rc = em_ret_far(ctxt);
2216 if (rc != X86EMUL_CONTINUE)
2218 rsp_increment(ctxt, ctxt->src.val);
2219 return X86EMUL_CONTINUE;
2222 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2224 /* Save real source value, then compare EAX against destination. */
2225 ctxt->dst.orig_val = ctxt->dst.val;
2226 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2227 ctxt->src.orig_val = ctxt->src.val;
2228 ctxt->src.val = ctxt->dst.orig_val;
2229 fastop(ctxt, em_cmp);
2231 if (ctxt->eflags & X86_EFLAGS_ZF) {
2232 /* Success: write back to memory; no update of EAX */
2233 ctxt->src.type = OP_NONE;
2234 ctxt->dst.val = ctxt->src.orig_val;
2236 /* Failure: write the value we saw to EAX. */
2237 ctxt->src.type = OP_REG;
2238 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2239 ctxt->src.val = ctxt->dst.orig_val;
2240 /* Create write-cycle to dest by writing the same value */
2241 ctxt->dst.val = ctxt->dst.orig_val;
2243 return X86EMUL_CONTINUE;
2246 static int em_lseg(struct x86_emulate_ctxt *ctxt)
2248 int seg = ctxt->src2.val;
2252 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2254 rc = load_segment_descriptor(ctxt, sel, seg);
2255 if (rc != X86EMUL_CONTINUE)
2258 ctxt->dst.val = ctxt->src.val;
2263 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2264 struct desc_struct *cs, struct desc_struct *ss)
2266 cs->l = 0; /* will be adjusted later */
2267 set_desc_base(cs, 0); /* flat segment */
2268 cs->g = 1; /* 4kb granularity */
2269 set_desc_limit(cs, 0xfffff); /* 4GB limit */
2270 cs->type = 0x0b; /* Read, Execute, Accessed */
2272 cs->dpl = 0; /* will be adjusted later */
2277 set_desc_base(ss, 0); /* flat segment */
2278 set_desc_limit(ss, 0xfffff); /* 4GB limit */
2279 ss->g = 1; /* 4kb granularity */
2281 ss->type = 0x03; /* Read/Write, Accessed */
2282 ss->d = 1; /* 32bit stack segment */
2289 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2291 u32 eax, ebx, ecx, edx;
2294 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2295 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2296 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2297 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2300 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2302 const struct x86_emulate_ops *ops = ctxt->ops;
2303 u32 eax, ebx, ecx, edx;
2306 * syscall should always be enabled in longmode - so only become
2307 * vendor specific (cpuid) if other modes are active...
2309 if (ctxt->mode == X86EMUL_MODE_PROT64)
2314 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
2316 * Intel ("GenuineIntel")
2317 * remark: Intel CPUs only support "syscall" in 64bit
2318 * longmode. Also an 64bit guest with a
2319 * 32bit compat-app running will #UD !! While this
2320 * behaviour can be fixed (by emulating) into AMD
2321 * response - CPUs of AMD can't behave like Intel.
2323 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2324 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2325 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2328 /* AMD ("AuthenticAMD") */
2329 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2330 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2331 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2334 /* AMD ("AMDisbetter!") */
2335 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2336 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2337 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2340 /* default: (not Intel, not AMD), apply Intel's stricter rules... */
2344 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2346 const struct x86_emulate_ops *ops = ctxt->ops;
2347 struct desc_struct cs, ss;
2352 /* syscall is not available in real mode */
2353 if (ctxt->mode == X86EMUL_MODE_REAL ||
2354 ctxt->mode == X86EMUL_MODE_VM86)
2355 return emulate_ud(ctxt);
2357 if (!(em_syscall_is_enabled(ctxt)))
2358 return emulate_ud(ctxt);
2360 ops->get_msr(ctxt, MSR_EFER, &efer);
2361 setup_syscalls_segments(ctxt, &cs, &ss);
2363 if (!(efer & EFER_SCE))
2364 return emulate_ud(ctxt);
2366 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2368 cs_sel = (u16)(msr_data & 0xfffc);
2369 ss_sel = (u16)(msr_data + 8);
2371 if (efer & EFER_LMA) {
2375 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2376 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2378 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2379 if (efer & EFER_LMA) {
2380 #ifdef CONFIG_X86_64
2381 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2384 ctxt->mode == X86EMUL_MODE_PROT64 ?
2385 MSR_LSTAR : MSR_CSTAR, &msr_data);
2386 ctxt->_eip = msr_data;
2388 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2389 ctxt->eflags &= ~msr_data;
2390 ctxt->eflags |= X86_EFLAGS_FIXED;
2394 ops->get_msr(ctxt, MSR_STAR, &msr_data);
2395 ctxt->_eip = (u32)msr_data;
2397 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2400 return X86EMUL_CONTINUE;
2403 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2405 const struct x86_emulate_ops *ops = ctxt->ops;
2406 struct desc_struct cs, ss;
2411 ops->get_msr(ctxt, MSR_EFER, &efer);
2412 /* inject #GP if in real mode */
2413 if (ctxt->mode == X86EMUL_MODE_REAL)
2414 return emulate_gp(ctxt, 0);
2417 * Not recognized on AMD in compat mode (but is recognized in legacy
2420 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
2421 && !vendor_intel(ctxt))
2422 return emulate_ud(ctxt);
2424 /* sysenter/sysexit have not been tested in 64bit mode. */
2425 if (ctxt->mode == X86EMUL_MODE_PROT64)
2426 return X86EMUL_UNHANDLEABLE;
2428 setup_syscalls_segments(ctxt, &cs, &ss);
2430 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2431 if ((msr_data & 0xfffc) == 0x0)
2432 return emulate_gp(ctxt, 0);
2434 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2435 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
2436 ss_sel = cs_sel + 8;
2437 if (efer & EFER_LMA) {
2442 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2443 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2445 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2446 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2448 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2449 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2452 return X86EMUL_CONTINUE;
2455 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2457 const struct x86_emulate_ops *ops = ctxt->ops;
2458 struct desc_struct cs, ss;
2459 u64 msr_data, rcx, rdx;
2461 u16 cs_sel = 0, ss_sel = 0;
2463 /* inject #GP if in real mode or Virtual 8086 mode */
2464 if (ctxt->mode == X86EMUL_MODE_REAL ||
2465 ctxt->mode == X86EMUL_MODE_VM86)
2466 return emulate_gp(ctxt, 0);
2468 setup_syscalls_segments(ctxt, &cs, &ss);
2470 if ((ctxt->rex_prefix & 0x8) != 0x0)
2471 usermode = X86EMUL_MODE_PROT64;
2473 usermode = X86EMUL_MODE_PROT32;
2475 rcx = reg_read(ctxt, VCPU_REGS_RCX);
2476 rdx = reg_read(ctxt, VCPU_REGS_RDX);
2480 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2482 case X86EMUL_MODE_PROT32:
2483 cs_sel = (u16)(msr_data + 16);
2484 if ((msr_data & 0xfffc) == 0x0)
2485 return emulate_gp(ctxt, 0);
2486 ss_sel = (u16)(msr_data + 24);
2490 case X86EMUL_MODE_PROT64:
2491 cs_sel = (u16)(msr_data + 32);
2492 if (msr_data == 0x0)
2493 return emulate_gp(ctxt, 0);
2494 ss_sel = cs_sel + 8;
2497 if (is_noncanonical_address(rcx) ||
2498 is_noncanonical_address(rdx))
2499 return emulate_gp(ctxt, 0);
2502 cs_sel |= SEGMENT_RPL_MASK;
2503 ss_sel |= SEGMENT_RPL_MASK;
2505 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2506 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2509 *reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2511 return X86EMUL_CONTINUE;
2514 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2517 if (ctxt->mode == X86EMUL_MODE_REAL)
2519 if (ctxt->mode == X86EMUL_MODE_VM86)
2521 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
2522 return ctxt->ops->cpl(ctxt) > iopl;
2525 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2528 const struct x86_emulate_ops *ops = ctxt->ops;
2529 struct desc_struct tr_seg;
2532 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2533 unsigned mask = (1 << len) - 1;
2536 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2539 if (desc_limit_scaled(&tr_seg) < 103)
2541 base = get_desc_base(&tr_seg);
2542 #ifdef CONFIG_X86_64
2543 base |= ((u64)base3) << 32;
2545 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2546 if (r != X86EMUL_CONTINUE)
2548 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2550 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2551 if (r != X86EMUL_CONTINUE)
2553 if ((perm >> bit_idx) & mask)
2558 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2564 if (emulator_bad_iopl(ctxt))
2565 if (!emulator_io_port_access_allowed(ctxt, port, len))
2568 ctxt->perm_ok = true;
2573 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2576 * Intel CPUs mask the counter and pointers in quite strange
2577 * manner when ECX is zero due to REP-string optimizations.
2579 #ifdef CONFIG_X86_64
2580 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2583 *reg_write(ctxt, VCPU_REGS_RCX) = 0;
2586 case 0xa4: /* movsb */
2587 case 0xa5: /* movsd/w */
2588 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2590 case 0xaa: /* stosb */
2591 case 0xab: /* stosd/w */
2592 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2597 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2598 struct tss_segment_16 *tss)
2600 tss->ip = ctxt->_eip;
2601 tss->flag = ctxt->eflags;
2602 tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2603 tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2604 tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2605 tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2606 tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2607 tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2608 tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2609 tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2611 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2612 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2613 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2614 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2615 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2618 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2619 struct tss_segment_16 *tss)
2624 ctxt->_eip = tss->ip;
2625 ctxt->eflags = tss->flag | 2;
2626 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
2627 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
2628 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
2629 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
2630 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
2631 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
2632 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
2633 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2636 * SDM says that segment selectors are loaded before segment
2639 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
2640 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2641 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2642 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2643 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2648 * Now load segment descriptors. If fault happens at this stage
2649 * it is handled in a context of new task
2651 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
2652 X86_TRANSFER_TASK_SWITCH, NULL);
2653 if (ret != X86EMUL_CONTINUE)
2655 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2656 X86_TRANSFER_TASK_SWITCH, NULL);
2657 if (ret != X86EMUL_CONTINUE)
2659 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2660 X86_TRANSFER_TASK_SWITCH, NULL);
2661 if (ret != X86EMUL_CONTINUE)
2663 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2664 X86_TRANSFER_TASK_SWITCH, NULL);
2665 if (ret != X86EMUL_CONTINUE)
2667 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2668 X86_TRANSFER_TASK_SWITCH, NULL);
2669 if (ret != X86EMUL_CONTINUE)
2672 return X86EMUL_CONTINUE;
2675 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2676 u16 tss_selector, u16 old_tss_sel,
2677 ulong old_tss_base, struct desc_struct *new_desc)
2679 const struct x86_emulate_ops *ops = ctxt->ops;
2680 struct tss_segment_16 tss_seg;
2682 u32 new_tss_base = get_desc_base(new_desc);
2684 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2686 if (ret != X86EMUL_CONTINUE)
2689 save_state_to_tss16(ctxt, &tss_seg);
2691 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2693 if (ret != X86EMUL_CONTINUE)
2696 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2698 if (ret != X86EMUL_CONTINUE)
2701 if (old_tss_sel != 0xffff) {
2702 tss_seg.prev_task_link = old_tss_sel;
2704 ret = ops->write_std(ctxt, new_tss_base,
2705 &tss_seg.prev_task_link,
2706 sizeof tss_seg.prev_task_link,
2708 if (ret != X86EMUL_CONTINUE)
2712 return load_state_from_tss16(ctxt, &tss_seg);
2715 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2716 struct tss_segment_32 *tss)
2718 /* CR3 and ldt selector are not saved intentionally */
2719 tss->eip = ctxt->_eip;
2720 tss->eflags = ctxt->eflags;
2721 tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
2722 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
2723 tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
2724 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
2725 tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
2726 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
2727 tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
2728 tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2730 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2731 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2732 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2733 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2734 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
2735 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2738 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2739 struct tss_segment_32 *tss)
2744 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2745 return emulate_gp(ctxt, 0);
2746 ctxt->_eip = tss->eip;
2747 ctxt->eflags = tss->eflags | 2;
2749 /* General purpose registers */
2750 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
2751 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
2752 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
2753 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
2754 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
2755 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
2756 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
2757 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2760 * SDM says that segment selectors are loaded before segment
2761 * descriptors. This is important because CPL checks will
2764 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2765 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
2766 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
2767 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
2768 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2769 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
2770 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2773 * If we're switching between Protected Mode and VM86, we need to make
2774 * sure to update the mode before loading the segment descriptors so
2775 * that the selectors are interpreted correctly.
2777 if (ctxt->eflags & X86_EFLAGS_VM) {
2778 ctxt->mode = X86EMUL_MODE_VM86;
2781 ctxt->mode = X86EMUL_MODE_PROT32;
2786 * Now load segment descriptors. If fault happenes at this stage
2787 * it is handled in a context of new task
2789 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
2790 cpl, X86_TRANSFER_TASK_SWITCH, NULL);
2791 if (ret != X86EMUL_CONTINUE)
2793 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
2794 X86_TRANSFER_TASK_SWITCH, NULL);
2795 if (ret != X86EMUL_CONTINUE)
2797 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
2798 X86_TRANSFER_TASK_SWITCH, NULL);
2799 if (ret != X86EMUL_CONTINUE)
2801 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
2802 X86_TRANSFER_TASK_SWITCH, NULL);
2803 if (ret != X86EMUL_CONTINUE)
2805 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
2806 X86_TRANSFER_TASK_SWITCH, NULL);
2807 if (ret != X86EMUL_CONTINUE)
2809 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
2810 X86_TRANSFER_TASK_SWITCH, NULL);
2811 if (ret != X86EMUL_CONTINUE)
2813 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
2814 X86_TRANSFER_TASK_SWITCH, NULL);
2819 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2820 u16 tss_selector, u16 old_tss_sel,
2821 ulong old_tss_base, struct desc_struct *new_desc)
2823 const struct x86_emulate_ops *ops = ctxt->ops;
2824 struct tss_segment_32 tss_seg;
2826 u32 new_tss_base = get_desc_base(new_desc);
2827 u32 eip_offset = offsetof(struct tss_segment_32, eip);
2828 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
2830 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2832 if (ret != X86EMUL_CONTINUE)
2835 save_state_to_tss32(ctxt, &tss_seg);
2837 /* Only GP registers and segment selectors are saved */
2838 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
2839 ldt_sel_offset - eip_offset, &ctxt->exception);
2840 if (ret != X86EMUL_CONTINUE)
2843 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2845 if (ret != X86EMUL_CONTINUE)
2848 if (old_tss_sel != 0xffff) {
2849 tss_seg.prev_task_link = old_tss_sel;
2851 ret = ops->write_std(ctxt, new_tss_base,
2852 &tss_seg.prev_task_link,
2853 sizeof tss_seg.prev_task_link,
2855 if (ret != X86EMUL_CONTINUE)
2859 return load_state_from_tss32(ctxt, &tss_seg);
2862 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2863 u16 tss_selector, int idt_index, int reason,
2864 bool has_error_code, u32 error_code)
2866 const struct x86_emulate_ops *ops = ctxt->ops;
2867 struct desc_struct curr_tss_desc, next_tss_desc;
2869 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2870 ulong old_tss_base =
2871 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2873 ulong desc_addr, dr7;
2875 /* FIXME: old_tss_base == ~0 ? */
2877 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2878 if (ret != X86EMUL_CONTINUE)
2880 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2881 if (ret != X86EMUL_CONTINUE)
2884 /* FIXME: check that next_tss_desc is tss */
2887 * Check privileges. The three cases are task switch caused by...
2889 * 1. jmp/call/int to task gate: Check against DPL of the task gate
2890 * 2. Exception/IRQ/iret: No check is performed
2891 * 3. jmp/call to TSS/task-gate: No check is performed since the
2892 * hardware checks it before exiting.
2894 if (reason == TASK_SWITCH_GATE) {
2895 if (idt_index != -1) {
2896 /* Software interrupts */
2897 struct desc_struct task_gate_desc;
2900 ret = read_interrupt_descriptor(ctxt, idt_index,
2902 if (ret != X86EMUL_CONTINUE)
2905 dpl = task_gate_desc.dpl;
2906 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
2907 return emulate_gp(ctxt, (idt_index << 3) | 0x2);
2911 desc_limit = desc_limit_scaled(&next_tss_desc);
2912 if (!next_tss_desc.p ||
2913 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2914 desc_limit < 0x2b)) {
2915 return emulate_ts(ctxt, tss_selector & 0xfffc);
2918 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2919 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2920 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2923 if (reason == TASK_SWITCH_IRET)
2924 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2926 /* set back link to prev task only if NT bit is set in eflags
2927 note that old_tss_sel is not used after this point */
2928 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2929 old_tss_sel = 0xffff;
2931 if (next_tss_desc.type & 8)
2932 ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2933 old_tss_base, &next_tss_desc);
2935 ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2936 old_tss_base, &next_tss_desc);
2937 if (ret != X86EMUL_CONTINUE)
2940 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2941 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2943 if (reason != TASK_SWITCH_IRET) {
2944 next_tss_desc.type |= (1 << 1); /* set busy flag */
2945 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2948 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS);
2949 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2951 if (has_error_code) {
2952 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2953 ctxt->lock_prefix = 0;
2954 ctxt->src.val = (unsigned long) error_code;
2955 ret = em_push(ctxt);
2958 ops->get_dr(ctxt, 7, &dr7);
2959 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
2964 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2965 u16 tss_selector, int idt_index, int reason,
2966 bool has_error_code, u32 error_code)
2970 invalidate_registers(ctxt);
2971 ctxt->_eip = ctxt->eip;
2972 ctxt->dst.type = OP_NONE;
2974 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2975 has_error_code, error_code);
2977 if (rc == X86EMUL_CONTINUE) {
2978 ctxt->eip = ctxt->_eip;
2979 writeback_registers(ctxt);
2982 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2985 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
2988 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
2990 register_address_increment(ctxt, reg, df * op->bytes);
2991 op->addr.mem.ea = register_address(ctxt, reg);
2994 static int em_das(struct x86_emulate_ctxt *ctxt)
2997 bool af, cf, old_cf;
2999 cf = ctxt->eflags & X86_EFLAGS_CF;
3005 af = ctxt->eflags & X86_EFLAGS_AF;
3006 if ((al & 0x0f) > 9 || af) {
3008 cf = old_cf | (al >= 250);
3013 if (old_al > 0x99 || old_cf) {
3019 /* Set PF, ZF, SF */
3020 ctxt->src.type = OP_IMM;
3022 ctxt->src.bytes = 1;
3023 fastop(ctxt, em_or);
3024 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3026 ctxt->eflags |= X86_EFLAGS_CF;
3028 ctxt->eflags |= X86_EFLAGS_AF;
3029 return X86EMUL_CONTINUE;
3032 static int em_aam(struct x86_emulate_ctxt *ctxt)
3036 if (ctxt->src.val == 0)
3037 return emulate_de(ctxt);
3039 al = ctxt->dst.val & 0xff;
3040 ah = al / ctxt->src.val;
3041 al %= ctxt->src.val;
3043 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3045 /* Set PF, ZF, SF */
3046 ctxt->src.type = OP_IMM;
3048 ctxt->src.bytes = 1;
3049 fastop(ctxt, em_or);
3051 return X86EMUL_CONTINUE;
3054 static int em_aad(struct x86_emulate_ctxt *ctxt)
3056 u8 al = ctxt->dst.val & 0xff;
3057 u8 ah = (ctxt->dst.val >> 8) & 0xff;
3059 al = (al + (ah * ctxt->src.val)) & 0xff;
3061 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3063 /* Set PF, ZF, SF */
3064 ctxt->src.type = OP_IMM;
3066 ctxt->src.bytes = 1;
3067 fastop(ctxt, em_or);
3069 return X86EMUL_CONTINUE;
3072 static int em_call(struct x86_emulate_ctxt *ctxt)
3075 long rel = ctxt->src.val;
3077 ctxt->src.val = (unsigned long)ctxt->_eip;
3078 rc = jmp_rel(ctxt, rel);
3079 if (rc != X86EMUL_CONTINUE)
3081 return em_push(ctxt);
3084 static int em_call_far(struct x86_emulate_ctxt *ctxt)
3089 struct desc_struct old_desc, new_desc;
3090 const struct x86_emulate_ops *ops = ctxt->ops;
3091 int cpl = ctxt->ops->cpl(ctxt);
3092 enum x86emul_mode prev_mode = ctxt->mode;
3094 old_eip = ctxt->_eip;
3095 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3097 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3098 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3099 X86_TRANSFER_CALL_JMP, &new_desc);
3100 if (rc != X86EMUL_CONTINUE)
3103 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
3104 if (rc != X86EMUL_CONTINUE)
3107 ctxt->src.val = old_cs;
3109 if (rc != X86EMUL_CONTINUE)
3112 ctxt->src.val = old_eip;
3114 /* If we failed, we tainted the memory, but the very least we should
3116 if (rc != X86EMUL_CONTINUE) {
3117 pr_warn_once("faulting far call emulation tainted memory\n");
3122 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3123 ctxt->mode = prev_mode;
3128 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3133 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3134 if (rc != X86EMUL_CONTINUE)
3136 rc = assign_eip_near(ctxt, eip);
3137 if (rc != X86EMUL_CONTINUE)
3139 rsp_increment(ctxt, ctxt->src.val);
3140 return X86EMUL_CONTINUE;
3143 static int em_xchg(struct x86_emulate_ctxt *ctxt)
3145 /* Write back the register source. */
3146 ctxt->src.val = ctxt->dst.val;
3147 write_register_operand(&ctxt->src);
3149 /* Write back the memory destination with implicit LOCK prefix. */
3150 ctxt->dst.val = ctxt->src.orig_val;
3151 ctxt->lock_prefix = 1;
3152 return X86EMUL_CONTINUE;
3155 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3157 ctxt->dst.val = ctxt->src2.val;
3158 return fastop(ctxt, em_imul);
3161 static int em_cwd(struct x86_emulate_ctxt *ctxt)
3163 ctxt->dst.type = OP_REG;
3164 ctxt->dst.bytes = ctxt->src.bytes;
3165 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3166 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3168 return X86EMUL_CONTINUE;
3171 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3175 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3176 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3177 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3178 return X86EMUL_CONTINUE;
3181 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3185 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3186 return emulate_gp(ctxt, 0);
3187 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3188 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3189 return X86EMUL_CONTINUE;
3192 static int em_mov(struct x86_emulate_ctxt *ctxt)
3194 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3195 return X86EMUL_CONTINUE;
3198 #define FFL(x) bit(X86_FEATURE_##x)
3200 static int em_movbe(struct x86_emulate_ctxt *ctxt)
3202 u32 ebx, ecx, edx, eax = 1;
3206 * Check MOVBE is set in the guest-visible CPUID leaf.
3208 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3209 if (!(ecx & FFL(MOVBE)))
3210 return emulate_ud(ctxt);
3212 switch (ctxt->op_bytes) {
3215 * From MOVBE definition: "...When the operand size is 16 bits,
3216 * the upper word of the destination register remains unchanged
3219 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3220 * rules so we have to do the operation almost per hand.
3222 tmp = (u16)ctxt->src.val;
3223 ctxt->dst.val &= ~0xffffUL;
3224 ctxt->dst.val |= (unsigned long)swab16(tmp);
3227 ctxt->dst.val = swab32((u32)ctxt->src.val);
3230 ctxt->dst.val = swab64(ctxt->src.val);
3235 return X86EMUL_CONTINUE;
3238 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3240 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3241 return emulate_gp(ctxt, 0);
3243 /* Disable writeback. */
3244 ctxt->dst.type = OP_NONE;
3245 return X86EMUL_CONTINUE;
3248 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3252 if (ctxt->mode == X86EMUL_MODE_PROT64)
3253 val = ctxt->src.val & ~0ULL;
3255 val = ctxt->src.val & ~0U;
3257 /* #UD condition is already handled. */
3258 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3259 return emulate_gp(ctxt, 0);
3261 /* Disable writeback. */
3262 ctxt->dst.type = OP_NONE;
3263 return X86EMUL_CONTINUE;
3266 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3270 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3271 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3272 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3273 return emulate_gp(ctxt, 0);
3275 return X86EMUL_CONTINUE;
3278 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3282 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3283 return emulate_gp(ctxt, 0);
3285 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3286 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3287 return X86EMUL_CONTINUE;
3290 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3292 if (ctxt->modrm_reg > VCPU_SREG_GS)
3293 return emulate_ud(ctxt);
3295 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3296 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3297 ctxt->dst.bytes = 2;
3298 return X86EMUL_CONTINUE;
3301 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3303 u16 sel = ctxt->src.val;
3305 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3306 return emulate_ud(ctxt);
3308 if (ctxt->modrm_reg == VCPU_SREG_SS)
3309 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3311 /* Disable writeback. */
3312 ctxt->dst.type = OP_NONE;
3313 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3316 static int em_lldt(struct x86_emulate_ctxt *ctxt)
3318 u16 sel = ctxt->src.val;
3320 /* Disable writeback. */
3321 ctxt->dst.type = OP_NONE;
3322 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3325 static int em_ltr(struct x86_emulate_ctxt *ctxt)
3327 u16 sel = ctxt->src.val;
3329 /* Disable writeback. */
3330 ctxt->dst.type = OP_NONE;
3331 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3334 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3339 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3340 if (rc == X86EMUL_CONTINUE)
3341 ctxt->ops->invlpg(ctxt, linear);
3342 /* Disable writeback. */
3343 ctxt->dst.type = OP_NONE;
3344 return X86EMUL_CONTINUE;
3347 static int em_clts(struct x86_emulate_ctxt *ctxt)
3351 cr0 = ctxt->ops->get_cr(ctxt, 0);
3353 ctxt->ops->set_cr(ctxt, 0, cr0);
3354 return X86EMUL_CONTINUE;
3357 static int em_hypercall(struct x86_emulate_ctxt *ctxt)
3359 int rc = ctxt->ops->fix_hypercall(ctxt);
3361 if (rc != X86EMUL_CONTINUE)
3364 /* Let the processor re-execute the fixed hypercall */
3365 ctxt->_eip = ctxt->eip;
3366 /* Disable writeback. */
3367 ctxt->dst.type = OP_NONE;
3368 return X86EMUL_CONTINUE;
3371 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3372 void (*get)(struct x86_emulate_ctxt *ctxt,
3373 struct desc_ptr *ptr))
3375 struct desc_ptr desc_ptr;
3377 if (ctxt->mode == X86EMUL_MODE_PROT64)
3379 get(ctxt, &desc_ptr);
3380 if (ctxt->op_bytes == 2) {
3382 desc_ptr.address &= 0x00ffffff;
3384 /* Disable writeback. */
3385 ctxt->dst.type = OP_NONE;
3386 return segmented_write(ctxt, ctxt->dst.addr.mem,
3387 &desc_ptr, 2 + ctxt->op_bytes);
3390 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3392 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3395 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3397 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3400 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3402 struct desc_ptr desc_ptr;
3405 if (ctxt->mode == X86EMUL_MODE_PROT64)
3407 rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3408 &desc_ptr.size, &desc_ptr.address,
3410 if (rc != X86EMUL_CONTINUE)
3412 if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3413 is_noncanonical_address(desc_ptr.address))
3414 return emulate_gp(ctxt, 0);
3416 ctxt->ops->set_gdt(ctxt, &desc_ptr);
3418 ctxt->ops->set_idt(ctxt, &desc_ptr);
3419 /* Disable writeback. */
3420 ctxt->dst.type = OP_NONE;
3421 return X86EMUL_CONTINUE;
3424 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3426 return em_lgdt_lidt(ctxt, true);
3429 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3431 return em_lgdt_lidt(ctxt, false);
3434 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3436 if (ctxt->dst.type == OP_MEM)
3437 ctxt->dst.bytes = 2;
3438 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3439 return X86EMUL_CONTINUE;
3442 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3444 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3445 | (ctxt->src.val & 0x0f));
3446 ctxt->dst.type = OP_NONE;
3447 return X86EMUL_CONTINUE;
3450 static int em_loop(struct x86_emulate_ctxt *ctxt)
3452 int rc = X86EMUL_CONTINUE;
3454 register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3455 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3456 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3457 rc = jmp_rel(ctxt, ctxt->src.val);
3462 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3464 int rc = X86EMUL_CONTINUE;
3466 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3467 rc = jmp_rel(ctxt, ctxt->src.val);
3472 static int em_in(struct x86_emulate_ctxt *ctxt)
3474 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3476 return X86EMUL_IO_NEEDED;
3478 return X86EMUL_CONTINUE;
3481 static int em_out(struct x86_emulate_ctxt *ctxt)
3483 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3485 /* Disable writeback. */
3486 ctxt->dst.type = OP_NONE;
3487 return X86EMUL_CONTINUE;
3490 static int em_cli(struct x86_emulate_ctxt *ctxt)
3492 if (emulator_bad_iopl(ctxt))
3493 return emulate_gp(ctxt, 0);
3495 ctxt->eflags &= ~X86_EFLAGS_IF;
3496 return X86EMUL_CONTINUE;
3499 static int em_sti(struct x86_emulate_ctxt *ctxt)
3501 if (emulator_bad_iopl(ctxt))
3502 return emulate_gp(ctxt, 0);
3504 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3505 ctxt->eflags |= X86_EFLAGS_IF;
3506 return X86EMUL_CONTINUE;
3509 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3511 u32 eax, ebx, ecx, edx;
3513 eax = reg_read(ctxt, VCPU_REGS_RAX);
3514 ecx = reg_read(ctxt, VCPU_REGS_RCX);
3515 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3516 *reg_write(ctxt, VCPU_REGS_RAX) = eax;
3517 *reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3518 *reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3519 *reg_write(ctxt, VCPU_REGS_RDX) = edx;
3520 return X86EMUL_CONTINUE;
3523 static int em_sahf(struct x86_emulate_ctxt *ctxt)
3527 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3529 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3531 ctxt->eflags &= ~0xffUL;
3532 ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3533 return X86EMUL_CONTINUE;
3536 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3538 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3539 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3540 return X86EMUL_CONTINUE;
3543 static int em_bswap(struct x86_emulate_ctxt *ctxt)
3545 switch (ctxt->op_bytes) {
3546 #ifdef CONFIG_X86_64
3548 asm("bswap %0" : "+r"(ctxt->dst.val));
3552 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3555 return X86EMUL_CONTINUE;
3558 static int em_clflush(struct x86_emulate_ctxt *ctxt)
3560 /* emulating clflush regardless of cpuid */
3561 return X86EMUL_CONTINUE;
3564 static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3566 ctxt->dst.val = (s32) ctxt->src.val;
3567 return X86EMUL_CONTINUE;
3570 static bool valid_cr(int nr)
3582 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
3584 if (!valid_cr(ctxt->modrm_reg))
3585 return emulate_ud(ctxt);
3587 return X86EMUL_CONTINUE;
3590 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
3592 u64 new_val = ctxt->src.val64;
3593 int cr = ctxt->modrm_reg;
3596 static u64 cr_reserved_bits[] = {
3597 0xffffffff00000000ULL,
3598 0, 0, 0, /* CR3 checked later */
3605 return emulate_ud(ctxt);
3607 if (new_val & cr_reserved_bits[cr])
3608 return emulate_gp(ctxt, 0);
3613 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
3614 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
3615 return emulate_gp(ctxt, 0);
3617 cr4 = ctxt->ops->get_cr(ctxt, 4);
3618 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3620 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
3621 !(cr4 & X86_CR4_PAE))
3622 return emulate_gp(ctxt, 0);
3629 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3630 if (efer & EFER_LMA)
3631 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD;
3634 return emulate_gp(ctxt, 0);
3639 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3641 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
3642 return emulate_gp(ctxt, 0);
3648 return X86EMUL_CONTINUE;
3651 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
3655 ctxt->ops->get_dr(ctxt, 7, &dr7);
3657 /* Check if DR7.Global_Enable is set */
3658 return dr7 & (1 << 13);
3661 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
3663 int dr = ctxt->modrm_reg;
3667 return emulate_ud(ctxt);
3669 cr4 = ctxt->ops->get_cr(ctxt, 4);
3670 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
3671 return emulate_ud(ctxt);
3673 if (check_dr7_gd(ctxt)) {
3676 ctxt->ops->get_dr(ctxt, 6, &dr6);
3678 dr6 |= DR6_BD | DR6_RTM;
3679 ctxt->ops->set_dr(ctxt, 6, dr6);
3680 return emulate_db(ctxt);
3683 return X86EMUL_CONTINUE;
3686 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
3688 u64 new_val = ctxt->src.val64;
3689 int dr = ctxt->modrm_reg;
3691 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
3692 return emulate_gp(ctxt, 0);
3694 return check_dr_read(ctxt);
3697 static int check_svme(struct x86_emulate_ctxt *ctxt)
3701 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3703 if (!(efer & EFER_SVME))
3704 return emulate_ud(ctxt);
3706 return X86EMUL_CONTINUE;
3709 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
3711 u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3713 /* Valid physical address? */
3714 if (rax & 0xffff000000000000ULL)
3715 return emulate_gp(ctxt, 0);
3717 return check_svme(ctxt);
3720 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
3722 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3724 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3725 return emulate_ud(ctxt);
3727 return X86EMUL_CONTINUE;
3730 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
3732 u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3733 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3735 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3736 ctxt->ops->check_pmc(ctxt, rcx))
3737 return emulate_gp(ctxt, 0);
3739 return X86EMUL_CONTINUE;
3742 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
3744 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
3745 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3746 return emulate_gp(ctxt, 0);
3748 return X86EMUL_CONTINUE;
3751 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
3753 ctxt->src.bytes = min(ctxt->src.bytes, 4u);
3754 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3755 return emulate_gp(ctxt, 0);
3757 return X86EMUL_CONTINUE;
3760 #define D(_y) { .flags = (_y) }
3761 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
3762 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
3763 .intercept = x86_intercept_##_i, .check_perm = (_p) }
3764 #define N D(NotImpl)
3765 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3766 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
3767 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3768 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
3769 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
3770 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3771 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3772 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3773 #define II(_f, _e, _i) \
3774 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
3775 #define IIP(_f, _e, _i, _p) \
3776 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
3777 .intercept = x86_intercept_##_i, .check_perm = (_p) }
3778 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3780 #define D2bv(_f) D((_f) | ByteOp), D(_f)
3781 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3782 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
3783 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e)
3784 #define I2bvIP(_f, _e, _i, _p) \
3785 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3787 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \
3788 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \
3789 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3791 static const struct opcode group7_rm0[] = {
3793 I(SrcNone | Priv | EmulateOnUD, em_hypercall),
3797 static const struct opcode group7_rm1[] = {
3798 DI(SrcNone | Priv, monitor),
3799 DI(SrcNone | Priv, mwait),
3803 static const struct opcode group7_rm3[] = {
3804 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa),
3805 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall),
3806 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa),
3807 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa),
3808 DIP(SrcNone | Prot | Priv, stgi, check_svme),
3809 DIP(SrcNone | Prot | Priv, clgi, check_svme),
3810 DIP(SrcNone | Prot | Priv, skinit, check_svme),
3811 DIP(SrcNone | Prot | Priv, invlpga, check_svme),
3814 static const struct opcode group7_rm7[] = {
3816 DIP(SrcNone, rdtscp, check_rdtsc),
3820 static const struct opcode group1[] = {
3822 F(Lock | PageTable, em_or),
3825 F(Lock | PageTable, em_and),
3831 static const struct opcode group1A[] = {
3832 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N,
3835 static const struct opcode group2[] = {
3836 F(DstMem | ModRM, em_rol),
3837 F(DstMem | ModRM, em_ror),
3838 F(DstMem | ModRM, em_rcl),
3839 F(DstMem | ModRM, em_rcr),
3840 F(DstMem | ModRM, em_shl),
3841 F(DstMem | ModRM, em_shr),
3842 F(DstMem | ModRM, em_shl),
3843 F(DstMem | ModRM, em_sar),
3846 static const struct opcode group3[] = {
3847 F(DstMem | SrcImm | NoWrite, em_test),
3848 F(DstMem | SrcImm | NoWrite, em_test),
3849 F(DstMem | SrcNone | Lock, em_not),
3850 F(DstMem | SrcNone | Lock, em_neg),
3851 F(DstXacc | Src2Mem, em_mul_ex),
3852 F(DstXacc | Src2Mem, em_imul_ex),
3853 F(DstXacc | Src2Mem, em_div_ex),
3854 F(DstXacc | Src2Mem, em_idiv_ex),
3857 static const struct opcode group4[] = {
3858 F(ByteOp | DstMem | SrcNone | Lock, em_inc),
3859 F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3863 static const struct opcode group5[] = {
3864 F(DstMem | SrcNone | Lock, em_inc),
3865 F(DstMem | SrcNone | Lock, em_dec),
3866 I(SrcMem | NearBranch, em_call_near_abs),
3867 I(SrcMemFAddr | ImplicitOps, em_call_far),
3868 I(SrcMem | NearBranch, em_jmp_abs),
3869 I(SrcMemFAddr | ImplicitOps, em_jmp_far),
3870 I(SrcMem | Stack, em_push), D(Undefined),
3873 static const struct opcode group6[] = {
3874 DI(Prot | DstMem, sldt),
3875 DI(Prot | DstMem, str),
3876 II(Prot | Priv | SrcMem16, em_lldt, lldt),
3877 II(Prot | Priv | SrcMem16, em_ltr, ltr),
3881 static const struct group_dual group7 = { {
3882 II(Mov | DstMem, em_sgdt, sgdt),
3883 II(Mov | DstMem, em_sidt, sidt),
3884 II(SrcMem | Priv, em_lgdt, lgdt),
3885 II(SrcMem | Priv, em_lidt, lidt),
3886 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3887 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3888 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3892 N, EXT(0, group7_rm3),
3893 II(SrcNone | DstMem | Mov, em_smsw, smsw), N,
3894 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw),
3898 static const struct opcode group8[] = {
3900 F(DstMem | SrcImmByte | NoWrite, em_bt),
3901 F(DstMem | SrcImmByte | Lock | PageTable, em_bts),
3902 F(DstMem | SrcImmByte | Lock, em_btr),
3903 F(DstMem | SrcImmByte | Lock | PageTable, em_btc),
3906 static const struct group_dual group9 = { {
3907 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3909 N, N, N, N, N, N, N, N,
3912 static const struct opcode group11[] = {
3913 I(DstMem | SrcImm | Mov | PageTable, em_mov),
3917 static const struct gprefix pfx_0f_ae_7 = {
3918 I(SrcMem | ByteOp, em_clflush), N, N, N,
3921 static const struct group_dual group15 = { {
3922 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
3924 N, N, N, N, N, N, N, N,
3927 static const struct gprefix pfx_0f_6f_0f_7f = {
3928 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3931 static const struct instr_dual instr_dual_0f_2b = {
3935 static const struct gprefix pfx_0f_2b = {
3936 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
3939 static const struct gprefix pfx_0f_28_0f_29 = {
3940 I(Aligned, em_mov), I(Aligned, em_mov), N, N,
3943 static const struct gprefix pfx_0f_e7 = {
3944 N, I(Sse, em_mov), N, N,
3947 static const struct escape escape_d9 = { {
3948 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
3951 N, N, N, N, N, N, N, N,
3953 N, N, N, N, N, N, N, N,
3955 N, N, N, N, N, N, N, N,
3957 N, N, N, N, N, N, N, N,
3959 N, N, N, N, N, N, N, N,
3961 N, N, N, N, N, N, N, N,
3963 N, N, N, N, N, N, N, N,
3965 N, N, N, N, N, N, N, N,
3968 static const struct escape escape_db = { {
3969 N, N, N, N, N, N, N, N,
3972 N, N, N, N, N, N, N, N,
3974 N, N, N, N, N, N, N, N,
3976 N, N, N, N, N, N, N, N,
3978 N, N, N, N, N, N, N, N,
3980 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
3982 N, N, N, N, N, N, N, N,
3984 N, N, N, N, N, N, N, N,
3986 N, N, N, N, N, N, N, N,
3989 static const struct escape escape_dd = { {
3990 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
3993 N, N, N, N, N, N, N, N,
3995 N, N, N, N, N, N, N, N,
3997 N, N, N, N, N, N, N, N,
3999 N, N, N, N, N, N, N, N,
4001 N, N, N, N, N, N, N, N,
4003 N, N, N, N, N, N, N, N,
4005 N, N, N, N, N, N, N, N,
4007 N, N, N, N, N, N, N, N,
4010 static const struct instr_dual instr_dual_0f_c3 = {
4011 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4014 static const struct mode_dual mode_dual_63 = {
4015 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4018 static const struct opcode opcode_table[256] = {
4020 F6ALU(Lock, em_add),
4021 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4022 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
4024 F6ALU(Lock | PageTable, em_or),
4025 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4028 F6ALU(Lock, em_adc),
4029 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4030 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
4032 F6ALU(Lock, em_sbb),
4033 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4034 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
4036 F6ALU(Lock | PageTable, em_and), N, N,
4038 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
4040 F6ALU(Lock, em_xor), N, N,
4042 F6ALU(NoWrite, em_cmp), N, N,
4044 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
4046 X8(I(SrcReg | Stack, em_push)),
4048 X8(I(DstReg | Stack, em_pop)),
4050 I(ImplicitOps | Stack | No64, em_pusha),
4051 I(ImplicitOps | Stack | No64, em_popa),
4052 N, MD(ModRM, &mode_dual_63),
4055 I(SrcImm | Mov | Stack, em_push),
4056 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4057 I(SrcImmByte | Mov | Stack, em_push),
4058 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4059 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4060 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4062 X16(D(SrcImmByte | NearBranch)),
4064 G(ByteOp | DstMem | SrcImm, group1),
4065 G(DstMem | SrcImm, group1),
4066 G(ByteOp | DstMem | SrcImm | No64, group1),
4067 G(DstMem | SrcImmByte, group1),
4068 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4069 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4071 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4072 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4073 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4074 D(ModRM | SrcMem | NoAccess | DstReg),
4075 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4078 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4080 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4081 I(SrcImmFAddr | No64, em_call_far), N,
4082 II(ImplicitOps | Stack, em_pushf, pushf),
4083 II(ImplicitOps | Stack, em_popf, popf),
4084 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4086 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4087 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4088 I2bv(SrcSI | DstDI | Mov | String, em_mov),
4089 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r),
4091 F2bv(DstAcc | SrcImm | NoWrite, em_test),
4092 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4093 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4094 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4096 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4098 X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4100 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4101 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4102 I(ImplicitOps | NearBranch, em_ret),
4103 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4104 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4105 G(ByteOp, group11), G(0, group11),
4107 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4108 I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4109 I(ImplicitOps, em_ret_far),
4110 D(ImplicitOps), DI(SrcImmByte, intn),
4111 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4113 G(Src2One | ByteOp, group2), G(Src2One, group2),
4114 G(Src2CL | ByteOp, group2), G(Src2CL, group2),
4115 I(DstAcc | SrcImmUByte | No64, em_aam),
4116 I(DstAcc | SrcImmUByte | No64, em_aad),
4117 F(DstAcc | ByteOp | No64, em_salc),
4118 I(DstAcc | SrcXLat | ByteOp, em_mov),
4120 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4122 X3(I(SrcImmByte | NearBranch, em_loop)),
4123 I(SrcImmByte | NearBranch, em_jcxz),
4124 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in),
4125 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4127 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4128 I(SrcImmFAddr | No64, em_jmp_far),
4129 D(SrcImmByte | ImplicitOps | NearBranch),
4130 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in),
4131 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4133 N, DI(ImplicitOps, icebp), N, N,
4134 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4135 G(ByteOp, group3), G(0, group3),
4137 D(ImplicitOps), D(ImplicitOps),
4138 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4139 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4142 static const struct opcode twobyte_table[256] = {
4144 G(0, group6), GD(0, &group7), N, N,
4145 N, I(ImplicitOps | EmulateOnUD, em_syscall),
4146 II(ImplicitOps | Priv, em_clts, clts), N,
4147 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4148 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4150 N, N, N, N, N, N, N, N,
4151 D(ImplicitOps | ModRM | SrcMem | NoAccess),
4152 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4154 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4155 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4156 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4158 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4161 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4162 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4163 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4166 II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4167 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4168 II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4169 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4170 I(ImplicitOps | EmulateOnUD, em_sysenter),
4171 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4173 N, N, N, N, N, N, N, N,
4175 X16(D(DstReg | SrcMem | ModRM)),
4177 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4182 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4187 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4189 X16(D(SrcImm | NearBranch)),
4191 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4193 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4194 II(ImplicitOps, em_cpuid, cpuid),
4195 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4196 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4197 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4199 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4200 DI(ImplicitOps, rsm),
4201 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4202 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4203 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4204 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4206 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
4207 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4208 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4209 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4210 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4211 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4215 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4216 I(DstReg | SrcMem | ModRM, em_bsf_c),
4217 I(DstReg | SrcMem | ModRM, em_bsr_c),
4218 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4220 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4221 N, ID(0, &instr_dual_0f_c3),
4222 N, N, N, GD(0, &group9),
4224 X8(I(DstReg, em_bswap)),
4226 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4228 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4229 N, N, N, N, N, N, N, N,
4231 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4234 static const struct instr_dual instr_dual_0f_38_f0 = {
4235 I(DstReg | SrcMem | Mov, em_movbe), N
4238 static const struct instr_dual instr_dual_0f_38_f1 = {
4239 I(DstMem | SrcReg | Mov, em_movbe), N
4242 static const struct gprefix three_byte_0f_38_f0 = {
4243 ID(0, &instr_dual_0f_38_f0), N, N, N
4246 static const struct gprefix three_byte_0f_38_f1 = {
4247 ID(0, &instr_dual_0f_38_f1), N, N, N
4251 * Insns below are selected by the prefix which indexed by the third opcode
4254 static const struct opcode opcode_map_0f_38[256] = {
4256 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4258 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4260 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4261 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
4282 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4286 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4292 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4293 unsigned size, bool sign_extension)
4295 int rc = X86EMUL_CONTINUE;
4299 op->addr.mem.ea = ctxt->_eip;
4300 /* NB. Immediates are sign-extended as necessary. */
4301 switch (op->bytes) {
4303 op->val = insn_fetch(s8, ctxt);
4306 op->val = insn_fetch(s16, ctxt);
4309 op->val = insn_fetch(s32, ctxt);
4312 op->val = insn_fetch(s64, ctxt);
4315 if (!sign_extension) {
4316 switch (op->bytes) {
4324 op->val &= 0xffffffff;
4332 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4335 int rc = X86EMUL_CONTINUE;
4339 decode_register_operand(ctxt, op);
4342 rc = decode_imm(ctxt, op, 1, false);
4345 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4349 if (ctxt->d & BitOp)
4350 fetch_bit_operand(ctxt);
4351 op->orig_val = op->val;
4354 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4358 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4359 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4360 fetch_register_operand(op);
4361 op->orig_val = op->val;
4365 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4366 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4367 fetch_register_operand(op);
4368 op->orig_val = op->val;
4371 if (ctxt->d & ByteOp) {
4376 op->bytes = ctxt->op_bytes;
4377 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4378 fetch_register_operand(op);
4379 op->orig_val = op->val;
4383 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4385 register_address(ctxt, VCPU_REGS_RDI);
4386 op->addr.mem.seg = VCPU_SREG_ES;
4393 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4394 fetch_register_operand(op);
4399 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4402 rc = decode_imm(ctxt, op, 1, true);
4410 rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4413 rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
4416 ctxt->memop.bytes = 1;
4417 if (ctxt->memop.type == OP_REG) {
4418 ctxt->memop.addr.reg = decode_register(ctxt,
4419 ctxt->modrm_rm, true);
4420 fetch_register_operand(&ctxt->memop);
4424 ctxt->memop.bytes = 2;
4427 ctxt->memop.bytes = 4;
4430 rc = decode_imm(ctxt, op, 2, false);
4433 rc = decode_imm(ctxt, op, imm_size(ctxt), false);
4437 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4439 register_address(ctxt, VCPU_REGS_RSI);
4440 op->addr.mem.seg = ctxt->seg_override;
4446 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4449 reg_read(ctxt, VCPU_REGS_RBX) +
4450 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
4451 op->addr.mem.seg = ctxt->seg_override;
4456 op->addr.mem.ea = ctxt->_eip;
4457 op->bytes = ctxt->op_bytes + 2;
4458 insn_fetch_arr(op->valptr, op->bytes, ctxt);
4461 ctxt->memop.bytes = ctxt->op_bytes + 2;
4465 op->val = VCPU_SREG_ES;
4469 op->val = VCPU_SREG_CS;
4473 op->val = VCPU_SREG_SS;
4477 op->val = VCPU_SREG_DS;
4481 op->val = VCPU_SREG_FS;
4485 op->val = VCPU_SREG_GS;
4488 /* Special instructions do their own operand decoding. */
4490 op->type = OP_NONE; /* Disable writeback. */
4498 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4500 int rc = X86EMUL_CONTINUE;
4501 int mode = ctxt->mode;
4502 int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4503 bool op_prefix = false;
4504 bool has_seg_override = false;
4505 struct opcode opcode;
4507 ctxt->memop.type = OP_NONE;
4508 ctxt->memopp = NULL;
4509 ctxt->_eip = ctxt->eip;
4510 ctxt->fetch.ptr = ctxt->fetch.data;
4511 ctxt->fetch.end = ctxt->fetch.data + insn_len;
4512 ctxt->opcode_len = 1;
4514 memcpy(ctxt->fetch.data, insn, insn_len);
4516 rc = __do_insn_fetch_bytes(ctxt, 1);
4517 if (rc != X86EMUL_CONTINUE)
4522 case X86EMUL_MODE_REAL:
4523 case X86EMUL_MODE_VM86:
4524 case X86EMUL_MODE_PROT16:
4525 def_op_bytes = def_ad_bytes = 2;
4527 case X86EMUL_MODE_PROT32:
4528 def_op_bytes = def_ad_bytes = 4;
4530 #ifdef CONFIG_X86_64
4531 case X86EMUL_MODE_PROT64:
4537 return EMULATION_FAILED;
4540 ctxt->op_bytes = def_op_bytes;
4541 ctxt->ad_bytes = def_ad_bytes;
4543 /* Legacy prefixes. */
4545 switch (ctxt->b = insn_fetch(u8, ctxt)) {
4546 case 0x66: /* operand-size override */
4548 /* switch between 2/4 bytes */
4549 ctxt->op_bytes = def_op_bytes ^ 6;
4551 case 0x67: /* address-size override */
4552 if (mode == X86EMUL_MODE_PROT64)
4553 /* switch between 4/8 bytes */
4554 ctxt->ad_bytes = def_ad_bytes ^ 12;
4556 /* switch between 2/4 bytes */
4557 ctxt->ad_bytes = def_ad_bytes ^ 6;
4559 case 0x26: /* ES override */
4560 case 0x2e: /* CS override */
4561 case 0x36: /* SS override */
4562 case 0x3e: /* DS override */
4563 has_seg_override = true;
4564 ctxt->seg_override = (ctxt->b >> 3) & 3;
4566 case 0x64: /* FS override */
4567 case 0x65: /* GS override */
4568 has_seg_override = true;
4569 ctxt->seg_override = ctxt->b & 7;
4571 case 0x40 ... 0x4f: /* REX */
4572 if (mode != X86EMUL_MODE_PROT64)
4574 ctxt->rex_prefix = ctxt->b;
4576 case 0xf0: /* LOCK */
4577 ctxt->lock_prefix = 1;
4579 case 0xf2: /* REPNE/REPNZ */
4580 case 0xf3: /* REP/REPE/REPZ */
4581 ctxt->rep_prefix = ctxt->b;
4587 /* Any legacy prefix after a REX prefix nullifies its effect. */
4589 ctxt->rex_prefix = 0;
4595 if (ctxt->rex_prefix & 8)
4596 ctxt->op_bytes = 8; /* REX.W */
4598 /* Opcode byte(s). */
4599 opcode = opcode_table[ctxt->b];
4600 /* Two-byte opcode? */
4601 if (ctxt->b == 0x0f) {
4602 ctxt->opcode_len = 2;
4603 ctxt->b = insn_fetch(u8, ctxt);
4604 opcode = twobyte_table[ctxt->b];
4606 /* 0F_38 opcode map */
4607 if (ctxt->b == 0x38) {
4608 ctxt->opcode_len = 3;
4609 ctxt->b = insn_fetch(u8, ctxt);
4610 opcode = opcode_map_0f_38[ctxt->b];
4613 ctxt->d = opcode.flags;
4615 if (ctxt->d & ModRM)
4616 ctxt->modrm = insn_fetch(u8, ctxt);
4618 /* vex-prefix instructions are not implemented */
4619 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
4620 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
4624 while (ctxt->d & GroupMask) {
4625 switch (ctxt->d & GroupMask) {
4627 goffset = (ctxt->modrm >> 3) & 7;
4628 opcode = opcode.u.group[goffset];
4631 goffset = (ctxt->modrm >> 3) & 7;
4632 if ((ctxt->modrm >> 6) == 3)
4633 opcode = opcode.u.gdual->mod3[goffset];
4635 opcode = opcode.u.gdual->mod012[goffset];
4638 goffset = ctxt->modrm & 7;
4639 opcode = opcode.u.group[goffset];
4642 if (ctxt->rep_prefix && op_prefix)
4643 return EMULATION_FAILED;
4644 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4645 switch (simd_prefix) {
4646 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
4647 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
4648 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
4649 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
4653 if (ctxt->modrm > 0xbf)
4654 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
4656 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
4659 if ((ctxt->modrm >> 6) == 3)
4660 opcode = opcode.u.idual->mod3;
4662 opcode = opcode.u.idual->mod012;
4665 if (ctxt->mode == X86EMUL_MODE_PROT64)
4666 opcode = opcode.u.mdual->mode64;
4668 opcode = opcode.u.mdual->mode32;
4671 return EMULATION_FAILED;
4674 ctxt->d &= ~(u64)GroupMask;
4675 ctxt->d |= opcode.flags;
4680 return EMULATION_FAILED;
4682 ctxt->execute = opcode.u.execute;
4684 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
4685 return EMULATION_FAILED;
4687 if (unlikely(ctxt->d &
4688 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
4691 * These are copied unconditionally here, and checked unconditionally
4692 * in x86_emulate_insn.
4694 ctxt->check_perm = opcode.check_perm;
4695 ctxt->intercept = opcode.intercept;
4697 if (ctxt->d & NotImpl)
4698 return EMULATION_FAILED;
4700 if (mode == X86EMUL_MODE_PROT64) {
4701 if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
4703 else if (ctxt->d & NearBranch)
4707 if (ctxt->d & Op3264) {
4708 if (mode == X86EMUL_MODE_PROT64)
4714 if ((ctxt->d & No16) && ctxt->op_bytes == 2)
4718 ctxt->op_bytes = 16;
4719 else if (ctxt->d & Mmx)
4723 /* ModRM and SIB bytes. */
4724 if (ctxt->d & ModRM) {
4725 rc = decode_modrm(ctxt, &ctxt->memop);
4726 if (!has_seg_override) {
4727 has_seg_override = true;
4728 ctxt->seg_override = ctxt->modrm_seg;
4730 } else if (ctxt->d & MemAbs)
4731 rc = decode_abs(ctxt, &ctxt->memop);
4732 if (rc != X86EMUL_CONTINUE)
4735 if (!has_seg_override)
4736 ctxt->seg_override = VCPU_SREG_DS;
4738 ctxt->memop.addr.mem.seg = ctxt->seg_override;
4741 * Decode and fetch the source operand: register, memory
4744 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4745 if (rc != X86EMUL_CONTINUE)
4749 * Decode and fetch the second source operand: register, memory
4752 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4753 if (rc != X86EMUL_CONTINUE)
4756 /* Decode and fetch the destination operand: register or memory. */
4757 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4759 if (ctxt->rip_relative)
4760 ctxt->memopp->addr.mem.ea = address_mask(ctxt,
4761 ctxt->memopp->addr.mem.ea + ctxt->_eip);
4764 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4767 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
4769 return ctxt->d & PageTable;
4772 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
4774 /* The second termination condition only applies for REPE
4775 * and REPNE. Test if the repeat string operation prefix is
4776 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
4777 * corresponding termination condition according to:
4778 * - if REPE/REPZ and ZF = 0 then done
4779 * - if REPNE/REPNZ and ZF = 1 then done
4781 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
4782 (ctxt->b == 0xae) || (ctxt->b == 0xaf))
4783 && (((ctxt->rep_prefix == REPE_PREFIX) &&
4784 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
4785 || ((ctxt->rep_prefix == REPNE_PREFIX) &&
4786 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
4792 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
4796 ctxt->ops->get_fpu(ctxt);
4797 asm volatile("1: fwait \n\t"
4799 ".pushsection .fixup,\"ax\" \n\t"
4801 "movb $1, %[fault] \n\t"
4804 _ASM_EXTABLE(1b, 3b)
4805 : [fault]"+qm"(fault));
4806 ctxt->ops->put_fpu(ctxt);
4808 if (unlikely(fault))
4809 return emulate_exception(ctxt, MF_VECTOR, 0, false);
4811 return X86EMUL_CONTINUE;
4814 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
4817 if (op->type == OP_MM)
4818 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
4821 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
4823 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4824 if (!(ctxt->d & ByteOp))
4825 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4826 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4827 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
4829 : "c"(ctxt->src2.val));
4830 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4831 if (!fop) /* exception is returned in fop variable */
4832 return emulate_de(ctxt);
4833 return X86EMUL_CONTINUE;
4836 void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4838 memset(&ctxt->rip_relative, 0,
4839 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
4841 ctxt->io_read.pos = 0;
4842 ctxt->io_read.end = 0;
4843 ctxt->mem_read.end = 0;
4846 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4848 const struct x86_emulate_ops *ops = ctxt->ops;
4849 int rc = X86EMUL_CONTINUE;
4850 int saved_dst_type = ctxt->dst.type;
4852 ctxt->mem_read.pos = 0;
4854 /* LOCK prefix is allowed only with some instructions */
4855 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4856 rc = emulate_ud(ctxt);
4860 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4861 rc = emulate_ud(ctxt);
4865 if (unlikely(ctxt->d &
4866 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
4867 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
4868 (ctxt->d & Undefined)) {
4869 rc = emulate_ud(ctxt);
4873 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
4874 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
4875 rc = emulate_ud(ctxt);
4879 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
4880 rc = emulate_nm(ctxt);
4884 if (ctxt->d & Mmx) {
4885 rc = flush_pending_x87_faults(ctxt);
4886 if (rc != X86EMUL_CONTINUE)
4889 * Now that we know the fpu is exception safe, we can fetch
4892 fetch_possible_mmx_operand(ctxt, &ctxt->src);
4893 fetch_possible_mmx_operand(ctxt, &ctxt->src2);
4894 if (!(ctxt->d & Mov))
4895 fetch_possible_mmx_operand(ctxt, &ctxt->dst);
4898 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4899 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4900 X86_ICPT_PRE_EXCEPT);
4901 if (rc != X86EMUL_CONTINUE)
4905 /* Instruction can only be executed in protected mode */
4906 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
4907 rc = emulate_ud(ctxt);
4911 /* Privileged instruction can be executed only in CPL=0 */
4912 if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4913 if (ctxt->d & PrivUD)
4914 rc = emulate_ud(ctxt);
4916 rc = emulate_gp(ctxt, 0);
4920 /* Do instruction specific permission checks */
4921 if (ctxt->d & CheckPerm) {
4922 rc = ctxt->check_perm(ctxt);
4923 if (rc != X86EMUL_CONTINUE)
4927 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4928 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4929 X86_ICPT_POST_EXCEPT);
4930 if (rc != X86EMUL_CONTINUE)
4934 if (ctxt->rep_prefix && (ctxt->d & String)) {
4935 /* All REP prefixes have the same first termination condition */
4936 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
4937 string_registers_quirk(ctxt);
4938 ctxt->eip = ctxt->_eip;
4939 ctxt->eflags &= ~X86_EFLAGS_RF;
4945 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
4946 rc = segmented_read(ctxt, ctxt->src.addr.mem,
4947 ctxt->src.valptr, ctxt->src.bytes);
4948 if (rc != X86EMUL_CONTINUE)
4950 ctxt->src.orig_val64 = ctxt->src.val64;
4953 if (ctxt->src2.type == OP_MEM) {
4954 rc = segmented_read(ctxt, ctxt->src2.addr.mem,
4955 &ctxt->src2.val, ctxt->src2.bytes);
4956 if (rc != X86EMUL_CONTINUE)
4960 if ((ctxt->d & DstMask) == ImplicitOps)
4964 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4965 /* optimisation - avoid slow emulated read if Mov */
4966 rc = segmented_read(ctxt, ctxt->dst.addr.mem,
4967 &ctxt->dst.val, ctxt->dst.bytes);
4968 if (rc != X86EMUL_CONTINUE) {
4969 if (!(ctxt->d & NoWrite) &&
4970 rc == X86EMUL_PROPAGATE_FAULT &&
4971 ctxt->exception.vector == PF_VECTOR)
4972 ctxt->exception.error_code |= PFERR_WRITE_MASK;
4976 /* Copy full 64-bit value for CMPXCHG8B. */
4977 ctxt->dst.orig_val64 = ctxt->dst.val64;
4981 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4982 rc = emulator_check_intercept(ctxt, ctxt->intercept,
4983 X86_ICPT_POST_MEMACCESS);
4984 if (rc != X86EMUL_CONTINUE)
4988 if (ctxt->rep_prefix && (ctxt->d & String))
4989 ctxt->eflags |= X86_EFLAGS_RF;
4991 ctxt->eflags &= ~X86_EFLAGS_RF;
4993 if (ctxt->execute) {
4994 if (ctxt->d & Fastop) {
4995 void (*fop)(struct fastop *) = (void *)ctxt->execute;
4996 rc = fastop(ctxt, fop);
4997 if (rc != X86EMUL_CONTINUE)
5001 rc = ctxt->execute(ctxt);
5002 if (rc != X86EMUL_CONTINUE)
5007 if (ctxt->opcode_len == 2)
5009 else if (ctxt->opcode_len == 3)
5010 goto threebyte_insn;
5013 case 0x70 ... 0x7f: /* jcc (short) */
5014 if (test_cc(ctxt->b, ctxt->eflags))
5015 rc = jmp_rel(ctxt, ctxt->src.val);
5017 case 0x8d: /* lea r16/r32, m */
5018 ctxt->dst.val = ctxt->src.addr.mem.ea;
5020 case 0x90 ... 0x97: /* nop / xchg reg, rax */
5021 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
5022 ctxt->dst.type = OP_NONE;
5026 case 0x98: /* cbw/cwde/cdqe */
5027 switch (ctxt->op_bytes) {
5028 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5029 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5030 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
5033 case 0xcc: /* int3 */
5034 rc = emulate_int(ctxt, 3);
5036 case 0xcd: /* int n */
5037 rc = emulate_int(ctxt, ctxt->src.val);
5039 case 0xce: /* into */
5040 if (ctxt->eflags & X86_EFLAGS_OF)
5041 rc = emulate_int(ctxt, 4);
5043 case 0xe9: /* jmp rel */
5044 case 0xeb: /* jmp rel short */
5045 rc = jmp_rel(ctxt, ctxt->src.val);
5046 ctxt->dst.type = OP_NONE; /* Disable writeback. */
5048 case 0xf4: /* hlt */
5049 ctxt->ops->halt(ctxt);
5051 case 0xf5: /* cmc */
5052 /* complement carry flag from eflags reg */
5053 ctxt->eflags ^= X86_EFLAGS_CF;
5055 case 0xf8: /* clc */
5056 ctxt->eflags &= ~X86_EFLAGS_CF;
5058 case 0xf9: /* stc */
5059 ctxt->eflags |= X86_EFLAGS_CF;
5061 case 0xfc: /* cld */
5062 ctxt->eflags &= ~X86_EFLAGS_DF;
5064 case 0xfd: /* std */
5065 ctxt->eflags |= X86_EFLAGS_DF;
5068 goto cannot_emulate;
5071 if (rc != X86EMUL_CONTINUE)
5075 if (ctxt->d & SrcWrite) {
5076 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5077 rc = writeback(ctxt, &ctxt->src);
5078 if (rc != X86EMUL_CONTINUE)
5081 if (!(ctxt->d & NoWrite)) {
5082 rc = writeback(ctxt, &ctxt->dst);
5083 if (rc != X86EMUL_CONTINUE)
5088 * restore dst type in case the decoding will be reused
5089 * (happens for string instruction )
5091 ctxt->dst.type = saved_dst_type;
5093 if ((ctxt->d & SrcMask) == SrcSI)
5094 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5096 if ((ctxt->d & DstMask) == DstDI)
5097 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5099 if (ctxt->rep_prefix && (ctxt->d & String)) {
5101 struct read_cache *r = &ctxt->io_read;
5102 if ((ctxt->d & SrcMask) == SrcSI)
5103 count = ctxt->src.count;
5105 count = ctxt->dst.count;
5106 register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5108 if (!string_insn_completed(ctxt)) {
5110 * Re-enter guest when pio read ahead buffer is empty
5111 * or, if it is not used, after each 1024 iteration.
5113 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5114 (r->end == 0 || r->end != r->pos)) {
5116 * Reset read cache. Usually happens before
5117 * decode, but since instruction is restarted
5118 * we have to do it here.
5120 ctxt->mem_read.end = 0;
5121 writeback_registers(ctxt);
5122 return EMULATION_RESTART;
5124 goto done; /* skip rip writeback */
5126 ctxt->eflags &= ~X86_EFLAGS_RF;
5129 ctxt->eip = ctxt->_eip;
5132 if (rc == X86EMUL_PROPAGATE_FAULT) {
5133 WARN_ON(ctxt->exception.vector > 0x1f);
5134 ctxt->have_exception = true;
5136 if (rc == X86EMUL_INTERCEPTED)
5137 return EMULATION_INTERCEPTED;
5139 if (rc == X86EMUL_CONTINUE)
5140 writeback_registers(ctxt);
5142 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
5146 case 0x09: /* wbinvd */
5147 (ctxt->ops->wbinvd)(ctxt);
5149 case 0x08: /* invd */
5150 case 0x0d: /* GrpP (prefetch) */
5151 case 0x18: /* Grp16 (prefetch/nop) */
5152 case 0x1f: /* nop */
5154 case 0x20: /* mov cr, reg */
5155 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5157 case 0x21: /* mov from dr to reg */
5158 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
5160 case 0x40 ... 0x4f: /* cmov */
5161 if (test_cc(ctxt->b, ctxt->eflags))
5162 ctxt->dst.val = ctxt->src.val;
5163 else if (ctxt->op_bytes != 4)
5164 ctxt->dst.type = OP_NONE; /* no writeback */
5166 case 0x80 ... 0x8f: /* jnz rel, etc*/
5167 if (test_cc(ctxt->b, ctxt->eflags))
5168 rc = jmp_rel(ctxt, ctxt->src.val);
5170 case 0x90 ... 0x9f: /* setcc r/m8 */
5171 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5173 case 0xb6 ... 0xb7: /* movzx */
5174 ctxt->dst.bytes = ctxt->op_bytes;
5175 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5176 : (u16) ctxt->src.val;
5178 case 0xbe ... 0xbf: /* movsx */
5179 ctxt->dst.bytes = ctxt->op_bytes;
5180 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5181 (s16) ctxt->src.val;
5184 goto cannot_emulate;
5189 if (rc != X86EMUL_CONTINUE)
5195 return EMULATION_FAILED;
5198 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5200 invalidate_registers(ctxt);
5203 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5205 writeback_registers(ctxt);