2 * 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
29 #include <linux/bitops.h>
32 #include <linux/kvm_host.h>
35 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
37 s->isr &= ~(1 << irq);
38 s->isr_ack |= (1 << irq);
39 if (s != &s->pics_state->pics[0])
42 * We are dropping lock while calling ack notifiers since ack
43 * notifier callbacks for assigned devices call into PIC recursively.
44 * Other interrupt may be delivered to PIC while lock is dropped but
45 * it should be safe since PIC state is already updated at this stage.
47 spin_unlock(&s->pics_state->lock);
48 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
49 spin_lock(&s->pics_state->lock);
52 void kvm_pic_clear_isr_ack(struct kvm *kvm)
54 struct kvm_pic *s = pic_irqchip(kvm);
56 s->pics[0].isr_ack = 0xff;
57 s->pics[1].isr_ack = 0xff;
58 spin_unlock(&s->lock);
62 * set irq level. If an edge is detected, then the IRR is set to 1
64 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
68 if (s->elcr & mask) /* level triggered */
70 ret = !(s->irr & mask);
77 else /* edge triggered */
79 if ((s->last_irr & mask) == 0) {
80 ret = !(s->irr & mask);
87 return (s->imr & mask) ? -1 : ret;
91 * return the highest priority found in mask (highest = smallest
92 * number). Return 8 if no irq
94 static inline int get_priority(struct kvm_kpic_state *s, int mask)
100 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
106 * return the pic wanted interrupt. return -1 if none
108 static int pic_get_irq(struct kvm_kpic_state *s)
110 int mask, cur_priority, priority;
112 mask = s->irr & ~s->imr;
113 priority = get_priority(s, mask);
117 * compute current priority. If special fully nested mode on the
118 * master, the IRQ coming from the slave is not taken into account
119 * for the priority computation.
122 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
124 cur_priority = get_priority(s, mask);
125 if (priority < cur_priority)
127 * higher priority found: an irq should be generated
129 return (priority + s->priority_add) & 7;
135 * raise irq to CPU if necessary. must be called every time the active
138 static void pic_update_irq(struct kvm_pic *s)
142 irq2 = pic_get_irq(&s->pics[1]);
145 * if irq request by slave pic, signal master PIC
147 pic_set_irq1(&s->pics[0], 2, 1);
148 pic_set_irq1(&s->pics[0], 2, 0);
150 irq = pic_get_irq(&s->pics[0]);
152 s->irq_request(s->irq_request_opaque, 1);
154 s->irq_request(s->irq_request_opaque, 0);
157 void kvm_pic_update_irq(struct kvm_pic *s)
161 spin_unlock(&s->lock);
164 int kvm_pic_set_irq(void *opaque, int irq, int level)
166 struct kvm_pic *s = opaque;
170 if (irq >= 0 && irq < PIC_NUM_PINS) {
171 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
173 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
174 s->pics[irq >> 3].imr, ret == 0);
176 spin_unlock(&s->lock);
182 * acknowledge interrupt 'irq'
184 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
188 * We don't clear a level sensitive interrupt here
190 if (!(s->elcr & (1 << irq)))
191 s->irr &= ~(1 << irq);
194 if (s->rotate_on_auto_eoi)
195 s->priority_add = (irq + 1) & 7;
196 pic_clear_isr(s, irq);
201 int kvm_pic_read_irq(struct kvm *kvm)
203 int irq, irq2, intno;
204 struct kvm_pic *s = pic_irqchip(kvm);
207 irq = pic_get_irq(&s->pics[0]);
209 pic_intack(&s->pics[0], irq);
211 irq2 = pic_get_irq(&s->pics[1]);
213 pic_intack(&s->pics[1], irq2);
216 * spurious IRQ on slave controller
219 intno = s->pics[1].irq_base + irq2;
222 intno = s->pics[0].irq_base + irq;
225 * spurious IRQ on host controller
228 intno = s->pics[0].irq_base + irq;
231 spin_unlock(&s->lock);
236 void kvm_pic_reset(struct kvm_kpic_state *s)
239 struct kvm *kvm = s->pics_state->irq_request_opaque;
240 struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu;
241 u8 irr = s->irr, isr = s->imr;
250 s->read_reg_select = 0;
255 s->rotate_on_auto_eoi = 0;
256 s->special_fully_nested_mode = 0;
259 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
260 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
261 if (irr & (1 << irq) || isr & (1 << irq)) {
262 pic_clear_isr(s, irq);
267 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
269 struct kvm_kpic_state *s = opaque;
270 int priority, cmd, irq;
275 kvm_pic_reset(s); /* init */
277 * deassert a pending interrupt
279 s->pics_state->irq_request(s->pics_state->
280 irq_request_opaque, 0);
284 printk(KERN_ERR "single mode not supported");
287 "level sensitive irq not supported");
288 } else if (val & 0x08) {
292 s->read_reg_select = val & 1;
294 s->special_mask = (val >> 5) & 1;
300 s->rotate_on_auto_eoi = cmd >> 2;
302 case 1: /* end of interrupt */
304 priority = get_priority(s, s->isr);
306 irq = (priority + s->priority_add) & 7;
308 s->priority_add = (irq + 1) & 7;
309 pic_clear_isr(s, irq);
310 pic_update_irq(s->pics_state);
315 pic_clear_isr(s, irq);
316 pic_update_irq(s->pics_state);
319 s->priority_add = (val + 1) & 7;
320 pic_update_irq(s->pics_state);
324 s->priority_add = (irq + 1) & 7;
325 pic_clear_isr(s, irq);
326 pic_update_irq(s->pics_state);
329 break; /* no operation */
333 switch (s->init_state) {
334 case 0: /* normal mode */
336 pic_update_irq(s->pics_state);
339 s->irq_base = val & 0xf8;
349 s->special_fully_nested_mode = (val >> 4) & 1;
350 s->auto_eoi = (val >> 1) & 1;
356 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
360 ret = pic_get_irq(s);
363 s->pics_state->pics[0].isr &= ~(1 << 2);
364 s->pics_state->pics[0].irr &= ~(1 << 2);
366 s->irr &= ~(1 << ret);
367 pic_clear_isr(s, ret);
368 if (addr1 >> 7 || ret != 2)
369 pic_update_irq(s->pics_state);
372 pic_update_irq(s->pics_state);
378 static u32 pic_ioport_read(void *opaque, u32 addr1)
380 struct kvm_kpic_state *s = opaque;
387 ret = pic_poll_read(s, addr1);
391 if (s->read_reg_select)
400 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
402 struct kvm_kpic_state *s = opaque;
403 s->elcr = val & s->elcr_mask;
406 static u32 elcr_ioport_read(void *opaque, u32 addr1)
408 struct kvm_kpic_state *s = opaque;
412 static int picdev_in_range(gpa_t addr)
427 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
429 return container_of(dev, struct kvm_pic, dev);
432 static int picdev_write(struct kvm_io_device *this,
433 gpa_t addr, int len, const void *val)
435 struct kvm_pic *s = to_pic(this);
436 unsigned char data = *(unsigned char *)val;
437 if (!picdev_in_range(addr))
441 if (printk_ratelimit())
442 printk(KERN_ERR "PIC: non byte write\n");
451 pic_ioport_write(&s->pics[addr >> 7], addr, data);
455 elcr_ioport_write(&s->pics[addr & 1], addr, data);
458 spin_unlock(&s->lock);
462 static int picdev_read(struct kvm_io_device *this,
463 gpa_t addr, int len, void *val)
465 struct kvm_pic *s = to_pic(this);
466 unsigned char data = 0;
467 if (!picdev_in_range(addr))
471 if (printk_ratelimit())
472 printk(KERN_ERR "PIC: non byte read\n");
481 data = pic_ioport_read(&s->pics[addr >> 7], addr);
485 data = elcr_ioport_read(&s->pics[addr & 1], addr);
488 *(unsigned char *)val = data;
489 spin_unlock(&s->lock);
494 * callback when PIC0 irq status changed
496 static void pic_irq_request(void *opaque, int level)
498 struct kvm *kvm = opaque;
499 struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
500 struct kvm_pic *s = pic_irqchip(kvm);
501 int irq = pic_get_irq(&s->pics[0]);
504 if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
505 s->pics[0].isr_ack &= ~(1 << irq);
510 static const struct kvm_io_device_ops picdev_ops = {
512 .write = picdev_write,
515 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
520 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
523 spin_lock_init(&s->lock);
525 s->pics[0].elcr_mask = 0xf8;
526 s->pics[1].elcr_mask = 0xde;
527 s->irq_request = pic_irq_request;
528 s->irq_request_opaque = kvm;
529 s->pics[0].pics_state = s;
530 s->pics[1].pics_state = s;
533 * Initialize PIO device
535 kvm_iodevice_init(&s->dev, &picdev_ops);
536 ret = kvm_io_bus_register_dev(kvm, &kvm->pio_bus, &s->dev);