2 * 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
29 #include <linux/bitops.h>
32 #include <linux/kvm_host.h>
35 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
37 s->isr &= ~(1 << irq);
38 s->isr_ack |= (1 << irq);
39 if (s != &s->pics_state->pics[0])
42 * We are dropping lock while calling ack notifiers since ack
43 * notifier callbacks for assigned devices call into PIC recursively.
44 * Other interrupt may be delivered to PIC while lock is dropped but
45 * it should be safe since PIC state is already updated at this stage.
47 raw_spin_unlock(&s->pics_state->lock);
48 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
49 raw_spin_lock(&s->pics_state->lock);
52 void kvm_pic_clear_isr_ack(struct kvm *kvm)
54 struct kvm_pic *s = pic_irqchip(kvm);
56 raw_spin_lock(&s->lock);
57 s->pics[0].isr_ack = 0xff;
58 s->pics[1].isr_ack = 0xff;
59 raw_spin_unlock(&s->lock);
63 * set irq level. If an edge is detected, then the IRR is set to 1
65 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
69 if (s->elcr & mask) /* level triggered */
71 ret = !(s->irr & mask);
78 else /* edge triggered */
80 if ((s->last_irr & mask) == 0) {
81 ret = !(s->irr & mask);
88 return (s->imr & mask) ? -1 : ret;
92 * return the highest priority found in mask (highest = smallest
93 * number). Return 8 if no irq
95 static inline int get_priority(struct kvm_kpic_state *s, int mask)
101 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
107 * return the pic wanted interrupt. return -1 if none
109 static int pic_get_irq(struct kvm_kpic_state *s)
111 int mask, cur_priority, priority;
113 mask = s->irr & ~s->imr;
114 priority = get_priority(s, mask);
118 * compute current priority. If special fully nested mode on the
119 * master, the IRQ coming from the slave is not taken into account
120 * for the priority computation.
123 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
125 cur_priority = get_priority(s, mask);
126 if (priority < cur_priority)
128 * higher priority found: an irq should be generated
130 return (priority + s->priority_add) & 7;
136 * raise irq to CPU if necessary. must be called every time the active
139 static void pic_update_irq(struct kvm_pic *s)
143 irq2 = pic_get_irq(&s->pics[1]);
146 * if irq request by slave pic, signal master PIC
148 pic_set_irq1(&s->pics[0], 2, 1);
149 pic_set_irq1(&s->pics[0], 2, 0);
151 irq = pic_get_irq(&s->pics[0]);
153 s->irq_request(s->irq_request_opaque, 1);
155 s->irq_request(s->irq_request_opaque, 0);
158 void kvm_pic_update_irq(struct kvm_pic *s)
160 raw_spin_lock(&s->lock);
162 raw_spin_unlock(&s->lock);
165 int kvm_pic_set_irq(void *opaque, int irq, int level)
167 struct kvm_pic *s = opaque;
170 raw_spin_lock(&s->lock);
171 if (irq >= 0 && irq < PIC_NUM_PINS) {
172 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
174 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
175 s->pics[irq >> 3].imr, ret == 0);
177 raw_spin_unlock(&s->lock);
183 * acknowledge interrupt 'irq'
185 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
189 * We don't clear a level sensitive interrupt here
191 if (!(s->elcr & (1 << irq)))
192 s->irr &= ~(1 << irq);
195 if (s->rotate_on_auto_eoi)
196 s->priority_add = (irq + 1) & 7;
197 pic_clear_isr(s, irq);
202 int kvm_pic_read_irq(struct kvm *kvm)
204 int irq, irq2, intno;
205 struct kvm_pic *s = pic_irqchip(kvm);
207 raw_spin_lock(&s->lock);
208 irq = pic_get_irq(&s->pics[0]);
210 pic_intack(&s->pics[0], irq);
212 irq2 = pic_get_irq(&s->pics[1]);
214 pic_intack(&s->pics[1], irq2);
217 * spurious IRQ on slave controller
220 intno = s->pics[1].irq_base + irq2;
223 intno = s->pics[0].irq_base + irq;
226 * spurious IRQ on host controller
229 intno = s->pics[0].irq_base + irq;
232 raw_spin_unlock(&s->lock);
237 void kvm_pic_reset(struct kvm_kpic_state *s)
240 struct kvm *kvm = s->pics_state->irq_request_opaque;
241 struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu;
242 u8 irr = s->irr, isr = s->imr;
251 s->read_reg_select = 0;
256 s->rotate_on_auto_eoi = 0;
257 s->special_fully_nested_mode = 0;
260 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
261 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
262 if (irr & (1 << irq) || isr & (1 << irq)) {
263 pic_clear_isr(s, irq);
268 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
270 struct kvm_kpic_state *s = opaque;
271 int priority, cmd, irq;
276 kvm_pic_reset(s); /* init */
278 * deassert a pending interrupt
280 s->pics_state->irq_request(s->pics_state->
281 irq_request_opaque, 0);
285 printk(KERN_ERR "single mode not supported");
288 "level sensitive irq not supported");
289 } else if (val & 0x08) {
293 s->read_reg_select = val & 1;
295 s->special_mask = (val >> 5) & 1;
301 s->rotate_on_auto_eoi = cmd >> 2;
303 case 1: /* end of interrupt */
305 priority = get_priority(s, s->isr);
307 irq = (priority + s->priority_add) & 7;
309 s->priority_add = (irq + 1) & 7;
310 pic_clear_isr(s, irq);
311 pic_update_irq(s->pics_state);
316 pic_clear_isr(s, irq);
317 pic_update_irq(s->pics_state);
320 s->priority_add = (val + 1) & 7;
321 pic_update_irq(s->pics_state);
325 s->priority_add = (irq + 1) & 7;
326 pic_clear_isr(s, irq);
327 pic_update_irq(s->pics_state);
330 break; /* no operation */
334 switch (s->init_state) {
335 case 0: /* normal mode */
337 pic_update_irq(s->pics_state);
340 s->irq_base = val & 0xf8;
350 s->special_fully_nested_mode = (val >> 4) & 1;
351 s->auto_eoi = (val >> 1) & 1;
357 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
361 ret = pic_get_irq(s);
364 s->pics_state->pics[0].isr &= ~(1 << 2);
365 s->pics_state->pics[0].irr &= ~(1 << 2);
367 s->irr &= ~(1 << ret);
368 pic_clear_isr(s, ret);
369 if (addr1 >> 7 || ret != 2)
370 pic_update_irq(s->pics_state);
373 pic_update_irq(s->pics_state);
379 static u32 pic_ioport_read(void *opaque, u32 addr1)
381 struct kvm_kpic_state *s = opaque;
388 ret = pic_poll_read(s, addr1);
392 if (s->read_reg_select)
401 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
403 struct kvm_kpic_state *s = opaque;
404 s->elcr = val & s->elcr_mask;
407 static u32 elcr_ioport_read(void *opaque, u32 addr1)
409 struct kvm_kpic_state *s = opaque;
413 static int picdev_in_range(gpa_t addr)
428 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
430 return container_of(dev, struct kvm_pic, dev);
433 static int picdev_write(struct kvm_io_device *this,
434 gpa_t addr, int len, const void *val)
436 struct kvm_pic *s = to_pic(this);
437 unsigned char data = *(unsigned char *)val;
438 if (!picdev_in_range(addr))
442 if (printk_ratelimit())
443 printk(KERN_ERR "PIC: non byte write\n");
446 raw_spin_lock(&s->lock);
452 pic_ioport_write(&s->pics[addr >> 7], addr, data);
456 elcr_ioport_write(&s->pics[addr & 1], addr, data);
459 raw_spin_unlock(&s->lock);
463 static int picdev_read(struct kvm_io_device *this,
464 gpa_t addr, int len, void *val)
466 struct kvm_pic *s = to_pic(this);
467 unsigned char data = 0;
468 if (!picdev_in_range(addr))
472 if (printk_ratelimit())
473 printk(KERN_ERR "PIC: non byte read\n");
476 raw_spin_lock(&s->lock);
482 data = pic_ioport_read(&s->pics[addr >> 7], addr);
486 data = elcr_ioport_read(&s->pics[addr & 1], addr);
489 *(unsigned char *)val = data;
490 raw_spin_unlock(&s->lock);
495 * callback when PIC0 irq status changed
497 static void pic_irq_request(void *opaque, int level)
499 struct kvm *kvm = opaque;
500 struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
501 struct kvm_pic *s = pic_irqchip(kvm);
502 int irq = pic_get_irq(&s->pics[0]);
505 if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
506 s->pics[0].isr_ack &= ~(1 << irq);
511 static const struct kvm_io_device_ops picdev_ops = {
513 .write = picdev_write,
516 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
521 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
524 raw_spin_lock_init(&s->lock);
526 s->pics[0].elcr_mask = 0xf8;
527 s->pics[1].elcr_mask = 0xde;
528 s->irq_request = pic_irq_request;
529 s->irq_request_opaque = kvm;
530 s->pics[0].pics_state = s;
531 s->pics[1].pics_state = s;
534 * Initialize PIO device
536 kvm_iodevice_init(&s->dev, &picdev_ops);
537 mutex_lock(&kvm->slots_lock);
538 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
539 mutex_unlock(&kvm->slots_lock);
548 void kvm_destroy_pic(struct kvm *kvm)
550 struct kvm_pic *vpic = kvm->arch.vpic;
553 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
554 kvm->arch.vpic = NULL;