arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 #define APIC_BUS_CYCLE_NS 1
  58
  59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  60 #define apic_debug(fmt, arg...)
  61
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 static inline int apic_test_vector(int vec, void *bitmap)
  76 {
  77         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  78 }
  79
  80 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  81 {
  82         struct kvm_lapic *apic = vcpu->arch.apic;
  83
  84         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  85                 apic_test_vector(vector, apic->regs + APIC_IRR);
  86 }
  87
  88 static inline void apic_clear_vector(int vec, void *bitmap)
  89 {
  90         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  91 }
  92
  93 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  94 {
  95         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  96 }
  97
  98 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
  99 {
 100         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 101 }
 102
 103 struct static_key_deferred apic_hw_disabled __read_mostly;
 104 struct static_key_deferred apic_sw_disabled __read_mostly;
 105
 106 static inline int apic_enabled(struct kvm_lapic *apic)
 107 {
 108         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 109 }
 110
 111 #define LVT_MASK        \
 112         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 113
 114 #define LINT_MASK       \
 115         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 116          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 117
 118 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 119 {
 120         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 121 }
 122
 123 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 124 {
 125         return apic->vcpu->vcpu_id;
 126 }
 127
 128 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 129                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 130         switch (map->mode) {
 131         case KVM_APIC_MODE_X2APIC: {
 132                 u32 offset = (dest_id >> 16) * 16;
 133                 u32 max_apic_id = map->max_apic_id;
 134
 135                 if (offset <= max_apic_id) {
 136                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 137
 138                         *cluster = &map->phys_map[offset];
 139                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 140                 } else {
 141                         *mask = 0;
 142                 }
 143
 144                 return true;
 145                 }
 146         case KVM_APIC_MODE_XAPIC_FLAT:
 147                 *cluster = map->xapic_flat_map;
 148                 *mask = dest_id & 0xff;
 149                 return true;
 150         case KVM_APIC_MODE_XAPIC_CLUSTER:
 151                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 152                 *mask = dest_id & 0xf;
 153                 return true;
 154         default:
 155                 /* Not optimized. */
 156                 return false;
 157         }
 158 }
 159
 160 static void kvm_apic_map_free(struct rcu_head *rcu)
 161 {
 162         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 163
 164         kvfree(map);
 165 }
 166
 167 static void recalculate_apic_map(struct kvm *kvm)
 168 {
 169         struct kvm_apic_map *new, *old = NULL;
 170         struct kvm_vcpu *vcpu;
 171         int i;
 172         u32 max_id = 255; /* enough space for any xAPIC ID */
 173
 174         mutex_lock(&kvm->arch.apic_map_lock);
 175
 176         kvm_for_each_vcpu(i, vcpu, kvm)
 177                 if (kvm_apic_present(vcpu))
 178                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 179
 180         new = kvm_kvzalloc(sizeof(struct kvm_apic_map) +
 181                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1));
 182
 183         if (!new)
 184                 goto out;
 185
 186         new->max_apic_id = max_id;
 187
 188         kvm_for_each_vcpu(i, vcpu, kvm) {
 189                 struct kvm_lapic *apic = vcpu->arch.apic;
 190                 struct kvm_lapic **cluster;
 191                 u16 mask;
 192                 u32 ldr;
 193                 u8 xapic_id;
 194                 u32 x2apic_id;
 195
 196                 if (!kvm_apic_present(vcpu))
 197                         continue;
 198
 199                 xapic_id = kvm_xapic_id(apic);
 200                 x2apic_id = kvm_x2apic_id(apic);
 201
 202                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 203                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 204                                 x2apic_id <= new->max_apic_id)
 205                         new->phys_map[x2apic_id] = apic;
 206                 /*
 207                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 208                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 209                  */
 210                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 211                         new->phys_map[xapic_id] = apic;
 212
 213                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 214
 215                 if (apic_x2apic_mode(apic)) {
 216                         new->mode |= KVM_APIC_MODE_X2APIC;
 217                 } else if (ldr) {
 218                         ldr = GET_APIC_LOGICAL_ID(ldr);
 219                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 220                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 221                         else
 222                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 223                 }
 224
 225                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 226                         continue;
 227
 228                 if (mask)
 229                         cluster[ffs(mask) - 1] = apic;
 230         }
 231 out:
 232         old = rcu_dereference_protected(kvm->arch.apic_map,
 233                         lockdep_is_held(&kvm->arch.apic_map_lock));
 234         rcu_assign_pointer(kvm->arch.apic_map, new);
 235         mutex_unlock(&kvm->arch.apic_map_lock);
 236
 237         if (old)
 238                 call_rcu(&old->rcu, kvm_apic_map_free);
 239
 240         kvm_make_scan_ioapic_request(kvm);
 241 }
 242
 243 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 244 {
 245         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 246
 247         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 248
 249         if (enabled != apic->sw_enabled) {
 250                 apic->sw_enabled = enabled;
 251                 if (enabled) {
 252                         static_key_slow_dec_deferred(&apic_sw_disabled);
 253                         recalculate_apic_map(apic->vcpu->kvm);
 254                 } else
 255                         static_key_slow_inc(&apic_sw_disabled.key);
 256         }
 257 }
 258
 259 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 260 {
 261         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 262         recalculate_apic_map(apic->vcpu->kvm);
 263 }
 264
 265 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 266 {
 267         kvm_lapic_set_reg(apic, APIC_LDR, id);
 268         recalculate_apic_map(apic->vcpu->kvm);
 269 }
 270
 271 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 272 {
 273         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
 274
 275         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 276
 277         kvm_lapic_set_reg(apic, APIC_ID, id);
 278         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 279         recalculate_apic_map(apic->vcpu->kvm);
 280 }
 281
 282 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 283 {
 284         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 285 }
 286
 287 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 288 {
 289         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 290 }
 291
 292 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 293 {
 294         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 295 }
 296
 297 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 298 {
 299         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 300 }
 301
 302 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 303 {
 304         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 305 }
 306
 307 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 308 {
 309         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 310 }
 311
 312 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 313 {
 314         struct kvm_lapic *apic = vcpu->arch.apic;
 315         struct kvm_cpuid_entry2 *feat;
 316         u32 v = APIC_VERSION;
 317
 318         if (!lapic_in_kernel(vcpu))
 319                 return;
 320
 321         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 322         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 323                 v |= APIC_LVR_DIRECTED_EOI;
 324         kvm_lapic_set_reg(apic, APIC_LVR, v);
 325 }
 326
 327 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 328         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 329         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 330         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 331         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 332         LVT_MASK                /* LVTERR */
 333 };
 334
 335 static int find_highest_vector(void *bitmap)
 336 {
 337         int vec;
 338         u32 *reg;
 339
 340         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 341              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 342                 reg = bitmap + REG_POS(vec);
 343                 if (*reg)
 344                         return fls(*reg) - 1 + vec;
 345         }
 346
 347         return -1;
 348 }
 349
 350 static u8 count_vectors(void *bitmap)
 351 {
 352         int vec;
 353         u32 *reg;
 354         u8 count = 0;
 355
 356         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 357                 reg = bitmap + REG_POS(vec);
 358                 count += hweight32(*reg);
 359         }
 360
 361         return count;
 362 }
 363
 364 void __kvm_apic_update_irr(u32 *pir, void *regs)
 365 {
 366         u32 i, pir_val;
 367
 368         for (i = 0; i <= 7; i++) {
 369                 pir_val = READ_ONCE(pir[i]);
 370                 if (pir_val) {
 371                         pir_val = xchg(&pir[i], 0);
 372                         *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
 373                 }
 374         }
 375 }
 376 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 377
 378 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 379 {
 380         struct kvm_lapic *apic = vcpu->arch.apic;
 381
 382         __kvm_apic_update_irr(pir, apic->regs);
 383
 384         kvm_make_request(KVM_REQ_EVENT, vcpu);
 385 }
 386 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 387
 388 static inline int apic_search_irr(struct kvm_lapic *apic)
 389 {
 390         return find_highest_vector(apic->regs + APIC_IRR);
 391 }
 392
 393 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 394 {
 395         int result;
 396
 397         /*
 398          * Note that irr_pending is just a hint. It will be always
 399          * true with virtual interrupt delivery enabled.
 400          */
 401         if (!apic->irr_pending)
 402                 return -1;
 403
 404         if (apic->vcpu->arch.apicv_active)
 405                 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 406         result = apic_search_irr(apic);
 407         ASSERT(result == -1 || result >= 16);
 408
 409         return result;
 410 }
 411
 412 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 413 {
 414         struct kvm_vcpu *vcpu;
 415
 416         vcpu = apic->vcpu;
 417
 418         if (unlikely(vcpu->arch.apicv_active)) {
 419                 /* try to update RVI */
 420                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 421                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 422         } else {
 423                 apic->irr_pending = false;
 424                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 425                 if (apic_search_irr(apic) != -1)
 426                         apic->irr_pending = true;
 427         }
 428 }
 429
 430 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 431 {
 432         struct kvm_vcpu *vcpu;
 433
 434         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 435                 return;
 436
 437         vcpu = apic->vcpu;
 438
 439         /*
 440          * With APIC virtualization enabled, all caching is disabled
 441          * because the processor can modify ISR under the hood.  Instead
 442          * just set SVI.
 443          */
 444         if (unlikely(vcpu->arch.apicv_active))
 445                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 446         else {
 447                 ++apic->isr_count;
 448                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 449                 /*
 450                  * ISR (in service register) bit is set when injecting an interrupt.
 451                  * The highest vector is injected. Thus the latest bit set matches
 452                  * the highest bit in ISR.
 453                  */
 454                 apic->highest_isr_cache = vec;
 455         }
 456 }
 457
 458 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 459 {
 460         int result;
 461
 462         /*
 463          * Note that isr_count is always 1, and highest_isr_cache
 464          * is always -1, with APIC virtualization enabled.
 465          */
 466         if (!apic->isr_count)
 467                 return -1;
 468         if (likely(apic->highest_isr_cache != -1))
 469                 return apic->highest_isr_cache;
 470
 471         result = find_highest_vector(apic->regs + APIC_ISR);
 472         ASSERT(result == -1 || result >= 16);
 473
 474         return result;
 475 }
 476
 477 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 478 {
 479         struct kvm_vcpu *vcpu;
 480         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 481                 return;
 482
 483         vcpu = apic->vcpu;
 484
 485         /*
 486          * We do get here for APIC virtualization enabled if the guest
 487          * uses the Hyper-V APIC enlightenment.  In this case we may need
 488          * to trigger a new interrupt delivery by writing the SVI field;
 489          * on the other hand isr_count and highest_isr_cache are unused
 490          * and must be left alone.
 491          */
 492         if (unlikely(vcpu->arch.apicv_active))
 493                 kvm_x86_ops->hwapic_isr_update(vcpu,
 494                                                apic_find_highest_isr(apic));
 495         else {
 496                 --apic->isr_count;
 497                 BUG_ON(apic->isr_count < 0);
 498                 apic->highest_isr_cache = -1;
 499         }
 500 }
 501
 502 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 503 {
 504         /* This may race with setting of irr in __apic_accept_irq() and
 505          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 506          * will cause vmexit immediately and the value will be recalculated
 507          * on the next vmentry.
 508          */
 509         return apic_find_highest_irr(vcpu->arch.apic);
 510 }
 511
 512 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 513                              int vector, int level, int trig_mode,
 514                              struct dest_map *dest_map);
 515
 516 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 517                      struct dest_map *dest_map)
 518 {
 519         struct kvm_lapic *apic = vcpu->arch.apic;
 520
 521         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 522                         irq->level, irq->trig_mode, dest_map);
 523 }
 524
 525 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 526 {
 527
 528         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 529                                       sizeof(val));
 530 }
 531
 532 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 533 {
 534
 535         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 536                                       sizeof(*val));
 537 }
 538
 539 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 540 {
 541         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 542 }
 543
 544 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 545 {
 546         u8 val;
 547         if (pv_eoi_get_user(vcpu, &val) < 0)
 548                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 549                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 550         return val & 0x1;
 551 }
 552
 553 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 554 {
 555         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 556                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 557                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 558                 return;
 559         }
 560         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 561 }
 562
 563 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 564 {
 565         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 566                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 567                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 568                 return;
 569         }
 570         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 571 }
 572
 573 static void apic_update_ppr(struct kvm_lapic *apic)
 574 {
 575         u32 tpr, isrv, ppr, old_ppr;
 576         int isr;
 577
 578         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 579         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 580         isr = apic_find_highest_isr(apic);
 581         isrv = (isr != -1) ? isr : 0;
 582
 583         if ((tpr & 0xf0) >= (isrv & 0xf0))
 584                 ppr = tpr & 0xff;
 585         else
 586                 ppr = isrv & 0xf0;
 587
 588         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 589                    apic, ppr, isr, isrv);
 590
 591         if (old_ppr != ppr) {
 592                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 593                 if (ppr < old_ppr)
 594                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 595         }
 596 }
 597
 598 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 599 {
 600         apic_update_ppr(vcpu->arch.apic);
 601 }
 602 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 603
 604 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 605 {
 606         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 607         apic_update_ppr(apic);
 608 }
 609
 610 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 611 {
 612         return mda == (apic_x2apic_mode(apic) ?
 613                         X2APIC_BROADCAST : APIC_BROADCAST);
 614 }
 615
 616 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 617 {
 618         if (kvm_apic_broadcast(apic, mda))
 619                 return true;
 620
 621         if (apic_x2apic_mode(apic))
 622                 return mda == kvm_x2apic_id(apic);
 623
 624         /*
 625          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 626          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 627          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 628          * The 0xff condition is needed because writeable xAPIC ID.
 629          */
 630         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 631                 return true;
 632
 633         return mda == kvm_xapic_id(apic);
 634 }
 635
 636 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 637 {
 638         u32 logical_id;
 639
 640         if (kvm_apic_broadcast(apic, mda))
 641                 return true;
 642
 643         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 644
 645         if (apic_x2apic_mode(apic))
 646                 return ((logical_id >> 16) == (mda >> 16))
 647                        && (logical_id & mda & 0xffff) != 0;
 648
 649         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 650
 651         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 652         case APIC_DFR_FLAT:
 653                 return (logical_id & mda) != 0;
 654         case APIC_DFR_CLUSTER:
 655                 return ((logical_id >> 4) == (mda >> 4))
 656                        && (logical_id & mda & 0xf) != 0;
 657         default:
 658                 apic_debug("Bad DFR vcpu %d: %08x\n",
 659                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 660                 return false;
 661         }
 662 }
 663
 664 /* The KVM local APIC implementation has two quirks:
 665  *
 666  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 667  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 668  *    KVM doesn't do that aliasing.
 669  *
 670  *  - in-kernel IOAPIC messages have to be delivered directly to
 671  *    x2APIC, because the kernel does not support interrupt remapping.
 672  *    In order to support broadcast without interrupt remapping, x2APIC
 673  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 674  *    to X2APIC_BROADCAST.
 675  *
 676  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 677  * important when userspace wants to use x2APIC-format MSIs, because
 678  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 679  */
 680 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 681                 struct kvm_lapic *source, struct kvm_lapic *target)
 682 {
 683         bool ipi = source != NULL;
 684
 685         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 686             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 687                 return X2APIC_BROADCAST;
 688
 689         return dest_id;
 690 }
 691
 692 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 693                            int short_hand, unsigned int dest, int dest_mode)
 694 {
 695         struct kvm_lapic *target = vcpu->arch.apic;
 696         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 697
 698         apic_debug("target %p, source %p, dest 0x%x, "
 699                    "dest_mode 0x%x, short_hand 0x%x\n",
 700                    target, source, dest, dest_mode, short_hand);
 701
 702         ASSERT(target);
 703         switch (short_hand) {
 704         case APIC_DEST_NOSHORT:
 705                 if (dest_mode == APIC_DEST_PHYSICAL)
 706                         return kvm_apic_match_physical_addr(target, mda);
 707                 else
 708                         return kvm_apic_match_logical_addr(target, mda);
 709         case APIC_DEST_SELF:
 710                 return target == source;
 711         case APIC_DEST_ALLINC:
 712                 return true;
 713         case APIC_DEST_ALLBUT:
 714                 return target != source;
 715         default:
 716                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 717                            short_hand);
 718                 return false;
 719         }
 720 }
 721 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 722
 723 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 724                        const unsigned long *bitmap, u32 bitmap_size)
 725 {
 726         u32 mod;
 727         int i, idx = -1;
 728
 729         mod = vector % dest_vcpus;
 730
 731         for (i = 0; i <= mod; i++) {
 732                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 733                 BUG_ON(idx == bitmap_size);
 734         }
 735
 736         return idx;
 737 }
 738
 739 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 740 {
 741         if (!kvm->arch.disabled_lapic_found) {
 742                 kvm->arch.disabled_lapic_found = true;
 743                 printk(KERN_INFO
 744                        "Disabled LAPIC found during irq injection\n");
 745         }
 746 }
 747
 748 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 749                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 750 {
 751         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 752                 if ((irq->dest_id == APIC_BROADCAST &&
 753                                 map->mode != KVM_APIC_MODE_X2APIC))
 754                         return true;
 755                 if (irq->dest_id == X2APIC_BROADCAST)
 756                         return true;
 757         } else {
 758                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 759                 if (irq->dest_id == (x2apic_ipi ?
 760                                      X2APIC_BROADCAST : APIC_BROADCAST))
 761                         return true;
 762         }
 763
 764         return false;
 765 }
 766
 767 /* Return true if the interrupt can be handled by using *bitmap as index mask
 768  * for valid destinations in *dst array.
 769  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 770  * Note: we may have zero kvm_lapic destinations when we return true, which
 771  * means that the interrupt should be dropped.  In this case, *bitmap would be
 772  * zero and *dst undefined.
 773  */
 774 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 775                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 776                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 777                 unsigned long *bitmap)
 778 {
 779         int i, lowest;
 780
 781         if (irq->shorthand == APIC_DEST_SELF && src) {
 782                 *dst = src;
 783                 *bitmap = 1;
 784                 return true;
 785         } else if (irq->shorthand)
 786                 return false;
 787
 788         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 789                 return false;
 790
 791         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 792                 if (irq->dest_id > map->max_apic_id) {
 793                         *bitmap = 0;
 794                 } else {
 795                         *dst = &map->phys_map[irq->dest_id];
 796                         *bitmap = 1;
 797                 }
 798                 return true;
 799         }
 800
 801         *bitmap = 0;
 802         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 803                                 (u16 *)bitmap))
 804                 return false;
 805
 806         if (!kvm_lowest_prio_delivery(irq))
 807                 return true;
 808
 809         if (!kvm_vector_hashing_enabled()) {
 810                 lowest = -1;
 811                 for_each_set_bit(i, bitmap, 16) {
 812                         if (!(*dst)[i])
 813                                 continue;
 814                         if (lowest < 0)
 815                                 lowest = i;
 816                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 817                                                 (*dst)[lowest]->vcpu) < 0)
 818                                 lowest = i;
 819                 }
 820         } else {
 821                 if (!*bitmap)
 822                         return true;
 823
 824                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 825                                 bitmap, 16);
 826
 827                 if (!(*dst)[lowest]) {
 828                         kvm_apic_disabled_lapic_found(kvm);
 829                         *bitmap = 0;
 830                         return true;
 831                 }
 832         }
 833
 834         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 835
 836         return true;
 837 }
 838
 839 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 840                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 841 {
 842         struct kvm_apic_map *map;
 843         unsigned long bitmap;
 844         struct kvm_lapic **dst = NULL;
 845         int i;
 846         bool ret;
 847
 848         *r = -1;
 849
 850         if (irq->shorthand == APIC_DEST_SELF) {
 851                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 852                 return true;
 853         }
 854
 855         rcu_read_lock();
 856         map = rcu_dereference(kvm->arch.apic_map);
 857
 858         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 859         if (ret)
 860                 for_each_set_bit(i, &bitmap, 16) {
 861                         if (!dst[i])
 862                                 continue;
 863                         if (*r < 0)
 864                                 *r = 0;
 865                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 866                 }
 867
 868         rcu_read_unlock();
 869         return ret;
 870 }
 871
 872 /*
 873  * This routine tries to handler interrupts in posted mode, here is how
 874  * it deals with different cases:
 875  * - For single-destination interrupts, handle it in posted mode
 876  * - Else if vector hashing is enabled and it is a lowest-priority
 877  *   interrupt, handle it in posted mode and use the following mechanism
 878  *   to find the destinaiton vCPU.
 879  *      1. For lowest-priority interrupts, store all the possible
 880  *         destination vCPUs in an array.
 881  *      2. Use "guest vector % max number of destination vCPUs" to find
 882  *         the right destination vCPU in the array for the lowest-priority
 883  *         interrupt.
 884  * - Otherwise, use remapped mode to inject the interrupt.
 885  */
 886 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 887                         struct kvm_vcpu **dest_vcpu)
 888 {
 889         struct kvm_apic_map *map;
 890         unsigned long bitmap;
 891         struct kvm_lapic **dst = NULL;
 892         bool ret = false;
 893
 894         if (irq->shorthand)
 895                 return false;
 896
 897         rcu_read_lock();
 898         map = rcu_dereference(kvm->arch.apic_map);
 899
 900         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
 901                         hweight16(bitmap) == 1) {
 902                 unsigned long i = find_first_bit(&bitmap, 16);
 903
 904                 if (dst[i]) {
 905                         *dest_vcpu = dst[i]->vcpu;
 906                         ret = true;
 907                 }
 908         }
 909
 910         rcu_read_unlock();
 911         return ret;
 912 }
 913
 914 /*
 915  * Add a pending IRQ into lapic.
 916  * Return 1 if successfully added and 0 if discarded.
 917  */
 918 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 919                              int vector, int level, int trig_mode,
 920                              struct dest_map *dest_map)
 921 {
 922         int result = 0;
 923         struct kvm_vcpu *vcpu = apic->vcpu;
 924
 925         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 926                                   trig_mode, vector);
 927         switch (delivery_mode) {
 928         case APIC_DM_LOWEST:
 929                 vcpu->arch.apic_arb_prio++;
 930         case APIC_DM_FIXED:
 931                 if (unlikely(trig_mode && !level))
 932                         break;
 933
 934                 /* FIXME add logic for vcpu on reset */
 935                 if (unlikely(!apic_enabled(apic)))
 936                         break;
 937
 938                 result = 1;
 939
 940                 if (dest_map) {
 941                         __set_bit(vcpu->vcpu_id, dest_map->map);
 942                         dest_map->vectors[vcpu->vcpu_id] = vector;
 943                 }
 944
 945                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
 946                         if (trig_mode)
 947                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
 948                         else
 949                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
 950                 }
 951
 952                 if (vcpu->arch.apicv_active)
 953                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 954                 else {
 955                         kvm_lapic_set_irr(vector, apic);
 956
 957                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 958                         kvm_vcpu_kick(vcpu);
 959                 }
 960                 break;
 961
 962         case APIC_DM_REMRD:
 963                 result = 1;
 964                 vcpu->arch.pv.pv_unhalted = 1;
 965                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 966                 kvm_vcpu_kick(vcpu);
 967                 break;
 968
 969         case APIC_DM_SMI:
 970                 result = 1;
 971                 kvm_make_request(KVM_REQ_SMI, vcpu);
 972                 kvm_vcpu_kick(vcpu);
 973                 break;
 974
 975         case APIC_DM_NMI:
 976                 result = 1;
 977                 kvm_inject_nmi(vcpu);
 978                 kvm_vcpu_kick(vcpu);
 979                 break;
 980
 981         case APIC_DM_INIT:
 982                 if (!trig_mode || level) {
 983                         result = 1;
 984                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 985                         apic->pending_events = (1UL << KVM_APIC_INIT);
 986                         /* make sure pending_events is visible before sending
 987                          * the request */
 988                         smp_wmb();
 989                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 990                         kvm_vcpu_kick(vcpu);
 991                 } else {
 992                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 993                                    vcpu->vcpu_id);
 994                 }
 995                 break;
 996
 997         case APIC_DM_STARTUP:
 998                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 999                            vcpu->vcpu_id, vector);
1000                 result = 1;
1001                 apic->sipi_vector = vector;
1002                 /* make sure sipi_vector is visible for the receiver */
1003                 smp_wmb();
1004                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1005                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1006                 kvm_vcpu_kick(vcpu);
1007                 break;
1008
1009         case APIC_DM_EXTINT:
1010                 /*
1011                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1012                  * before NMI watchdog was enabled. Already handled by
1013                  * kvm_apic_accept_pic_intr().
1014                  */
1015                 break;
1016
1017         default:
1018                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1019                        delivery_mode);
1020                 break;
1021         }
1022         return result;
1023 }
1024
1025 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1026 {
1027         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1028 }
1029
1030 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1031 {
1032         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1033 }
1034
1035 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1036 {
1037         int trigger_mode;
1038
1039         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1040         if (!kvm_ioapic_handles_vector(apic, vector))
1041                 return;
1042
1043         /* Request a KVM exit to inform the userspace IOAPIC. */
1044         if (irqchip_split(apic->vcpu->kvm)) {
1045                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1046                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1047                 return;
1048         }
1049
1050         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1051                 trigger_mode = IOAPIC_LEVEL_TRIG;
1052         else
1053                 trigger_mode = IOAPIC_EDGE_TRIG;
1054
1055         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1056 }
1057
1058 static int apic_set_eoi(struct kvm_lapic *apic)
1059 {
1060         int vector = apic_find_highest_isr(apic);
1061
1062         trace_kvm_eoi(apic, vector);
1063
1064         /*
1065          * Not every write EOI will has corresponding ISR,
1066          * one example is when Kernel check timer on setup_IO_APIC
1067          */
1068         if (vector == -1)
1069                 return vector;
1070
1071         apic_clear_isr(vector, apic);
1072         apic_update_ppr(apic);
1073
1074         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1075                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1076
1077         kvm_ioapic_send_eoi(apic, vector);
1078         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1079         return vector;
1080 }
1081
1082 /*
1083  * this interface assumes a trap-like exit, which has already finished
1084  * desired side effect including vISR and vPPR update.
1085  */
1086 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1087 {
1088         struct kvm_lapic *apic = vcpu->arch.apic;
1089
1090         trace_kvm_eoi(apic, vector);
1091
1092         kvm_ioapic_send_eoi(apic, vector);
1093         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1094 }
1095 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1096
1097 static void apic_send_ipi(struct kvm_lapic *apic)
1098 {
1099         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1100         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1101         struct kvm_lapic_irq irq;
1102
1103         irq.vector = icr_low & APIC_VECTOR_MASK;
1104         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1105         irq.dest_mode = icr_low & APIC_DEST_MASK;
1106         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1107         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1108         irq.shorthand = icr_low & APIC_SHORT_MASK;
1109         irq.msi_redir_hint = false;
1110         if (apic_x2apic_mode(apic))
1111                 irq.dest_id = icr_high;
1112         else
1113                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1114
1115         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1116
1117         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1118                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1119                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1120                    "msi_redir_hint 0x%x\n",
1121                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1122                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1123                    irq.vector, irq.msi_redir_hint);
1124
1125         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1126 }
1127
1128 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1129 {
1130         ktime_t remaining, now;
1131         s64 ns;
1132         u32 tmcct;
1133
1134         ASSERT(apic != NULL);
1135
1136         /* if initial count is 0, current count should also be 0 */
1137         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1138                 apic->lapic_timer.period == 0)
1139                 return 0;
1140
1141         now = ktime_get();
1142         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1143         if (ktime_to_ns(remaining) < 0)
1144                 remaining = 0;
1145
1146         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1147         tmcct = div64_u64(ns,
1148                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1149
1150         return tmcct;
1151 }
1152
1153 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1154 {
1155         struct kvm_vcpu *vcpu = apic->vcpu;
1156         struct kvm_run *run = vcpu->run;
1157
1158         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1159         run->tpr_access.rip = kvm_rip_read(vcpu);
1160         run->tpr_access.is_write = write;
1161 }
1162
1163 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1164 {
1165         if (apic->vcpu->arch.tpr_access_reporting)
1166                 __report_tpr_access(apic, write);
1167 }
1168
1169 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1170 {
1171         u32 val = 0;
1172
1173         if (offset >= LAPIC_MMIO_LENGTH)
1174                 return 0;
1175
1176         switch (offset) {
1177         case APIC_ARBPRI:
1178                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1179                 break;
1180
1181         case APIC_TMCCT:        /* Timer CCR */
1182                 if (apic_lvtt_tscdeadline(apic))
1183                         return 0;
1184
1185                 val = apic_get_tmcct(apic);
1186                 break;
1187         case APIC_PROCPRI:
1188                 apic_update_ppr(apic);
1189                 val = kvm_lapic_get_reg(apic, offset);
1190                 break;
1191         case APIC_TASKPRI:
1192                 report_tpr_access(apic, false);
1193                 /* fall thru */
1194         default:
1195                 val = kvm_lapic_get_reg(apic, offset);
1196                 break;
1197         }
1198
1199         return val;
1200 }
1201
1202 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1203 {
1204         return container_of(dev, struct kvm_lapic, dev);
1205 }
1206
1207 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1208                 void *data)
1209 {
1210         unsigned char alignment = offset & 0xf;
1211         u32 result;
1212         /* this bitmask has a bit cleared for each reserved register */
1213         static const u64 rmask = 0x43ff01ffffffe70cULL;
1214
1215         if ((alignment + len) > 4) {
1216                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1217                            offset, len);
1218                 return 1;
1219         }
1220
1221         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1222                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1223                            offset);
1224                 return 1;
1225         }
1226
1227         result = __apic_read(apic, offset & ~0xf);
1228
1229         trace_kvm_apic_read(offset, result);
1230
1231         switch (len) {
1232         case 1:
1233         case 2:
1234         case 4:
1235                 memcpy(data, (char *)&result + alignment, len);
1236                 break;
1237         default:
1238                 printk(KERN_ERR "Local APIC read with len = %x, "
1239                        "should be 1,2, or 4 instead\n", len);
1240                 break;
1241         }
1242         return 0;
1243 }
1244 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1245
1246 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1247 {
1248         return kvm_apic_hw_enabled(apic) &&
1249             addr >= apic->base_address &&
1250             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1251 }
1252
1253 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1254                            gpa_t address, int len, void *data)
1255 {
1256         struct kvm_lapic *apic = to_lapic(this);
1257         u32 offset = address - apic->base_address;
1258
1259         if (!apic_mmio_in_range(apic, address))
1260                 return -EOPNOTSUPP;
1261
1262         kvm_lapic_reg_read(apic, offset, len, data);
1263
1264         return 0;
1265 }
1266
1267 static void update_divide_count(struct kvm_lapic *apic)
1268 {
1269         u32 tmp1, tmp2, tdcr;
1270
1271         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1272         tmp1 = tdcr & 0xf;
1273         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1274         apic->divide_count = 0x1 << (tmp2 & 0x7);
1275
1276         apic_debug("timer divide count is 0x%x\n",
1277                                    apic->divide_count);
1278 }
1279
1280 static void apic_update_lvtt(struct kvm_lapic *apic)
1281 {
1282         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1283                         apic->lapic_timer.timer_mode_mask;
1284
1285         if (apic->lapic_timer.timer_mode != timer_mode) {
1286                 apic->lapic_timer.timer_mode = timer_mode;
1287                 hrtimer_cancel(&apic->lapic_timer.timer);
1288         }
1289 }
1290
1291 static void apic_timer_expired(struct kvm_lapic *apic)
1292 {
1293         struct kvm_vcpu *vcpu = apic->vcpu;
1294         struct swait_queue_head *q = &vcpu->wq;
1295         struct kvm_timer *ktimer = &apic->lapic_timer;
1296
1297         if (atomic_read(&apic->lapic_timer.pending))
1298                 return;
1299
1300         atomic_inc(&apic->lapic_timer.pending);
1301         kvm_set_pending_timer(vcpu);
1302
1303         if (swait_active(q))
1304                 swake_up(q);
1305
1306         if (apic_lvtt_tscdeadline(apic))
1307                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1308 }
1309
1310 /*
1311  * On APICv, this test will cause a busy wait
1312  * during a higher-priority task.
1313  */
1314
1315 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1316 {
1317         struct kvm_lapic *apic = vcpu->arch.apic;
1318         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1319
1320         if (kvm_apic_hw_enabled(apic)) {
1321                 int vec = reg & APIC_VECTOR_MASK;
1322                 void *bitmap = apic->regs + APIC_ISR;
1323
1324                 if (vcpu->arch.apicv_active)
1325                         bitmap = apic->regs + APIC_IRR;
1326
1327                 if (apic_test_vector(vec, bitmap))
1328                         return true;
1329         }
1330         return false;
1331 }
1332
1333 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1334 {
1335         struct kvm_lapic *apic = vcpu->arch.apic;
1336         u64 guest_tsc, tsc_deadline;
1337
1338         if (!lapic_in_kernel(vcpu))
1339                 return;
1340
1341         if (apic->lapic_timer.expired_tscdeadline == 0)
1342                 return;
1343
1344         if (!lapic_timer_int_injected(vcpu))
1345                 return;
1346
1347         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1348         apic->lapic_timer.expired_tscdeadline = 0;
1349         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1350         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1351
1352         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1353         if (guest_tsc < tsc_deadline)
1354                 __delay(min(tsc_deadline - guest_tsc,
1355                         nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1356 }
1357
1358 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1359 {
1360         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1361         u64 ns = 0;
1362         ktime_t expire;
1363         struct kvm_vcpu *vcpu = apic->vcpu;
1364         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1365         unsigned long flags;
1366         ktime_t now;
1367
1368         if (unlikely(!tscdeadline || !this_tsc_khz))
1369                 return;
1370
1371         local_irq_save(flags);
1372
1373         now = ktime_get();
1374         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1375         if (likely(tscdeadline > guest_tsc)) {
1376                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1377                 do_div(ns, this_tsc_khz);
1378                 expire = ktime_add_ns(now, ns);
1379                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1380                 hrtimer_start(&apic->lapic_timer.timer,
1381                                 expire, HRTIMER_MODE_ABS_PINNED);
1382         } else
1383                 apic_timer_expired(apic);
1384
1385         local_irq_restore(flags);
1386 }
1387
1388 static void start_sw_period(struct kvm_lapic *apic)
1389 {
1390         if (!apic->lapic_timer.period)
1391                 return;
1392
1393         if (apic_lvtt_oneshot(apic) &&
1394             ktime_after(ktime_get(),
1395                         apic->lapic_timer.target_expiration)) {
1396                 apic_timer_expired(apic);
1397                 return;
1398         }
1399
1400         hrtimer_start(&apic->lapic_timer.timer,
1401                 apic->lapic_timer.target_expiration,
1402                 HRTIMER_MODE_ABS_PINNED);
1403 }
1404
1405 static bool set_target_expiration(struct kvm_lapic *apic)
1406 {
1407         ktime_t now;
1408         u64 tscl = rdtsc();
1409
1410         now = ktime_get();
1411         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1412                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1413
1414         if (!apic->lapic_timer.period)
1415                 return false;
1416
1417         /*
1418          * Do not allow the guest to program periodic timers with small
1419          * interval, since the hrtimers are not throttled by the host
1420          * scheduler.
1421          */
1422         if (apic_lvtt_period(apic)) {
1423                 s64 min_period = min_timer_period_us * 1000LL;
1424
1425                 if (apic->lapic_timer.period < min_period) {
1426                         pr_info_ratelimited(
1427                             "kvm: vcpu %i: requested %lld ns "
1428                             "lapic timer period limited to %lld ns\n",
1429                             apic->vcpu->vcpu_id,
1430                             apic->lapic_timer.period, min_period);
1431                         apic->lapic_timer.period = min_period;
1432                 }
1433         }
1434
1435         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1436                    PRIx64 ", "
1437                    "timer initial count 0x%x, period %lldns, "
1438                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1439                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1440                    kvm_lapic_get_reg(apic, APIC_TMICT),
1441                    apic->lapic_timer.period,
1442                    ktime_to_ns(ktime_add_ns(now,
1443                                 apic->lapic_timer.period)));
1444
1445         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1446                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1447         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1448
1449         return true;
1450 }
1451
1452 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1453 {
1454         apic->lapic_timer.tscdeadline +=
1455                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1456         apic->lapic_timer.target_expiration =
1457                 ktime_add_ns(apic->lapic_timer.target_expiration,
1458                                 apic->lapic_timer.period);
1459 }
1460
1461 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1462 {
1463         if (!lapic_in_kernel(vcpu))
1464                 return false;
1465
1466         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1467 }
1468 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1469
1470 static void cancel_hv_timer(struct kvm_lapic *apic)
1471 {
1472         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1473         apic->lapic_timer.hv_timer_in_use = false;
1474 }
1475
1476 static bool start_hv_timer(struct kvm_lapic *apic)
1477 {
1478         u64 tscdeadline = apic->lapic_timer.tscdeadline;
1479
1480         if ((atomic_read(&apic->lapic_timer.pending) &&
1481                 !apic_lvtt_period(apic)) ||
1482                 kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) {
1483                 if (apic->lapic_timer.hv_timer_in_use)
1484                         cancel_hv_timer(apic);
1485         } else {
1486                 apic->lapic_timer.hv_timer_in_use = true;
1487                 hrtimer_cancel(&apic->lapic_timer.timer);
1488
1489                 /* In case the sw timer triggered in the window */
1490                 if (atomic_read(&apic->lapic_timer.pending) &&
1491                         !apic_lvtt_period(apic))
1492                         cancel_hv_timer(apic);
1493         }
1494         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id,
1495                         apic->lapic_timer.hv_timer_in_use);
1496         return apic->lapic_timer.hv_timer_in_use;
1497 }
1498
1499 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1500 {
1501         struct kvm_lapic *apic = vcpu->arch.apic;
1502
1503         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1504         WARN_ON(swait_active(&vcpu->wq));
1505         cancel_hv_timer(apic);
1506         apic_timer_expired(apic);
1507
1508         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1509                 advance_periodic_target_expiration(apic);
1510                 if (!start_hv_timer(apic))
1511                         start_sw_period(apic);
1512         }
1513 }
1514 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1515
1516 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1517 {
1518         struct kvm_lapic *apic = vcpu->arch.apic;
1519
1520         WARN_ON(apic->lapic_timer.hv_timer_in_use);
1521
1522         start_hv_timer(apic);
1523 }
1524 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1525
1526 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1527 {
1528         struct kvm_lapic *apic = vcpu->arch.apic;
1529
1530         /* Possibly the TSC deadline timer is not enabled yet */
1531         if (!apic->lapic_timer.hv_timer_in_use)
1532                 return;
1533
1534         cancel_hv_timer(apic);
1535
1536         if (atomic_read(&apic->lapic_timer.pending))
1537                 return;
1538
1539         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1540                 start_sw_period(apic);
1541         else if (apic_lvtt_tscdeadline(apic))
1542                 start_sw_tscdeadline(apic);
1543 }
1544 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1545
1546 static void start_apic_timer(struct kvm_lapic *apic)
1547 {
1548         atomic_set(&apic->lapic_timer.pending, 0);
1549
1550         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1551                 if (set_target_expiration(apic) &&
1552                         !(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1553                         start_sw_period(apic);
1554         } else if (apic_lvtt_tscdeadline(apic)) {
1555                 if (!(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1556                         start_sw_tscdeadline(apic);
1557         }
1558 }
1559
1560 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1561 {
1562         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1563
1564         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1565                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1566                 if (lvt0_in_nmi_mode) {
1567                         apic_debug("Receive NMI setting on APIC_LVT0 "
1568                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1569                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1570                 } else
1571                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1572         }
1573 }
1574
1575 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1576 {
1577         int ret = 0;
1578
1579         trace_kvm_apic_write(reg, val);
1580
1581         switch (reg) {
1582         case APIC_ID:           /* Local APIC ID */
1583                 if (!apic_x2apic_mode(apic))
1584                         kvm_apic_set_xapic_id(apic, val >> 24);
1585                 else
1586                         ret = 1;
1587                 break;
1588
1589         case APIC_TASKPRI:
1590                 report_tpr_access(apic, true);
1591                 apic_set_tpr(apic, val & 0xff);
1592                 break;
1593
1594         case APIC_EOI:
1595                 apic_set_eoi(apic);
1596                 break;
1597
1598         case APIC_LDR:
1599                 if (!apic_x2apic_mode(apic))
1600                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1601                 else
1602                         ret = 1;
1603                 break;
1604
1605         case APIC_DFR:
1606                 if (!apic_x2apic_mode(apic)) {
1607                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1608                         recalculate_apic_map(apic->vcpu->kvm);
1609                 } else
1610                         ret = 1;
1611                 break;
1612
1613         case APIC_SPIV: {
1614                 u32 mask = 0x3ff;
1615                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1616                         mask |= APIC_SPIV_DIRECTED_EOI;
1617                 apic_set_spiv(apic, val & mask);
1618                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1619                         int i;
1620                         u32 lvt_val;
1621
1622                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1623                                 lvt_val = kvm_lapic_get_reg(apic,
1624                                                        APIC_LVTT + 0x10 * i);
1625                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1626                                              lvt_val | APIC_LVT_MASKED);
1627                         }
1628                         apic_update_lvtt(apic);
1629                         atomic_set(&apic->lapic_timer.pending, 0);
1630
1631                 }
1632                 break;
1633         }
1634         case APIC_ICR:
1635                 /* No delay here, so we always clear the pending bit */
1636                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1637                 apic_send_ipi(apic);
1638                 break;
1639
1640         case APIC_ICR2:
1641                 if (!apic_x2apic_mode(apic))
1642                         val &= 0xff000000;
1643                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1644                 break;
1645
1646         case APIC_LVT0:
1647                 apic_manage_nmi_watchdog(apic, val);
1648         case APIC_LVTTHMR:
1649         case APIC_LVTPC:
1650         case APIC_LVT1:
1651         case APIC_LVTERR:
1652                 /* TODO: Check vector */
1653                 if (!kvm_apic_sw_enabled(apic))
1654                         val |= APIC_LVT_MASKED;
1655
1656                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1657                 kvm_lapic_set_reg(apic, reg, val);
1658
1659                 break;
1660
1661         case APIC_LVTT:
1662                 if (!kvm_apic_sw_enabled(apic))
1663                         val |= APIC_LVT_MASKED;
1664                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1665                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1666                 apic_update_lvtt(apic);
1667                 break;
1668
1669         case APIC_TMICT:
1670                 if (apic_lvtt_tscdeadline(apic))
1671                         break;
1672
1673                 hrtimer_cancel(&apic->lapic_timer.timer);
1674                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1675                 start_apic_timer(apic);
1676                 break;
1677
1678         case APIC_TDCR:
1679                 if (val & 4)
1680                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1681                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1682                 update_divide_count(apic);
1683                 break;
1684
1685         case APIC_ESR:
1686                 if (apic_x2apic_mode(apic) && val != 0) {
1687                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1688                         ret = 1;
1689                 }
1690                 break;
1691
1692         case APIC_SELF_IPI:
1693                 if (apic_x2apic_mode(apic)) {
1694                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1695                 } else
1696                         ret = 1;
1697                 break;
1698         default:
1699                 ret = 1;
1700                 break;
1701         }
1702         if (ret)
1703                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1704         return ret;
1705 }
1706 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1707
1708 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1709                             gpa_t address, int len, const void *data)
1710 {
1711         struct kvm_lapic *apic = to_lapic(this);
1712         unsigned int offset = address - apic->base_address;
1713         u32 val;
1714
1715         if (!apic_mmio_in_range(apic, address))
1716                 return -EOPNOTSUPP;
1717
1718         /*
1719          * APIC register must be aligned on 128-bits boundary.
1720          * 32/64/128 bits registers must be accessed thru 32 bits.
1721          * Refer SDM 8.4.1
1722          */
1723         if (len != 4 || (offset & 0xf)) {
1724                 /* Don't shout loud, $infamous_os would cause only noise. */
1725                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1726                 return 0;
1727         }
1728
1729         val = *(u32*)data;
1730
1731         /* too common printing */
1732         if (offset != APIC_EOI)
1733                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1734                            "0x%x\n", __func__, offset, len, val);
1735
1736         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1737
1738         return 0;
1739 }
1740
1741 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1742 {
1743         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1744 }
1745 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1746
1747 /* emulate APIC access in a trap manner */
1748 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1749 {
1750         u32 val = 0;
1751
1752         /* hw has done the conditional check and inst decode */
1753         offset &= 0xff0;
1754
1755         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1756
1757         /* TODO: optimize to just emulate side effect w/o one more write */
1758         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1759 }
1760 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1761
1762 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1763 {
1764         struct kvm_lapic *apic = vcpu->arch.apic;
1765
1766         if (!vcpu->arch.apic)
1767                 return;
1768
1769         hrtimer_cancel(&apic->lapic_timer.timer);
1770
1771         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1772                 static_key_slow_dec_deferred(&apic_hw_disabled);
1773
1774         if (!apic->sw_enabled)
1775                 static_key_slow_dec_deferred(&apic_sw_disabled);
1776
1777         if (apic->regs)
1778                 free_page((unsigned long)apic->regs);
1779
1780         kfree(apic);
1781 }
1782
1783 /*
1784  *----------------------------------------------------------------------
1785  * LAPIC interface
1786  *----------------------------------------------------------------------
1787  */
1788 u64 kvm_get_lapic_target_expiration_tsc(struct kvm_vcpu *vcpu)
1789 {
1790         struct kvm_lapic *apic = vcpu->arch.apic;
1791
1792         if (!lapic_in_kernel(vcpu))
1793                 return 0;
1794
1795         return apic->lapic_timer.tscdeadline;
1796 }
1797
1798 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1799 {
1800         struct kvm_lapic *apic = vcpu->arch.apic;
1801
1802         if (!lapic_in_kernel(vcpu) ||
1803                 !apic_lvtt_tscdeadline(apic))
1804                 return 0;
1805
1806         return apic->lapic_timer.tscdeadline;
1807 }
1808
1809 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1810 {
1811         struct kvm_lapic *apic = vcpu->arch.apic;
1812
1813         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1814                         apic_lvtt_period(apic))
1815                 return;
1816
1817         hrtimer_cancel(&apic->lapic_timer.timer);
1818         apic->lapic_timer.tscdeadline = data;
1819         start_apic_timer(apic);
1820 }
1821
1822 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1823 {
1824         struct kvm_lapic *apic = vcpu->arch.apic;
1825
1826         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1827                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1828 }
1829
1830 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1831 {
1832         u64 tpr;
1833
1834         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1835
1836         return (tpr & 0xf0) >> 4;
1837 }
1838
1839 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1840 {
1841         u64 old_value = vcpu->arch.apic_base;
1842         struct kvm_lapic *apic = vcpu->arch.apic;
1843
1844         if (!apic)
1845                 value |= MSR_IA32_APICBASE_BSP;
1846
1847         vcpu->arch.apic_base = value;
1848
1849         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1850                 kvm_update_cpuid(vcpu);
1851
1852         if (!apic)
1853                 return;
1854
1855         /* update jump label if enable bit changes */
1856         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1857                 if (value & MSR_IA32_APICBASE_ENABLE) {
1858                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1859                         static_key_slow_dec_deferred(&apic_hw_disabled);
1860                 } else {
1861                         static_key_slow_inc(&apic_hw_disabled.key);
1862                         recalculate_apic_map(vcpu->kvm);
1863                 }
1864         }
1865
1866         if ((old_value ^ value) & X2APIC_ENABLE) {
1867                 if (value & X2APIC_ENABLE) {
1868                         kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1869                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1870                 } else
1871                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1872         }
1873
1874         apic->base_address = apic->vcpu->arch.apic_base &
1875                              MSR_IA32_APICBASE_BASE;
1876
1877         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1878              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1879                 pr_warn_once("APIC base relocation is unsupported by KVM");
1880
1881         /* with FSB delivery interrupt, we can restart APIC functionality */
1882         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1883                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1884
1885 }
1886
1887 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1888 {
1889         struct kvm_lapic *apic;
1890         int i;
1891
1892         apic_debug("%s\n", __func__);
1893
1894         ASSERT(vcpu);
1895         apic = vcpu->arch.apic;
1896         ASSERT(apic != NULL);
1897
1898         /* Stop the timer in case it's a reset to an active apic */
1899         hrtimer_cancel(&apic->lapic_timer.timer);
1900
1901         if (!init_event) {
1902                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
1903                                          MSR_IA32_APICBASE_ENABLE);
1904                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1905         }
1906         kvm_apic_set_version(apic->vcpu);
1907
1908         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1909                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1910         apic_update_lvtt(apic);
1911         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1912                 kvm_lapic_set_reg(apic, APIC_LVT0,
1913                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1914         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1915
1916         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
1917         apic_set_spiv(apic, 0xff);
1918         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
1919         if (!apic_x2apic_mode(apic))
1920                 kvm_apic_set_ldr(apic, 0);
1921         kvm_lapic_set_reg(apic, APIC_ESR, 0);
1922         kvm_lapic_set_reg(apic, APIC_ICR, 0);
1923         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1924         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1925         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1926         for (i = 0; i < 8; i++) {
1927                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1928                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1929                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1930         }
1931         apic->irr_pending = vcpu->arch.apicv_active;
1932         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1933         apic->highest_isr_cache = -1;
1934         update_divide_count(apic);
1935         atomic_set(&apic->lapic_timer.pending, 0);
1936         if (kvm_vcpu_is_bsp(vcpu))
1937                 kvm_lapic_set_base(vcpu,
1938                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1939         vcpu->arch.pv_eoi.msr_val = 0;
1940         apic_update_ppr(apic);
1941
1942         vcpu->arch.apic_arb_prio = 0;
1943         vcpu->arch.apic_attention = 0;
1944
1945         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
1946                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1947                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
1948                    vcpu->arch.apic_base, apic->base_address);
1949 }
1950
1951 /*
1952  *----------------------------------------------------------------------
1953  * timer interface
1954  *----------------------------------------------------------------------
1955  */
1956
1957 static bool lapic_is_periodic(struct kvm_lapic *apic)
1958 {
1959         return apic_lvtt_period(apic);
1960 }
1961
1962 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1963 {
1964         struct kvm_lapic *apic = vcpu->arch.apic;
1965
1966         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1967                 return atomic_read(&apic->lapic_timer.pending);
1968
1969         return 0;
1970 }
1971
1972 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1973 {
1974         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
1975         int vector, mode, trig_mode;
1976
1977         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1978                 vector = reg & APIC_VECTOR_MASK;
1979                 mode = reg & APIC_MODE_MASK;
1980                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1981                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1982                                         NULL);
1983         }
1984         return 0;
1985 }
1986
1987 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1988 {
1989         struct kvm_lapic *apic = vcpu->arch.apic;
1990
1991         if (apic)
1992                 kvm_apic_local_deliver(apic, APIC_LVT0);
1993 }
1994
1995 static const struct kvm_io_device_ops apic_mmio_ops = {
1996         .read     = apic_mmio_read,
1997         .write    = apic_mmio_write,
1998 };
1999
2000 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2001 {
2002         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2003         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2004
2005         apic_timer_expired(apic);
2006
2007         if (lapic_is_periodic(apic)) {
2008                 advance_periodic_target_expiration(apic);
2009                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2010                 return HRTIMER_RESTART;
2011         } else
2012                 return HRTIMER_NORESTART;
2013 }
2014
2015 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2016 {
2017         struct kvm_lapic *apic;
2018
2019         ASSERT(vcpu != NULL);
2020         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2021
2022         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2023         if (!apic)
2024                 goto nomem;
2025
2026         vcpu->arch.apic = apic;
2027
2028         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2029         if (!apic->regs) {
2030                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2031                        vcpu->vcpu_id);
2032                 goto nomem_free_apic;
2033         }
2034         apic->vcpu = vcpu;
2035
2036         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2037                      HRTIMER_MODE_ABS_PINNED);
2038         apic->lapic_timer.timer.function = apic_timer_fn;
2039
2040         /*
2041          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2042          * thinking that APIC satet has changed.
2043          */
2044         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2045         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2046         kvm_lapic_reset(vcpu, false);
2047         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2048
2049         return 0;
2050 nomem_free_apic:
2051         kfree(apic);
2052 nomem:
2053         return -ENOMEM;
2054 }
2055
2056 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2057 {
2058         struct kvm_lapic *apic = vcpu->arch.apic;
2059         int highest_irr;
2060
2061         if (!apic_enabled(apic))
2062                 return -1;
2063
2064         apic_update_ppr(apic);
2065         highest_irr = apic_find_highest_irr(apic);
2066         if ((highest_irr == -1) ||
2067             ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI)))
2068                 return -1;
2069         return highest_irr;
2070 }
2071
2072 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2073 {
2074         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2075         int r = 0;
2076
2077         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2078                 r = 1;
2079         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2080             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2081                 r = 1;
2082         return r;
2083 }
2084
2085 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2086 {
2087         struct kvm_lapic *apic = vcpu->arch.apic;
2088
2089         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2090                 kvm_apic_local_deliver(apic, APIC_LVTT);
2091                 if (apic_lvtt_tscdeadline(apic))
2092                         apic->lapic_timer.tscdeadline = 0;
2093                 if (apic_lvtt_oneshot(apic)) {
2094                         apic->lapic_timer.tscdeadline = 0;
2095                         apic->lapic_timer.target_expiration = 0;
2096                 }
2097                 atomic_set(&apic->lapic_timer.pending, 0);
2098         }
2099 }
2100
2101 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2102 {
2103         int vector = kvm_apic_has_interrupt(vcpu);
2104         struct kvm_lapic *apic = vcpu->arch.apic;
2105
2106         if (vector == -1)
2107                 return -1;
2108
2109         /*
2110          * We get here even with APIC virtualization enabled, if doing
2111          * nested virtualization and L1 runs with the "acknowledge interrupt
2112          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2113          * because the process would deliver it through the IDT.
2114          */
2115
2116         apic_set_isr(vector, apic);
2117         apic_update_ppr(apic);
2118         apic_clear_irr(vector, apic);
2119
2120         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2121                 apic_clear_isr(vector, apic);
2122                 apic_update_ppr(apic);
2123         }
2124
2125         return vector;
2126 }
2127
2128 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2129                 struct kvm_lapic_state *s, bool set)
2130 {
2131         if (apic_x2apic_mode(vcpu->arch.apic)) {
2132                 u32 *id = (u32 *)(s->regs + APIC_ID);
2133
2134                 if (vcpu->kvm->arch.x2apic_format) {
2135                         if (*id != vcpu->vcpu_id)
2136                                 return -EINVAL;
2137                 } else {
2138                         if (set)
2139                                 *id >>= 24;
2140                         else
2141                                 *id <<= 24;
2142                 }
2143         }
2144
2145         return 0;
2146 }
2147
2148 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2149 {
2150         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2151         return kvm_apic_state_fixup(vcpu, s, false);
2152 }
2153
2154 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2155 {
2156         struct kvm_lapic *apic = vcpu->arch.apic;
2157         int r;
2158
2159
2160         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2161         /* set SPIV separately to get count of SW disabled APICs right */
2162         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2163
2164         r = kvm_apic_state_fixup(vcpu, s, true);
2165         if (r)
2166                 return r;
2167         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2168
2169         recalculate_apic_map(vcpu->kvm);
2170         kvm_apic_set_version(vcpu);
2171
2172         apic_update_ppr(apic);
2173         hrtimer_cancel(&apic->lapic_timer.timer);
2174         apic_update_lvtt(apic);
2175         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2176         update_divide_count(apic);
2177         start_apic_timer(apic);
2178         apic->irr_pending = true;
2179         apic->isr_count = vcpu->arch.apicv_active ?
2180                                 1 : count_vectors(apic->regs + APIC_ISR);
2181         apic->highest_isr_cache = -1;
2182         if (vcpu->arch.apicv_active) {
2183                 if (kvm_x86_ops->apicv_post_state_restore)
2184                         kvm_x86_ops->apicv_post_state_restore(vcpu);
2185                 kvm_x86_ops->hwapic_irr_update(vcpu,
2186                                 apic_find_highest_irr(apic));
2187                 kvm_x86_ops->hwapic_isr_update(vcpu,
2188                                 apic_find_highest_isr(apic));
2189         }
2190         kvm_make_request(KVM_REQ_EVENT, vcpu);
2191         if (ioapic_in_kernel(vcpu->kvm))
2192                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2193
2194         vcpu->arch.apic_arb_prio = 0;
2195
2196         return 0;
2197 }
2198
2199 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2200 {
2201         struct hrtimer *timer;
2202
2203         if (!lapic_in_kernel(vcpu))
2204                 return;
2205
2206         timer = &vcpu->arch.apic->lapic_timer.timer;
2207         if (hrtimer_cancel(timer))
2208                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2209 }
2210
2211 /*
2212  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2213  *
2214  * Detect whether guest triggered PV EOI since the
2215  * last entry. If yes, set EOI on guests's behalf.
2216  * Clear PV EOI in guest memory in any case.
2217  */
2218 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2219                                         struct kvm_lapic *apic)
2220 {
2221         bool pending;
2222         int vector;
2223         /*
2224          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2225          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2226          *
2227          * KVM_APIC_PV_EOI_PENDING is unset:
2228          *      -> host disabled PV EOI.
2229          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2230          *      -> host enabled PV EOI, guest did not execute EOI yet.
2231          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2232          *      -> host enabled PV EOI, guest executed EOI.
2233          */
2234         BUG_ON(!pv_eoi_enabled(vcpu));
2235         pending = pv_eoi_get_pending(vcpu);
2236         /*
2237          * Clear pending bit in any case: it will be set again on vmentry.
2238          * While this might not be ideal from performance point of view,
2239          * this makes sure pv eoi is only enabled when we know it's safe.
2240          */
2241         pv_eoi_clr_pending(vcpu);
2242         if (pending)
2243                 return;
2244         vector = apic_set_eoi(apic);
2245         trace_kvm_pv_eoi(apic, vector);
2246 }
2247
2248 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2249 {
2250         u32 data;
2251
2252         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2253                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2254
2255         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2256                 return;
2257
2258         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2259                                   sizeof(u32)))
2260                 return;
2261
2262         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2263 }
2264
2265 /*
2266  * apic_sync_pv_eoi_to_guest - called before vmentry
2267  *
2268  * Detect whether it's safe to enable PV EOI and
2269  * if yes do so.
2270  */
2271 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2272                                         struct kvm_lapic *apic)
2273 {
2274         if (!pv_eoi_enabled(vcpu) ||
2275             /* IRR set or many bits in ISR: could be nested. */
2276             apic->irr_pending ||
2277             /* Cache not set: could be safe but we don't bother. */
2278             apic->highest_isr_cache == -1 ||
2279             /* Need EOI to update ioapic. */
2280             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2281                 /*
2282                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2283                  * so we need not do anything here.
2284                  */
2285                 return;
2286         }
2287
2288         pv_eoi_set_pending(apic->vcpu);
2289 }
2290
2291 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2292 {
2293         u32 data, tpr;
2294         int max_irr, max_isr;
2295         struct kvm_lapic *apic = vcpu->arch.apic;
2296
2297         apic_sync_pv_eoi_to_guest(vcpu, apic);
2298
2299         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2300                 return;
2301
2302         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2303         max_irr = apic_find_highest_irr(apic);
2304         if (max_irr < 0)
2305                 max_irr = 0;
2306         max_isr = apic_find_highest_isr(apic);
2307         if (max_isr < 0)
2308                 max_isr = 0;
2309         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2310
2311         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2312                                 sizeof(u32));
2313 }
2314
2315 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2316 {
2317         if (vapic_addr) {
2318                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2319                                         &vcpu->arch.apic->vapic_cache,
2320                                         vapic_addr, sizeof(u32)))
2321                         return -EINVAL;
2322                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2323         } else {
2324                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2325         }
2326
2327         vcpu->arch.apic->vapic_addr = vapic_addr;
2328         return 0;
2329 }
2330
2331 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2332 {
2333         struct kvm_lapic *apic = vcpu->arch.apic;
2334         u32 reg = (msr - APIC_BASE_MSR) << 4;
2335
2336         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2337                 return 1;
2338
2339         if (reg == APIC_ICR2)
2340                 return 1;
2341
2342         /* if this is ICR write vector before command */
2343         if (reg == APIC_ICR)
2344                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2345         return kvm_lapic_reg_write(apic, reg, (u32)data);
2346 }
2347
2348 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2349 {
2350         struct kvm_lapic *apic = vcpu->arch.apic;
2351         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2352
2353         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2354                 return 1;
2355
2356         if (reg == APIC_DFR || reg == APIC_ICR2) {
2357                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2358                            reg);
2359                 return 1;
2360         }
2361
2362         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2363                 return 1;
2364         if (reg == APIC_ICR)
2365                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2366
2367         *data = (((u64)high) << 32) | low;
2368
2369         return 0;
2370 }
2371
2372 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2373 {
2374         struct kvm_lapic *apic = vcpu->arch.apic;
2375
2376         if (!lapic_in_kernel(vcpu))
2377                 return 1;
2378
2379         /* if this is ICR write vector before command */
2380         if (reg == APIC_ICR)
2381                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2382         return kvm_lapic_reg_write(apic, reg, (u32)data);
2383 }
2384
2385 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2386 {
2387         struct kvm_lapic *apic = vcpu->arch.apic;
2388         u32 low, high = 0;
2389
2390         if (!lapic_in_kernel(vcpu))
2391                 return 1;
2392
2393         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2394                 return 1;
2395         if (reg == APIC_ICR)
2396                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2397
2398         *data = (((u64)high) << 32) | low;
2399
2400         return 0;
2401 }
2402
2403 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2404 {
2405         u64 addr = data & ~KVM_MSR_ENABLED;
2406         if (!IS_ALIGNED(addr, 4))
2407                 return 1;
2408
2409         vcpu->arch.pv_eoi.msr_val = data;
2410         if (!pv_eoi_enabled(vcpu))
2411                 return 0;
2412         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2413                                          addr, sizeof(u8));
2414 }
2415
2416 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2417 {
2418         struct kvm_lapic *apic = vcpu->arch.apic;
2419         u8 sipi_vector;
2420         unsigned long pe;
2421
2422         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2423                 return;
2424
2425         /*
2426          * INITs are latched while in SMM.  Because an SMM CPU cannot
2427          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2428          * and delay processing of INIT until the next RSM.
2429          */
2430         if (is_smm(vcpu)) {
2431                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2432                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2433                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2434                 return;
2435         }
2436
2437         pe = xchg(&apic->pending_events, 0);
2438         if (test_bit(KVM_APIC_INIT, &pe)) {
2439                 kvm_lapic_reset(vcpu, true);
2440                 kvm_vcpu_reset(vcpu, true);
2441                 if (kvm_vcpu_is_bsp(apic->vcpu))
2442                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2443                 else
2444                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2445         }
2446         if (test_bit(KVM_APIC_SIPI, &pe) &&
2447             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2448                 /* evaluate pending_events before reading the vector */
2449                 smp_rmb();
2450                 sipi_vector = apic->sipi_vector;
2451                 apic_debug("vcpu %d received sipi with vector # %x\n",
2452                          vcpu->vcpu_id, sipi_vector);
2453                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2454                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2455         }
2456 }
2457
2458 void kvm_lapic_init(void)
2459 {
2460         /* do not patch jump label more than once per second */
2461         jump_label_rate_limit(&apic_hw_disabled, HZ);
2462         jump_label_rate_limit(&apic_sw_disabled, HZ);
2463 }