3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 #define APIC_BUS_CYCLE_NS 1
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
80 *((u32 *) (apic->regs + reg_off)) = val;
83 static inline int apic_test_vector(int vec, void *bitmap)
85 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
90 struct kvm_lapic *apic = vcpu->arch.apic;
92 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
93 apic_test_vector(vector, apic->regs + APIC_IRR);
96 static inline void apic_set_vector(int vec, void *bitmap)
98 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101 static inline void apic_clear_vector(int vec, void *bitmap)
103 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
108 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
113 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
116 struct static_key_deferred apic_hw_disabled __read_mostly;
117 struct static_key_deferred apic_sw_disabled __read_mostly;
119 static inline int apic_enabled(struct kvm_lapic *apic)
121 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
131 static inline int kvm_apic_id(struct kvm_lapic *apic)
133 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
136 static void recalculate_apic_map(struct kvm *kvm)
138 struct kvm_apic_map *new, *old = NULL;
139 struct kvm_vcpu *vcpu;
142 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
144 mutex_lock(&kvm->arch.apic_map_lock);
150 /* flat mode is default */
153 new->lid_mask = 0xff;
154 new->broadcast = APIC_BROADCAST;
156 kvm_for_each_vcpu(i, vcpu, kvm) {
157 struct kvm_lapic *apic = vcpu->arch.apic;
159 if (!kvm_apic_present(vcpu))
162 if (apic_x2apic_mode(apic)) {
165 new->cid_mask = new->lid_mask = 0xffff;
166 new->broadcast = X2APIC_BROADCAST;
167 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
168 if (kvm_apic_get_reg(apic, APIC_DFR) ==
176 new->lid_mask = 0xff;
181 * All APICs have to be configured in the same mode by an OS.
182 * We take advatage of this while building logical id loockup
183 * table. After reset APICs are in software disabled mode, so if
184 * we find apic with different setting we assume this is the mode
185 * OS wants all apics to be in; build lookup table accordingly.
187 if (kvm_apic_sw_enabled(apic))
191 kvm_for_each_vcpu(i, vcpu, kvm) {
192 struct kvm_lapic *apic = vcpu->arch.apic;
196 aid = kvm_apic_id(apic);
197 ldr = kvm_apic_get_reg(apic, APIC_LDR);
198 cid = apic_cluster_id(new, ldr);
199 lid = apic_logical_id(new, ldr);
201 if (aid < ARRAY_SIZE(new->phys_map))
202 new->phys_map[aid] = apic;
203 if (lid && cid < ARRAY_SIZE(new->logical_map))
204 new->logical_map[cid][ffs(lid) - 1] = apic;
207 old = rcu_dereference_protected(kvm->arch.apic_map,
208 lockdep_is_held(&kvm->arch.apic_map_lock));
209 rcu_assign_pointer(kvm->arch.apic_map, new);
210 mutex_unlock(&kvm->arch.apic_map_lock);
215 kvm_vcpu_request_scan_ioapic(kvm);
218 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
220 bool enabled = val & APIC_SPIV_APIC_ENABLED;
222 apic_set_reg(apic, APIC_SPIV, val);
224 if (enabled != apic->sw_enabled) {
225 apic->sw_enabled = enabled;
227 static_key_slow_dec_deferred(&apic_sw_disabled);
228 recalculate_apic_map(apic->vcpu->kvm);
230 static_key_slow_inc(&apic_sw_disabled.key);
234 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
236 apic_set_reg(apic, APIC_ID, id << 24);
237 recalculate_apic_map(apic->vcpu->kvm);
240 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
242 apic_set_reg(apic, APIC_LDR, id);
243 recalculate_apic_map(apic->vcpu->kvm);
246 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
248 return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
251 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
253 return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
256 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
258 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
261 static inline int apic_lvtt_period(struct kvm_lapic *apic)
263 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
266 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
268 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
271 static inline int apic_lvt_nmi_mode(u32 lvt_val)
273 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
276 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
278 struct kvm_lapic *apic = vcpu->arch.apic;
279 struct kvm_cpuid_entry2 *feat;
280 u32 v = APIC_VERSION;
282 if (!kvm_vcpu_has_lapic(vcpu))
285 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
286 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
287 v |= APIC_LVR_DIRECTED_EOI;
288 apic_set_reg(apic, APIC_LVR, v);
291 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
292 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
293 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
294 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
295 LINT_MASK, LINT_MASK, /* LVT0-1 */
296 LVT_MASK /* LVTERR */
299 static int find_highest_vector(void *bitmap)
304 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
305 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
306 reg = bitmap + REG_POS(vec);
308 return fls(*reg) - 1 + vec;
314 static u8 count_vectors(void *bitmap)
320 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
321 reg = bitmap + REG_POS(vec);
322 count += hweight32(*reg);
328 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
331 struct kvm_lapic *apic = vcpu->arch.apic;
333 for (i = 0; i <= 7; i++) {
334 pir_val = xchg(&pir[i], 0);
336 *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
339 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
341 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
343 apic_set_vector(vec, apic->regs + APIC_IRR);
345 * irr_pending must be true if any interrupt is pending; set it after
346 * APIC_IRR to avoid race with apic_clear_irr
348 apic->irr_pending = true;
351 static inline int apic_search_irr(struct kvm_lapic *apic)
353 return find_highest_vector(apic->regs + APIC_IRR);
356 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
361 * Note that irr_pending is just a hint. It will be always
362 * true with virtual interrupt delivery enabled.
364 if (!apic->irr_pending)
367 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
368 result = apic_search_irr(apic);
369 ASSERT(result == -1 || result >= 16);
374 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
376 struct kvm_vcpu *vcpu;
380 if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
381 /* try to update RVI */
382 apic_clear_vector(vec, apic->regs + APIC_IRR);
383 kvm_make_request(KVM_REQ_EVENT, vcpu);
385 apic->irr_pending = false;
386 apic_clear_vector(vec, apic->regs + APIC_IRR);
387 if (apic_search_irr(apic) != -1)
388 apic->irr_pending = true;
392 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
394 struct kvm_vcpu *vcpu;
396 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
402 * With APIC virtualization enabled, all caching is disabled
403 * because the processor can modify ISR under the hood. Instead
406 if (unlikely(kvm_x86_ops->hwapic_isr_update))
407 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
410 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
412 * ISR (in service register) bit is set when injecting an interrupt.
413 * The highest vector is injected. Thus the latest bit set matches
414 * the highest bit in ISR.
416 apic->highest_isr_cache = vec;
420 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
425 * Note that isr_count is always 1, and highest_isr_cache
426 * is always -1, with APIC virtualization enabled.
428 if (!apic->isr_count)
430 if (likely(apic->highest_isr_cache != -1))
431 return apic->highest_isr_cache;
433 result = find_highest_vector(apic->regs + APIC_ISR);
434 ASSERT(result == -1 || result >= 16);
439 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
441 struct kvm_vcpu *vcpu;
442 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
448 * We do get here for APIC virtualization enabled if the guest
449 * uses the Hyper-V APIC enlightenment. In this case we may need
450 * to trigger a new interrupt delivery by writing the SVI field;
451 * on the other hand isr_count and highest_isr_cache are unused
452 * and must be left alone.
454 if (unlikely(kvm_x86_ops->hwapic_isr_update))
455 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
456 apic_find_highest_isr(apic));
459 BUG_ON(apic->isr_count < 0);
460 apic->highest_isr_cache = -1;
464 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
468 /* This may race with setting of irr in __apic_accept_irq() and
469 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
470 * will cause vmexit immediately and the value will be recalculated
471 * on the next vmentry.
473 if (!kvm_vcpu_has_lapic(vcpu))
475 highest_irr = apic_find_highest_irr(vcpu->arch.apic);
480 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
481 int vector, int level, int trig_mode,
482 unsigned long *dest_map);
484 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
485 unsigned long *dest_map)
487 struct kvm_lapic *apic = vcpu->arch.apic;
489 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
490 irq->level, irq->trig_mode, dest_map);
493 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
496 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
500 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
503 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
507 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
509 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
512 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
515 if (pv_eoi_get_user(vcpu, &val) < 0)
516 apic_debug("Can't read EOI MSR value: 0x%llx\n",
517 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
521 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
523 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
524 apic_debug("Can't set EOI MSR value: 0x%llx\n",
525 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
528 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
531 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
533 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
534 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
535 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
538 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
541 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
543 struct kvm_lapic *apic = vcpu->arch.apic;
546 for (i = 0; i < 8; i++)
547 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
550 static void apic_update_ppr(struct kvm_lapic *apic)
552 u32 tpr, isrv, ppr, old_ppr;
555 old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
556 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
557 isr = apic_find_highest_isr(apic);
558 isrv = (isr != -1) ? isr : 0;
560 if ((tpr & 0xf0) >= (isrv & 0xf0))
565 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
566 apic, ppr, isr, isrv);
568 if (old_ppr != ppr) {
569 apic_set_reg(apic, APIC_PROCPRI, ppr);
571 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
575 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
577 apic_set_reg(apic, APIC_TASKPRI, tpr);
578 apic_update_ppr(apic);
581 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
583 return dest == (apic_x2apic_mode(apic) ?
584 X2APIC_BROADCAST : APIC_BROADCAST);
587 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
589 return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
592 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
597 if (kvm_apic_broadcast(apic, mda))
600 if (apic_x2apic_mode(apic)) {
601 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
602 return logical_id & mda;
605 logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
607 switch (kvm_apic_get_reg(apic, APIC_DFR)) {
609 if (logical_id & mda)
612 case APIC_DFR_CLUSTER:
613 if (((logical_id >> 4) == (mda >> 0x4))
614 && (logical_id & mda & 0xf))
618 apic_debug("Bad DFR vcpu %d: %08x\n",
619 apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
626 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
627 int short_hand, unsigned int dest, int dest_mode)
630 struct kvm_lapic *target = vcpu->arch.apic;
632 apic_debug("target %p, source %p, dest 0x%x, "
633 "dest_mode 0x%x, short_hand 0x%x\n",
634 target, source, dest, dest_mode, short_hand);
637 switch (short_hand) {
638 case APIC_DEST_NOSHORT:
641 result = kvm_apic_match_physical_addr(target, dest);
644 result = kvm_apic_match_logical_addr(target, dest);
647 result = (target == source);
649 case APIC_DEST_ALLINC:
652 case APIC_DEST_ALLBUT:
653 result = (target != source);
656 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
664 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
665 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
667 struct kvm_apic_map *map;
668 unsigned long bitmap = 1;
669 struct kvm_lapic **dst;
675 if (irq->shorthand == APIC_DEST_SELF) {
676 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
684 map = rcu_dereference(kvm->arch.apic_map);
689 if (irq->dest_id == map->broadcast)
694 if (irq->dest_mode == 0) { /* physical mode */
695 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
698 dst = &map->phys_map[irq->dest_id];
700 u32 mda = irq->dest_id << (32 - map->ldr_bits);
701 u16 cid = apic_cluster_id(map, mda);
703 if (cid >= ARRAY_SIZE(map->logical_map))
706 dst = map->logical_map[cid];
708 bitmap = apic_logical_id(map, mda);
710 if (irq->delivery_mode == APIC_DM_LOWEST) {
712 for_each_set_bit(i, &bitmap, 16) {
717 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
721 bitmap = (l >= 0) ? 1 << l : 0;
725 for_each_set_bit(i, &bitmap, 16) {
730 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
738 * Add a pending IRQ into lapic.
739 * Return 1 if successfully added and 0 if discarded.
741 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
742 int vector, int level, int trig_mode,
743 unsigned long *dest_map)
746 struct kvm_vcpu *vcpu = apic->vcpu;
748 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
750 switch (delivery_mode) {
752 vcpu->arch.apic_arb_prio++;
754 /* FIXME add logic for vcpu on reset */
755 if (unlikely(!apic_enabled(apic)))
761 __set_bit(vcpu->vcpu_id, dest_map);
763 if (kvm_x86_ops->deliver_posted_interrupt)
764 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
766 apic_set_irr(vector, apic);
768 kvm_make_request(KVM_REQ_EVENT, vcpu);
775 vcpu->arch.pv.pv_unhalted = 1;
776 kvm_make_request(KVM_REQ_EVENT, vcpu);
781 apic_debug("Ignoring guest SMI\n");
786 kvm_inject_nmi(vcpu);
791 if (!trig_mode || level) {
793 /* assumes that there are only KVM_APIC_INIT/SIPI */
794 apic->pending_events = (1UL << KVM_APIC_INIT);
795 /* make sure pending_events is visible before sending
798 kvm_make_request(KVM_REQ_EVENT, vcpu);
801 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
806 case APIC_DM_STARTUP:
807 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
808 vcpu->vcpu_id, vector);
810 apic->sipi_vector = vector;
811 /* make sure sipi_vector is visible for the receiver */
813 set_bit(KVM_APIC_SIPI, &apic->pending_events);
814 kvm_make_request(KVM_REQ_EVENT, vcpu);
820 * Should only be called by kvm_apic_local_deliver() with LVT0,
821 * before NMI watchdog was enabled. Already handled by
822 * kvm_apic_accept_pic_intr().
827 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
834 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
836 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
839 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
841 if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
842 kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
844 if (apic_test_vector(vector, apic->regs + APIC_TMR))
845 trigger_mode = IOAPIC_LEVEL_TRIG;
847 trigger_mode = IOAPIC_EDGE_TRIG;
848 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
852 static int apic_set_eoi(struct kvm_lapic *apic)
854 int vector = apic_find_highest_isr(apic);
856 trace_kvm_eoi(apic, vector);
859 * Not every write EOI will has corresponding ISR,
860 * one example is when Kernel check timer on setup_IO_APIC
865 apic_clear_isr(vector, apic);
866 apic_update_ppr(apic);
868 kvm_ioapic_send_eoi(apic, vector);
869 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
874 * this interface assumes a trap-like exit, which has already finished
875 * desired side effect including vISR and vPPR update.
877 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
879 struct kvm_lapic *apic = vcpu->arch.apic;
881 trace_kvm_eoi(apic, vector);
883 kvm_ioapic_send_eoi(apic, vector);
884 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
886 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
888 static void apic_send_ipi(struct kvm_lapic *apic)
890 u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
891 u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
892 struct kvm_lapic_irq irq;
894 irq.vector = icr_low & APIC_VECTOR_MASK;
895 irq.delivery_mode = icr_low & APIC_MODE_MASK;
896 irq.dest_mode = icr_low & APIC_DEST_MASK;
897 irq.level = icr_low & APIC_INT_ASSERT;
898 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
899 irq.shorthand = icr_low & APIC_SHORT_MASK;
900 if (apic_x2apic_mode(apic))
901 irq.dest_id = icr_high;
903 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
905 trace_kvm_apic_ipi(icr_low, irq.dest_id);
907 apic_debug("icr_high 0x%x, icr_low 0x%x, "
908 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
909 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
910 icr_high, icr_low, irq.shorthand, irq.dest_id,
911 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
914 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
917 static u32 apic_get_tmcct(struct kvm_lapic *apic)
923 ASSERT(apic != NULL);
925 /* if initial count is 0, current count should also be 0 */
926 if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
927 apic->lapic_timer.period == 0)
930 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
931 if (ktime_to_ns(remaining) < 0)
932 remaining = ktime_set(0, 0);
934 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
935 tmcct = div64_u64(ns,
936 (APIC_BUS_CYCLE_NS * apic->divide_count));
941 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
943 struct kvm_vcpu *vcpu = apic->vcpu;
944 struct kvm_run *run = vcpu->run;
946 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
947 run->tpr_access.rip = kvm_rip_read(vcpu);
948 run->tpr_access.is_write = write;
951 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
953 if (apic->vcpu->arch.tpr_access_reporting)
954 __report_tpr_access(apic, write);
957 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
961 if (offset >= LAPIC_MMIO_LENGTH)
966 if (apic_x2apic_mode(apic))
967 val = kvm_apic_id(apic);
969 val = kvm_apic_id(apic) << 24;
972 apic_debug("Access APIC ARBPRI register which is for P6\n");
975 case APIC_TMCCT: /* Timer CCR */
976 if (apic_lvtt_tscdeadline(apic))
979 val = apic_get_tmcct(apic);
982 apic_update_ppr(apic);
983 val = kvm_apic_get_reg(apic, offset);
986 report_tpr_access(apic, false);
989 val = kvm_apic_get_reg(apic, offset);
996 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
998 return container_of(dev, struct kvm_lapic, dev);
1001 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1004 unsigned char alignment = offset & 0xf;
1006 /* this bitmask has a bit cleared for each reserved register */
1007 static const u64 rmask = 0x43ff01ffffffe70cULL;
1009 if ((alignment + len) > 4) {
1010 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1015 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1016 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1021 result = __apic_read(apic, offset & ~0xf);
1023 trace_kvm_apic_read(offset, result);
1029 memcpy(data, (char *)&result + alignment, len);
1032 printk(KERN_ERR "Local APIC read with len = %x, "
1033 "should be 1,2, or 4 instead\n", len);
1039 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1041 return kvm_apic_hw_enabled(apic) &&
1042 addr >= apic->base_address &&
1043 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1046 static int apic_mmio_read(struct kvm_io_device *this,
1047 gpa_t address, int len, void *data)
1049 struct kvm_lapic *apic = to_lapic(this);
1050 u32 offset = address - apic->base_address;
1052 if (!apic_mmio_in_range(apic, address))
1055 apic_reg_read(apic, offset, len, data);
1060 static void update_divide_count(struct kvm_lapic *apic)
1062 u32 tmp1, tmp2, tdcr;
1064 tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1066 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1067 apic->divide_count = 0x1 << (tmp2 & 0x7);
1069 apic_debug("timer divide count is 0x%x\n",
1070 apic->divide_count);
1073 static void apic_timer_expired(struct kvm_lapic *apic)
1075 struct kvm_vcpu *vcpu = apic->vcpu;
1076 wait_queue_head_t *q = &vcpu->wq;
1077 struct kvm_timer *ktimer = &apic->lapic_timer;
1079 if (atomic_read(&apic->lapic_timer.pending))
1082 atomic_inc(&apic->lapic_timer.pending);
1083 kvm_set_pending_timer(vcpu);
1085 if (waitqueue_active(q))
1086 wake_up_interruptible(q);
1088 if (apic_lvtt_tscdeadline(apic))
1089 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1093 * On APICv, this test will cause a busy wait
1094 * during a higher-priority task.
1097 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1099 struct kvm_lapic *apic = vcpu->arch.apic;
1100 u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1102 if (kvm_apic_hw_enabled(apic)) {
1103 int vec = reg & APIC_VECTOR_MASK;
1105 if (kvm_x86_ops->test_posted_interrupt)
1106 return kvm_x86_ops->test_posted_interrupt(vcpu, vec);
1108 if (apic_test_vector(vec, apic->regs + APIC_ISR))
1115 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1117 struct kvm_lapic *apic = vcpu->arch.apic;
1118 u64 guest_tsc, tsc_deadline;
1120 if (!kvm_vcpu_has_lapic(vcpu))
1123 if (apic->lapic_timer.expired_tscdeadline == 0)
1126 if (!lapic_timer_int_injected(vcpu))
1129 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1130 apic->lapic_timer.expired_tscdeadline = 0;
1131 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1132 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1134 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1135 if (guest_tsc < tsc_deadline)
1136 __delay(tsc_deadline - guest_tsc);
1139 static void start_apic_timer(struct kvm_lapic *apic)
1143 atomic_set(&apic->lapic_timer.pending, 0);
1145 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1146 /* lapic timer in oneshot or periodic mode */
1147 now = apic->lapic_timer.timer.base->get_time();
1148 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1149 * APIC_BUS_CYCLE_NS * apic->divide_count;
1151 if (!apic->lapic_timer.period)
1154 * Do not allow the guest to program periodic timers with small
1155 * interval, since the hrtimers are not throttled by the host
1158 if (apic_lvtt_period(apic)) {
1159 s64 min_period = min_timer_period_us * 1000LL;
1161 if (apic->lapic_timer.period < min_period) {
1162 pr_info_ratelimited(
1163 "kvm: vcpu %i: requested %lld ns "
1164 "lapic timer period limited to %lld ns\n",
1165 apic->vcpu->vcpu_id,
1166 apic->lapic_timer.period, min_period);
1167 apic->lapic_timer.period = min_period;
1171 hrtimer_start(&apic->lapic_timer.timer,
1172 ktime_add_ns(now, apic->lapic_timer.period),
1175 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1177 "timer initial count 0x%x, period %lldns, "
1178 "expire @ 0x%016" PRIx64 ".\n", __func__,
1179 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1180 kvm_apic_get_reg(apic, APIC_TMICT),
1181 apic->lapic_timer.period,
1182 ktime_to_ns(ktime_add_ns(now,
1183 apic->lapic_timer.period)));
1184 } else if (apic_lvtt_tscdeadline(apic)) {
1185 /* lapic timer in tsc deadline mode */
1186 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1189 struct kvm_vcpu *vcpu = apic->vcpu;
1190 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1191 unsigned long flags;
1193 if (unlikely(!tscdeadline || !this_tsc_khz))
1196 local_irq_save(flags);
1198 now = apic->lapic_timer.timer.base->get_time();
1199 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1200 if (likely(tscdeadline > guest_tsc)) {
1201 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1202 do_div(ns, this_tsc_khz);
1203 expire = ktime_add_ns(now, ns);
1204 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1205 hrtimer_start(&apic->lapic_timer.timer,
1206 expire, HRTIMER_MODE_ABS);
1208 apic_timer_expired(apic);
1210 local_irq_restore(flags);
1214 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1216 int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1218 if (apic_lvt_nmi_mode(lvt0_val)) {
1219 if (!nmi_wd_enabled) {
1220 apic_debug("Receive NMI setting on APIC_LVT0 "
1221 "for cpu %d\n", apic->vcpu->vcpu_id);
1222 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1224 } else if (nmi_wd_enabled)
1225 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1228 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1232 trace_kvm_apic_write(reg, val);
1235 case APIC_ID: /* Local APIC ID */
1236 if (!apic_x2apic_mode(apic))
1237 kvm_apic_set_id(apic, val >> 24);
1243 report_tpr_access(apic, true);
1244 apic_set_tpr(apic, val & 0xff);
1252 if (!apic_x2apic_mode(apic))
1253 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1259 if (!apic_x2apic_mode(apic)) {
1260 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1261 recalculate_apic_map(apic->vcpu->kvm);
1268 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1269 mask |= APIC_SPIV_DIRECTED_EOI;
1270 apic_set_spiv(apic, val & mask);
1271 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1275 for (i = 0; i < APIC_LVT_NUM; i++) {
1276 lvt_val = kvm_apic_get_reg(apic,
1277 APIC_LVTT + 0x10 * i);
1278 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1279 lvt_val | APIC_LVT_MASKED);
1281 atomic_set(&apic->lapic_timer.pending, 0);
1287 /* No delay here, so we always clear the pending bit */
1288 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1289 apic_send_ipi(apic);
1293 if (!apic_x2apic_mode(apic))
1295 apic_set_reg(apic, APIC_ICR2, val);
1299 apic_manage_nmi_watchdog(apic, val);
1304 /* TODO: Check vector */
1305 if (!kvm_apic_sw_enabled(apic))
1306 val |= APIC_LVT_MASKED;
1308 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1309 apic_set_reg(apic, reg, val);
1314 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1316 if (apic->lapic_timer.timer_mode != timer_mode) {
1317 apic->lapic_timer.timer_mode = timer_mode;
1318 hrtimer_cancel(&apic->lapic_timer.timer);
1321 if (!kvm_apic_sw_enabled(apic))
1322 val |= APIC_LVT_MASKED;
1323 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1324 apic_set_reg(apic, APIC_LVTT, val);
1329 if (apic_lvtt_tscdeadline(apic))
1332 hrtimer_cancel(&apic->lapic_timer.timer);
1333 apic_set_reg(apic, APIC_TMICT, val);
1334 start_apic_timer(apic);
1339 apic_debug("KVM_WRITE:TDCR %x\n", val);
1340 apic_set_reg(apic, APIC_TDCR, val);
1341 update_divide_count(apic);
1345 if (apic_x2apic_mode(apic) && val != 0) {
1346 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1352 if (apic_x2apic_mode(apic)) {
1353 apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1362 apic_debug("Local APIC Write to read-only register %x\n", reg);
1366 static int apic_mmio_write(struct kvm_io_device *this,
1367 gpa_t address, int len, const void *data)
1369 struct kvm_lapic *apic = to_lapic(this);
1370 unsigned int offset = address - apic->base_address;
1373 if (!apic_mmio_in_range(apic, address))
1377 * APIC register must be aligned on 128-bits boundary.
1378 * 32/64/128 bits registers must be accessed thru 32 bits.
1381 if (len != 4 || (offset & 0xf)) {
1382 /* Don't shout loud, $infamous_os would cause only noise. */
1383 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1389 /* too common printing */
1390 if (offset != APIC_EOI)
1391 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1392 "0x%x\n", __func__, offset, len, val);
1394 apic_reg_write(apic, offset & 0xff0, val);
1399 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1401 if (kvm_vcpu_has_lapic(vcpu))
1402 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1404 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1406 /* emulate APIC access in a trap manner */
1407 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1411 /* hw has done the conditional check and inst decode */
1414 apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1416 /* TODO: optimize to just emulate side effect w/o one more write */
1417 apic_reg_write(vcpu->arch.apic, offset, val);
1419 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1421 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1423 struct kvm_lapic *apic = vcpu->arch.apic;
1425 if (!vcpu->arch.apic)
1428 hrtimer_cancel(&apic->lapic_timer.timer);
1430 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1431 static_key_slow_dec_deferred(&apic_hw_disabled);
1433 if (!apic->sw_enabled)
1434 static_key_slow_dec_deferred(&apic_sw_disabled);
1437 free_page((unsigned long)apic->regs);
1443 *----------------------------------------------------------------------
1445 *----------------------------------------------------------------------
1448 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1450 struct kvm_lapic *apic = vcpu->arch.apic;
1452 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1453 apic_lvtt_period(apic))
1456 return apic->lapic_timer.tscdeadline;
1459 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1461 struct kvm_lapic *apic = vcpu->arch.apic;
1463 if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1464 apic_lvtt_period(apic))
1467 hrtimer_cancel(&apic->lapic_timer.timer);
1468 apic->lapic_timer.tscdeadline = data;
1469 start_apic_timer(apic);
1472 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1474 struct kvm_lapic *apic = vcpu->arch.apic;
1476 if (!kvm_vcpu_has_lapic(vcpu))
1479 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1480 | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1483 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1487 if (!kvm_vcpu_has_lapic(vcpu))
1490 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1492 return (tpr & 0xf0) >> 4;
1495 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1497 u64 old_value = vcpu->arch.apic_base;
1498 struct kvm_lapic *apic = vcpu->arch.apic;
1501 value |= MSR_IA32_APICBASE_BSP;
1502 vcpu->arch.apic_base = value;
1506 if (!kvm_vcpu_is_bsp(apic->vcpu))
1507 value &= ~MSR_IA32_APICBASE_BSP;
1508 vcpu->arch.apic_base = value;
1510 /* update jump label if enable bit changes */
1511 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1512 if (value & MSR_IA32_APICBASE_ENABLE)
1513 static_key_slow_dec_deferred(&apic_hw_disabled);
1515 static_key_slow_inc(&apic_hw_disabled.key);
1516 recalculate_apic_map(vcpu->kvm);
1519 if ((old_value ^ value) & X2APIC_ENABLE) {
1520 if (value & X2APIC_ENABLE) {
1521 u32 id = kvm_apic_id(apic);
1522 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1523 kvm_apic_set_ldr(apic, ldr);
1524 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1526 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1529 apic->base_address = apic->vcpu->arch.apic_base &
1530 MSR_IA32_APICBASE_BASE;
1532 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1533 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1534 pr_warn_once("APIC base relocation is unsupported by KVM");
1536 /* with FSB delivery interrupt, we can restart APIC functionality */
1537 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1538 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1542 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1544 struct kvm_lapic *apic;
1547 apic_debug("%s\n", __func__);
1550 apic = vcpu->arch.apic;
1551 ASSERT(apic != NULL);
1553 /* Stop the timer in case it's a reset to an active apic */
1554 hrtimer_cancel(&apic->lapic_timer.timer);
1556 kvm_apic_set_id(apic, vcpu->vcpu_id);
1557 kvm_apic_set_version(apic->vcpu);
1559 for (i = 0; i < APIC_LVT_NUM; i++)
1560 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1561 apic->lapic_timer.timer_mode = 0;
1562 apic_set_reg(apic, APIC_LVT0,
1563 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1565 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1566 apic_set_spiv(apic, 0xff);
1567 apic_set_reg(apic, APIC_TASKPRI, 0);
1568 kvm_apic_set_ldr(apic, 0);
1569 apic_set_reg(apic, APIC_ESR, 0);
1570 apic_set_reg(apic, APIC_ICR, 0);
1571 apic_set_reg(apic, APIC_ICR2, 0);
1572 apic_set_reg(apic, APIC_TDCR, 0);
1573 apic_set_reg(apic, APIC_TMICT, 0);
1574 for (i = 0; i < 8; i++) {
1575 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1576 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1577 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1579 apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1580 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1581 apic->highest_isr_cache = -1;
1582 update_divide_count(apic);
1583 atomic_set(&apic->lapic_timer.pending, 0);
1584 if (kvm_vcpu_is_bsp(vcpu))
1585 kvm_lapic_set_base(vcpu,
1586 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1587 vcpu->arch.pv_eoi.msr_val = 0;
1588 apic_update_ppr(apic);
1590 vcpu->arch.apic_arb_prio = 0;
1591 vcpu->arch.apic_attention = 0;
1593 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1594 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1595 vcpu, kvm_apic_id(apic),
1596 vcpu->arch.apic_base, apic->base_address);
1600 *----------------------------------------------------------------------
1602 *----------------------------------------------------------------------
1605 static bool lapic_is_periodic(struct kvm_lapic *apic)
1607 return apic_lvtt_period(apic);
1610 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1612 struct kvm_lapic *apic = vcpu->arch.apic;
1614 if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1615 apic_lvt_enabled(apic, APIC_LVTT))
1616 return atomic_read(&apic->lapic_timer.pending);
1621 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1623 u32 reg = kvm_apic_get_reg(apic, lvt_type);
1624 int vector, mode, trig_mode;
1626 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1627 vector = reg & APIC_VECTOR_MASK;
1628 mode = reg & APIC_MODE_MASK;
1629 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1630 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1636 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1638 struct kvm_lapic *apic = vcpu->arch.apic;
1641 kvm_apic_local_deliver(apic, APIC_LVT0);
1644 static const struct kvm_io_device_ops apic_mmio_ops = {
1645 .read = apic_mmio_read,
1646 .write = apic_mmio_write,
1649 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1651 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1652 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1654 apic_timer_expired(apic);
1656 if (lapic_is_periodic(apic)) {
1657 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1658 return HRTIMER_RESTART;
1660 return HRTIMER_NORESTART;
1663 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1665 struct kvm_lapic *apic;
1667 ASSERT(vcpu != NULL);
1668 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1670 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1674 vcpu->arch.apic = apic;
1676 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1678 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1680 goto nomem_free_apic;
1684 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1686 apic->lapic_timer.timer.function = apic_timer_fn;
1689 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1690 * thinking that APIC satet has changed.
1692 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1693 kvm_lapic_set_base(vcpu,
1694 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1696 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1697 kvm_lapic_reset(vcpu);
1698 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1707 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1709 struct kvm_lapic *apic = vcpu->arch.apic;
1712 if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1715 apic_update_ppr(apic);
1716 highest_irr = apic_find_highest_irr(apic);
1717 if ((highest_irr == -1) ||
1718 ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1723 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1725 u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1728 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1730 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1731 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1736 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1738 struct kvm_lapic *apic = vcpu->arch.apic;
1740 if (!kvm_vcpu_has_lapic(vcpu))
1743 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1744 kvm_apic_local_deliver(apic, APIC_LVTT);
1745 if (apic_lvtt_tscdeadline(apic))
1746 apic->lapic_timer.tscdeadline = 0;
1747 atomic_set(&apic->lapic_timer.pending, 0);
1751 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1753 int vector = kvm_apic_has_interrupt(vcpu);
1754 struct kvm_lapic *apic = vcpu->arch.apic;
1760 * We get here even with APIC virtualization enabled, if doing
1761 * nested virtualization and L1 runs with the "acknowledge interrupt
1762 * on exit" mode. Then we cannot inject the interrupt via RVI,
1763 * because the process would deliver it through the IDT.
1766 apic_set_isr(vector, apic);
1767 apic_update_ppr(apic);
1768 apic_clear_irr(vector, apic);
1772 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1773 struct kvm_lapic_state *s)
1775 struct kvm_lapic *apic = vcpu->arch.apic;
1777 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1778 /* set SPIV separately to get count of SW disabled APICs right */
1779 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1780 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1781 /* call kvm_apic_set_id() to put apic into apic_map */
1782 kvm_apic_set_id(apic, kvm_apic_id(apic));
1783 kvm_apic_set_version(vcpu);
1785 apic_update_ppr(apic);
1786 hrtimer_cancel(&apic->lapic_timer.timer);
1787 update_divide_count(apic);
1788 start_apic_timer(apic);
1789 apic->irr_pending = true;
1790 apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1791 1 : count_vectors(apic->regs + APIC_ISR);
1792 apic->highest_isr_cache = -1;
1793 if (kvm_x86_ops->hwapic_irr_update)
1794 kvm_x86_ops->hwapic_irr_update(vcpu,
1795 apic_find_highest_irr(apic));
1796 if (unlikely(kvm_x86_ops->hwapic_isr_update))
1797 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1798 apic_find_highest_isr(apic));
1799 kvm_make_request(KVM_REQ_EVENT, vcpu);
1800 kvm_rtc_eoi_tracking_restore_one(vcpu);
1803 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1805 struct hrtimer *timer;
1807 if (!kvm_vcpu_has_lapic(vcpu))
1810 timer = &vcpu->arch.apic->lapic_timer.timer;
1811 if (hrtimer_cancel(timer))
1812 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1816 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1818 * Detect whether guest triggered PV EOI since the
1819 * last entry. If yes, set EOI on guests's behalf.
1820 * Clear PV EOI in guest memory in any case.
1822 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1823 struct kvm_lapic *apic)
1828 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1829 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1831 * KVM_APIC_PV_EOI_PENDING is unset:
1832 * -> host disabled PV EOI.
1833 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1834 * -> host enabled PV EOI, guest did not execute EOI yet.
1835 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1836 * -> host enabled PV EOI, guest executed EOI.
1838 BUG_ON(!pv_eoi_enabled(vcpu));
1839 pending = pv_eoi_get_pending(vcpu);
1841 * Clear pending bit in any case: it will be set again on vmentry.
1842 * While this might not be ideal from performance point of view,
1843 * this makes sure pv eoi is only enabled when we know it's safe.
1845 pv_eoi_clr_pending(vcpu);
1848 vector = apic_set_eoi(apic);
1849 trace_kvm_pv_eoi(apic, vector);
1852 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1856 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1857 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1859 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1862 kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1865 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1869 * apic_sync_pv_eoi_to_guest - called before vmentry
1871 * Detect whether it's safe to enable PV EOI and
1874 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1875 struct kvm_lapic *apic)
1877 if (!pv_eoi_enabled(vcpu) ||
1878 /* IRR set or many bits in ISR: could be nested. */
1879 apic->irr_pending ||
1880 /* Cache not set: could be safe but we don't bother. */
1881 apic->highest_isr_cache == -1 ||
1882 /* Need EOI to update ioapic. */
1883 kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1885 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1886 * so we need not do anything here.
1891 pv_eoi_set_pending(apic->vcpu);
1894 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1897 int max_irr, max_isr;
1898 struct kvm_lapic *apic = vcpu->arch.apic;
1900 apic_sync_pv_eoi_to_guest(vcpu, apic);
1902 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1905 tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1906 max_irr = apic_find_highest_irr(apic);
1909 max_isr = apic_find_highest_isr(apic);
1912 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1914 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1918 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1921 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1922 &vcpu->arch.apic->vapic_cache,
1923 vapic_addr, sizeof(u32)))
1925 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1927 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1930 vcpu->arch.apic->vapic_addr = vapic_addr;
1934 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1936 struct kvm_lapic *apic = vcpu->arch.apic;
1937 u32 reg = (msr - APIC_BASE_MSR) << 4;
1939 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1942 if (reg == APIC_ICR2)
1945 /* if this is ICR write vector before command */
1946 if (reg == APIC_ICR)
1947 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1948 return apic_reg_write(apic, reg, (u32)data);
1951 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1953 struct kvm_lapic *apic = vcpu->arch.apic;
1954 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1956 if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1959 if (reg == APIC_DFR || reg == APIC_ICR2) {
1960 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1965 if (apic_reg_read(apic, reg, 4, &low))
1967 if (reg == APIC_ICR)
1968 apic_reg_read(apic, APIC_ICR2, 4, &high);
1970 *data = (((u64)high) << 32) | low;
1975 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1977 struct kvm_lapic *apic = vcpu->arch.apic;
1979 if (!kvm_vcpu_has_lapic(vcpu))
1982 /* if this is ICR write vector before command */
1983 if (reg == APIC_ICR)
1984 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1985 return apic_reg_write(apic, reg, (u32)data);
1988 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1990 struct kvm_lapic *apic = vcpu->arch.apic;
1993 if (!kvm_vcpu_has_lapic(vcpu))
1996 if (apic_reg_read(apic, reg, 4, &low))
1998 if (reg == APIC_ICR)
1999 apic_reg_read(apic, APIC_ICR2, 4, &high);
2001 *data = (((u64)high) << 32) | low;
2006 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2008 u64 addr = data & ~KVM_MSR_ENABLED;
2009 if (!IS_ALIGNED(addr, 4))
2012 vcpu->arch.pv_eoi.msr_val = data;
2013 if (!pv_eoi_enabled(vcpu))
2015 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2019 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2021 struct kvm_lapic *apic = vcpu->arch.apic;
2025 if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2028 pe = xchg(&apic->pending_events, 0);
2030 if (test_bit(KVM_APIC_INIT, &pe)) {
2031 kvm_lapic_reset(vcpu);
2032 kvm_vcpu_reset(vcpu);
2033 if (kvm_vcpu_is_bsp(apic->vcpu))
2034 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2036 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2038 if (test_bit(KVM_APIC_SIPI, &pe) &&
2039 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2040 /* evaluate pending_events before reading the vector */
2042 sipi_vector = apic->sipi_vector;
2043 apic_debug("vcpu %d received sipi with vector # %x\n",
2044 vcpu->vcpu_id, sipi_vector);
2045 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2046 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2050 void kvm_lapic_init(void)
2052 /* do not patch jump label more than once per second */
2053 jump_label_rate_limit(&apic_hw_disabled, HZ);
2054 jump_label_rate_limit(&apic_sw_disabled, HZ);