arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 #define APIC_BUS_CYCLE_NS 1
  58
  59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  60 #define apic_debug(fmt, arg...)
  61
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 static inline int apic_test_vector(int vec, void *bitmap)
  76 {
  77         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  78 }
  79
  80 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  81 {
  82         struct kvm_lapic *apic = vcpu->arch.apic;
  83
  84         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  85                 apic_test_vector(vector, apic->regs + APIC_IRR);
  86 }
  87
  88 static inline void apic_clear_vector(int vec, void *bitmap)
  89 {
  90         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  91 }
  92
  93 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  94 {
  95         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  96 }
  97
  98 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
  99 {
 100         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 101 }
 102
 103 struct static_key_deferred apic_hw_disabled __read_mostly;
 104 struct static_key_deferred apic_sw_disabled __read_mostly;
 105
 106 static inline int apic_enabled(struct kvm_lapic *apic)
 107 {
 108         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 109 }
 110
 111 #define LVT_MASK        \
 112         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 113
 114 #define LINT_MASK       \
 115         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 116          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 117
 118 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 119 {
 120         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 121 }
 122
 123 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 124 {
 125         return apic->vcpu->vcpu_id;
 126 }
 127
 128 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 129                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 130         switch (map->mode) {
 131         case KVM_APIC_MODE_X2APIC: {
 132                 u32 offset = (dest_id >> 16) * 16;
 133                 u32 max_apic_id = map->max_apic_id;
 134
 135                 if (offset <= max_apic_id) {
 136                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 137
 138                         *cluster = &map->phys_map[offset];
 139                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 140                 } else {
 141                         *mask = 0;
 142                 }
 143
 144                 return true;
 145                 }
 146         case KVM_APIC_MODE_XAPIC_FLAT:
 147                 *cluster = map->xapic_flat_map;
 148                 *mask = dest_id & 0xff;
 149                 return true;
 150         case KVM_APIC_MODE_XAPIC_CLUSTER:
 151                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 152                 *mask = dest_id & 0xf;
 153                 return true;
 154         default:
 155                 /* Not optimized. */
 156                 return false;
 157         }
 158 }
 159
 160 static void kvm_apic_map_free(struct rcu_head *rcu)
 161 {
 162         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 163
 164         kvfree(map);
 165 }
 166
 167 static void recalculate_apic_map(struct kvm *kvm)
 168 {
 169         struct kvm_apic_map *new, *old = NULL;
 170         struct kvm_vcpu *vcpu;
 171         int i;
 172         u32 max_id = 255; /* enough space for any xAPIC ID */
 173
 174         mutex_lock(&kvm->arch.apic_map_lock);
 175
 176         kvm_for_each_vcpu(i, vcpu, kvm)
 177                 if (kvm_apic_present(vcpu))
 178                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 179
 180         new = kvm_kvzalloc(sizeof(struct kvm_apic_map) +
 181                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1));
 182
 183         if (!new)
 184                 goto out;
 185
 186         new->max_apic_id = max_id;
 187
 188         kvm_for_each_vcpu(i, vcpu, kvm) {
 189                 struct kvm_lapic *apic = vcpu->arch.apic;
 190                 struct kvm_lapic **cluster;
 191                 u16 mask;
 192                 u32 ldr;
 193                 u8 xapic_id;
 194                 u32 x2apic_id;
 195
 196                 if (!kvm_apic_present(vcpu))
 197                         continue;
 198
 199                 xapic_id = kvm_xapic_id(apic);
 200                 x2apic_id = kvm_x2apic_id(apic);
 201
 202                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 203                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 204                                 x2apic_id <= new->max_apic_id)
 205                         new->phys_map[x2apic_id] = apic;
 206                 /*
 207                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 208                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 209                  */
 210                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 211                         new->phys_map[xapic_id] = apic;
 212
 213                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 214
 215                 if (apic_x2apic_mode(apic)) {
 216                         new->mode |= KVM_APIC_MODE_X2APIC;
 217                 } else if (ldr) {
 218                         ldr = GET_APIC_LOGICAL_ID(ldr);
 219                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 220                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 221                         else
 222                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 223                 }
 224
 225                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 226                         continue;
 227
 228                 if (mask)
 229                         cluster[ffs(mask) - 1] = apic;
 230         }
 231 out:
 232         old = rcu_dereference_protected(kvm->arch.apic_map,
 233                         lockdep_is_held(&kvm->arch.apic_map_lock));
 234         rcu_assign_pointer(kvm->arch.apic_map, new);
 235         mutex_unlock(&kvm->arch.apic_map_lock);
 236
 237         if (old)
 238                 call_rcu(&old->rcu, kvm_apic_map_free);
 239
 240         kvm_make_scan_ioapic_request(kvm);
 241 }
 242
 243 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 244 {
 245         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 246
 247         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 248
 249         if (enabled != apic->sw_enabled) {
 250                 apic->sw_enabled = enabled;
 251                 if (enabled) {
 252                         static_key_slow_dec_deferred(&apic_sw_disabled);
 253                         recalculate_apic_map(apic->vcpu->kvm);
 254                 } else
 255                         static_key_slow_inc(&apic_sw_disabled.key);
 256         }
 257 }
 258
 259 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 260 {
 261         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 262         recalculate_apic_map(apic->vcpu->kvm);
 263 }
 264
 265 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 266 {
 267         kvm_lapic_set_reg(apic, APIC_LDR, id);
 268         recalculate_apic_map(apic->vcpu->kvm);
 269 }
 270
 271 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 272 {
 273         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
 274
 275         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 276
 277         kvm_lapic_set_reg(apic, APIC_ID, id);
 278         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 279         recalculate_apic_map(apic->vcpu->kvm);
 280 }
 281
 282 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 283 {
 284         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 285 }
 286
 287 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 288 {
 289         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 290 }
 291
 292 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 293 {
 294         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 295 }
 296
 297 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 298 {
 299         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 300 }
 301
 302 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 303 {
 304         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 305 }
 306
 307 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 308 {
 309         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 310 }
 311
 312 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 313 {
 314         struct kvm_lapic *apic = vcpu->arch.apic;
 315         struct kvm_cpuid_entry2 *feat;
 316         u32 v = APIC_VERSION;
 317
 318         if (!lapic_in_kernel(vcpu))
 319                 return;
 320
 321         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 322         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 323                 v |= APIC_LVR_DIRECTED_EOI;
 324         kvm_lapic_set_reg(apic, APIC_LVR, v);
 325 }
 326
 327 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 328         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 329         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 330         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 331         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 332         LVT_MASK                /* LVTERR */
 333 };
 334
 335 static int find_highest_vector(void *bitmap)
 336 {
 337         int vec;
 338         u32 *reg;
 339
 340         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 341              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 342                 reg = bitmap + REG_POS(vec);
 343                 if (*reg)
 344                         return fls(*reg) - 1 + vec;
 345         }
 346
 347         return -1;
 348 }
 349
 350 static u8 count_vectors(void *bitmap)
 351 {
 352         int vec;
 353         u32 *reg;
 354         u8 count = 0;
 355
 356         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 357                 reg = bitmap + REG_POS(vec);
 358                 count += hweight32(*reg);
 359         }
 360
 361         return count;
 362 }
 363
 364 void __kvm_apic_update_irr(u32 *pir, void *regs)
 365 {
 366         u32 i, pir_val;
 367
 368         for (i = 0; i <= 7; i++) {
 369                 pir_val = READ_ONCE(pir[i]);
 370                 if (pir_val) {
 371                         pir_val = xchg(&pir[i], 0);
 372                         *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
 373                 }
 374         }
 375 }
 376 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 377
 378 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 379 {
 380         struct kvm_lapic *apic = vcpu->arch.apic;
 381
 382         __kvm_apic_update_irr(pir, apic->regs);
 383
 384         kvm_make_request(KVM_REQ_EVENT, vcpu);
 385 }
 386 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 387
 388 static inline int apic_search_irr(struct kvm_lapic *apic)
 389 {
 390         return find_highest_vector(apic->regs + APIC_IRR);
 391 }
 392
 393 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 394 {
 395         int result;
 396
 397         /*
 398          * Note that irr_pending is just a hint. It will be always
 399          * true with virtual interrupt delivery enabled.
 400          */
 401         if (!apic->irr_pending)
 402                 return -1;
 403
 404         if (apic->vcpu->arch.apicv_active)
 405                 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 406         result = apic_search_irr(apic);
 407         ASSERT(result == -1 || result >= 16);
 408
 409         return result;
 410 }
 411
 412 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 413 {
 414         struct kvm_vcpu *vcpu;
 415
 416         vcpu = apic->vcpu;
 417
 418         if (unlikely(vcpu->arch.apicv_active)) {
 419                 /* try to update RVI */
 420                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 421                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 422         } else {
 423                 apic->irr_pending = false;
 424                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 425                 if (apic_search_irr(apic) != -1)
 426                         apic->irr_pending = true;
 427         }
 428 }
 429
 430 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 431 {
 432         struct kvm_vcpu *vcpu;
 433
 434         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 435                 return;
 436
 437         vcpu = apic->vcpu;
 438
 439         /*
 440          * With APIC virtualization enabled, all caching is disabled
 441          * because the processor can modify ISR under the hood.  Instead
 442          * just set SVI.
 443          */
 444         if (unlikely(vcpu->arch.apicv_active))
 445                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 446         else {
 447                 ++apic->isr_count;
 448                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 449                 /*
 450                  * ISR (in service register) bit is set when injecting an interrupt.
 451                  * The highest vector is injected. Thus the latest bit set matches
 452                  * the highest bit in ISR.
 453                  */
 454                 apic->highest_isr_cache = vec;
 455         }
 456 }
 457
 458 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 459 {
 460         int result;
 461
 462         /*
 463          * Note that isr_count is always 1, and highest_isr_cache
 464          * is always -1, with APIC virtualization enabled.
 465          */
 466         if (!apic->isr_count)
 467                 return -1;
 468         if (likely(apic->highest_isr_cache != -1))
 469                 return apic->highest_isr_cache;
 470
 471         result = find_highest_vector(apic->regs + APIC_ISR);
 472         ASSERT(result == -1 || result >= 16);
 473
 474         return result;
 475 }
 476
 477 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 478 {
 479         struct kvm_vcpu *vcpu;
 480         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 481                 return;
 482
 483         vcpu = apic->vcpu;
 484
 485         /*
 486          * We do get here for APIC virtualization enabled if the guest
 487          * uses the Hyper-V APIC enlightenment.  In this case we may need
 488          * to trigger a new interrupt delivery by writing the SVI field;
 489          * on the other hand isr_count and highest_isr_cache are unused
 490          * and must be left alone.
 491          */
 492         if (unlikely(vcpu->arch.apicv_active))
 493                 kvm_x86_ops->hwapic_isr_update(vcpu,
 494                                                apic_find_highest_isr(apic));
 495         else {
 496                 --apic->isr_count;
 497                 BUG_ON(apic->isr_count < 0);
 498                 apic->highest_isr_cache = -1;
 499         }
 500 }
 501
 502 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 503 {
 504         /* This may race with setting of irr in __apic_accept_irq() and
 505          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 506          * will cause vmexit immediately and the value will be recalculated
 507          * on the next vmentry.
 508          */
 509         return apic_find_highest_irr(vcpu->arch.apic);
 510 }
 511
 512 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 513                              int vector, int level, int trig_mode,
 514                              struct dest_map *dest_map);
 515
 516 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 517                      struct dest_map *dest_map)
 518 {
 519         struct kvm_lapic *apic = vcpu->arch.apic;
 520
 521         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 522                         irq->level, irq->trig_mode, dest_map);
 523 }
 524
 525 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 526 {
 527
 528         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 529                                       sizeof(val));
 530 }
 531
 532 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 533 {
 534
 535         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 536                                       sizeof(*val));
 537 }
 538
 539 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 540 {
 541         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 542 }
 543
 544 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 545 {
 546         u8 val;
 547         if (pv_eoi_get_user(vcpu, &val) < 0)
 548                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 549                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 550         return val & 0x1;
 551 }
 552
 553 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 554 {
 555         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 556                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 557                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 558                 return;
 559         }
 560         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 561 }
 562
 563 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 564 {
 565         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 566                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 567                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 568                 return;
 569         }
 570         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 571 }
 572
 573 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 574 {
 575         int highest_irr = apic_find_highest_irr(apic);
 576         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 577                 return -1;
 578         return highest_irr;
 579 }
 580
 581 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 582 {
 583         u32 tpr, isrv, ppr, old_ppr;
 584         int isr;
 585
 586         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 587         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 588         isr = apic_find_highest_isr(apic);
 589         isrv = (isr != -1) ? isr : 0;
 590
 591         if ((tpr & 0xf0) >= (isrv & 0xf0))
 592                 ppr = tpr & 0xff;
 593         else
 594                 ppr = isrv & 0xf0;
 595
 596         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 597                    apic, ppr, isr, isrv);
 598
 599         *new_ppr = ppr;
 600         if (old_ppr != ppr)
 601                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 602
 603         return ppr < old_ppr;
 604 }
 605
 606 static void apic_update_ppr(struct kvm_lapic *apic)
 607 {
 608         u32 ppr;
 609
 610         if (__apic_update_ppr(apic, &ppr))
 611                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 612 }
 613
 614 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 615 {
 616         apic_update_ppr(vcpu->arch.apic);
 617 }
 618 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 619
 620 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 621 {
 622         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 623         apic_update_ppr(apic);
 624 }
 625
 626 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 627 {
 628         return mda == (apic_x2apic_mode(apic) ?
 629                         X2APIC_BROADCAST : APIC_BROADCAST);
 630 }
 631
 632 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 633 {
 634         if (kvm_apic_broadcast(apic, mda))
 635                 return true;
 636
 637         if (apic_x2apic_mode(apic))
 638                 return mda == kvm_x2apic_id(apic);
 639
 640         /*
 641          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 642          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 643          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 644          * The 0xff condition is needed because writeable xAPIC ID.
 645          */
 646         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 647                 return true;
 648
 649         return mda == kvm_xapic_id(apic);
 650 }
 651
 652 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 653 {
 654         u32 logical_id;
 655
 656         if (kvm_apic_broadcast(apic, mda))
 657                 return true;
 658
 659         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 660
 661         if (apic_x2apic_mode(apic))
 662                 return ((logical_id >> 16) == (mda >> 16))
 663                        && (logical_id & mda & 0xffff) != 0;
 664
 665         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 666
 667         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 668         case APIC_DFR_FLAT:
 669                 return (logical_id & mda) != 0;
 670         case APIC_DFR_CLUSTER:
 671                 return ((logical_id >> 4) == (mda >> 4))
 672                        && (logical_id & mda & 0xf) != 0;
 673         default:
 674                 apic_debug("Bad DFR vcpu %d: %08x\n",
 675                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 676                 return false;
 677         }
 678 }
 679
 680 /* The KVM local APIC implementation has two quirks:
 681  *
 682  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 683  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 684  *    KVM doesn't do that aliasing.
 685  *
 686  *  - in-kernel IOAPIC messages have to be delivered directly to
 687  *    x2APIC, because the kernel does not support interrupt remapping.
 688  *    In order to support broadcast without interrupt remapping, x2APIC
 689  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 690  *    to X2APIC_BROADCAST.
 691  *
 692  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 693  * important when userspace wants to use x2APIC-format MSIs, because
 694  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 695  */
 696 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 697                 struct kvm_lapic *source, struct kvm_lapic *target)
 698 {
 699         bool ipi = source != NULL;
 700
 701         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 702             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 703                 return X2APIC_BROADCAST;
 704
 705         return dest_id;
 706 }
 707
 708 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 709                            int short_hand, unsigned int dest, int dest_mode)
 710 {
 711         struct kvm_lapic *target = vcpu->arch.apic;
 712         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 713
 714         apic_debug("target %p, source %p, dest 0x%x, "
 715                    "dest_mode 0x%x, short_hand 0x%x\n",
 716                    target, source, dest, dest_mode, short_hand);
 717
 718         ASSERT(target);
 719         switch (short_hand) {
 720         case APIC_DEST_NOSHORT:
 721                 if (dest_mode == APIC_DEST_PHYSICAL)
 722                         return kvm_apic_match_physical_addr(target, mda);
 723                 else
 724                         return kvm_apic_match_logical_addr(target, mda);
 725         case APIC_DEST_SELF:
 726                 return target == source;
 727         case APIC_DEST_ALLINC:
 728                 return true;
 729         case APIC_DEST_ALLBUT:
 730                 return target != source;
 731         default:
 732                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 733                            short_hand);
 734                 return false;
 735         }
 736 }
 737 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 738
 739 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 740                        const unsigned long *bitmap, u32 bitmap_size)
 741 {
 742         u32 mod;
 743         int i, idx = -1;
 744
 745         mod = vector % dest_vcpus;
 746
 747         for (i = 0; i <= mod; i++) {
 748                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 749                 BUG_ON(idx == bitmap_size);
 750         }
 751
 752         return idx;
 753 }
 754
 755 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 756 {
 757         if (!kvm->arch.disabled_lapic_found) {
 758                 kvm->arch.disabled_lapic_found = true;
 759                 printk(KERN_INFO
 760                        "Disabled LAPIC found during irq injection\n");
 761         }
 762 }
 763
 764 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 765                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 766 {
 767         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 768                 if ((irq->dest_id == APIC_BROADCAST &&
 769                                 map->mode != KVM_APIC_MODE_X2APIC))
 770                         return true;
 771                 if (irq->dest_id == X2APIC_BROADCAST)
 772                         return true;
 773         } else {
 774                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 775                 if (irq->dest_id == (x2apic_ipi ?
 776                                      X2APIC_BROADCAST : APIC_BROADCAST))
 777                         return true;
 778         }
 779
 780         return false;
 781 }
 782
 783 /* Return true if the interrupt can be handled by using *bitmap as index mask
 784  * for valid destinations in *dst array.
 785  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 786  * Note: we may have zero kvm_lapic destinations when we return true, which
 787  * means that the interrupt should be dropped.  In this case, *bitmap would be
 788  * zero and *dst undefined.
 789  */
 790 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 791                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 792                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 793                 unsigned long *bitmap)
 794 {
 795         int i, lowest;
 796
 797         if (irq->shorthand == APIC_DEST_SELF && src) {
 798                 *dst = src;
 799                 *bitmap = 1;
 800                 return true;
 801         } else if (irq->shorthand)
 802                 return false;
 803
 804         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 805                 return false;
 806
 807         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 808                 if (irq->dest_id > map->max_apic_id) {
 809                         *bitmap = 0;
 810                 } else {
 811                         *dst = &map->phys_map[irq->dest_id];
 812                         *bitmap = 1;
 813                 }
 814                 return true;
 815         }
 816
 817         *bitmap = 0;
 818         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 819                                 (u16 *)bitmap))
 820                 return false;
 821
 822         if (!kvm_lowest_prio_delivery(irq))
 823                 return true;
 824
 825         if (!kvm_vector_hashing_enabled()) {
 826                 lowest = -1;
 827                 for_each_set_bit(i, bitmap, 16) {
 828                         if (!(*dst)[i])
 829                                 continue;
 830                         if (lowest < 0)
 831                                 lowest = i;
 832                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 833                                                 (*dst)[lowest]->vcpu) < 0)
 834                                 lowest = i;
 835                 }
 836         } else {
 837                 if (!*bitmap)
 838                         return true;
 839
 840                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 841                                 bitmap, 16);
 842
 843                 if (!(*dst)[lowest]) {
 844                         kvm_apic_disabled_lapic_found(kvm);
 845                         *bitmap = 0;
 846                         return true;
 847                 }
 848         }
 849
 850         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 851
 852         return true;
 853 }
 854
 855 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 856                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 857 {
 858         struct kvm_apic_map *map;
 859         unsigned long bitmap;
 860         struct kvm_lapic **dst = NULL;
 861         int i;
 862         bool ret;
 863
 864         *r = -1;
 865
 866         if (irq->shorthand == APIC_DEST_SELF) {
 867                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 868                 return true;
 869         }
 870
 871         rcu_read_lock();
 872         map = rcu_dereference(kvm->arch.apic_map);
 873
 874         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 875         if (ret)
 876                 for_each_set_bit(i, &bitmap, 16) {
 877                         if (!dst[i])
 878                                 continue;
 879                         if (*r < 0)
 880                                 *r = 0;
 881                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 882                 }
 883
 884         rcu_read_unlock();
 885         return ret;
 886 }
 887
 888 /*
 889  * This routine tries to handler interrupts in posted mode, here is how
 890  * it deals with different cases:
 891  * - For single-destination interrupts, handle it in posted mode
 892  * - Else if vector hashing is enabled and it is a lowest-priority
 893  *   interrupt, handle it in posted mode and use the following mechanism
 894  *   to find the destinaiton vCPU.
 895  *      1. For lowest-priority interrupts, store all the possible
 896  *         destination vCPUs in an array.
 897  *      2. Use "guest vector % max number of destination vCPUs" to find
 898  *         the right destination vCPU in the array for the lowest-priority
 899  *         interrupt.
 900  * - Otherwise, use remapped mode to inject the interrupt.
 901  */
 902 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 903                         struct kvm_vcpu **dest_vcpu)
 904 {
 905         struct kvm_apic_map *map;
 906         unsigned long bitmap;
 907         struct kvm_lapic **dst = NULL;
 908         bool ret = false;
 909
 910         if (irq->shorthand)
 911                 return false;
 912
 913         rcu_read_lock();
 914         map = rcu_dereference(kvm->arch.apic_map);
 915
 916         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
 917                         hweight16(bitmap) == 1) {
 918                 unsigned long i = find_first_bit(&bitmap, 16);
 919
 920                 if (dst[i]) {
 921                         *dest_vcpu = dst[i]->vcpu;
 922                         ret = true;
 923                 }
 924         }
 925
 926         rcu_read_unlock();
 927         return ret;
 928 }
 929
 930 /*
 931  * Add a pending IRQ into lapic.
 932  * Return 1 if successfully added and 0 if discarded.
 933  */
 934 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 935                              int vector, int level, int trig_mode,
 936                              struct dest_map *dest_map)
 937 {
 938         int result = 0;
 939         struct kvm_vcpu *vcpu = apic->vcpu;
 940
 941         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 942                                   trig_mode, vector);
 943         switch (delivery_mode) {
 944         case APIC_DM_LOWEST:
 945                 vcpu->arch.apic_arb_prio++;
 946         case APIC_DM_FIXED:
 947                 if (unlikely(trig_mode && !level))
 948                         break;
 949
 950                 /* FIXME add logic for vcpu on reset */
 951                 if (unlikely(!apic_enabled(apic)))
 952                         break;
 953
 954                 result = 1;
 955
 956                 if (dest_map) {
 957                         __set_bit(vcpu->vcpu_id, dest_map->map);
 958                         dest_map->vectors[vcpu->vcpu_id] = vector;
 959                 }
 960
 961                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
 962                         if (trig_mode)
 963                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
 964                         else
 965                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
 966                 }
 967
 968                 if (vcpu->arch.apicv_active)
 969                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 970                 else {
 971                         kvm_lapic_set_irr(vector, apic);
 972
 973                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 974                         kvm_vcpu_kick(vcpu);
 975                 }
 976                 break;
 977
 978         case APIC_DM_REMRD:
 979                 result = 1;
 980                 vcpu->arch.pv.pv_unhalted = 1;
 981                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 982                 kvm_vcpu_kick(vcpu);
 983                 break;
 984
 985         case APIC_DM_SMI:
 986                 result = 1;
 987                 kvm_make_request(KVM_REQ_SMI, vcpu);
 988                 kvm_vcpu_kick(vcpu);
 989                 break;
 990
 991         case APIC_DM_NMI:
 992                 result = 1;
 993                 kvm_inject_nmi(vcpu);
 994                 kvm_vcpu_kick(vcpu);
 995                 break;
 996
 997         case APIC_DM_INIT:
 998                 if (!trig_mode || level) {
 999                         result = 1;
1000                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1001                         apic->pending_events = (1UL << KVM_APIC_INIT);
1002                         /* make sure pending_events is visible before sending
1003                          * the request */
1004                         smp_wmb();
1005                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1006                         kvm_vcpu_kick(vcpu);
1007                 } else {
1008                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1009                                    vcpu->vcpu_id);
1010                 }
1011                 break;
1012
1013         case APIC_DM_STARTUP:
1014                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1015                            vcpu->vcpu_id, vector);
1016                 result = 1;
1017                 apic->sipi_vector = vector;
1018                 /* make sure sipi_vector is visible for the receiver */
1019                 smp_wmb();
1020                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1021                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1022                 kvm_vcpu_kick(vcpu);
1023                 break;
1024
1025         case APIC_DM_EXTINT:
1026                 /*
1027                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1028                  * before NMI watchdog was enabled. Already handled by
1029                  * kvm_apic_accept_pic_intr().
1030                  */
1031                 break;
1032
1033         default:
1034                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1035                        delivery_mode);
1036                 break;
1037         }
1038         return result;
1039 }
1040
1041 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1042 {
1043         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1044 }
1045
1046 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1047 {
1048         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1049 }
1050
1051 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1052 {
1053         int trigger_mode;
1054
1055         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1056         if (!kvm_ioapic_handles_vector(apic, vector))
1057                 return;
1058
1059         /* Request a KVM exit to inform the userspace IOAPIC. */
1060         if (irqchip_split(apic->vcpu->kvm)) {
1061                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1062                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1063                 return;
1064         }
1065
1066         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1067                 trigger_mode = IOAPIC_LEVEL_TRIG;
1068         else
1069                 trigger_mode = IOAPIC_EDGE_TRIG;
1070
1071         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1072 }
1073
1074 static int apic_set_eoi(struct kvm_lapic *apic)
1075 {
1076         int vector = apic_find_highest_isr(apic);
1077
1078         trace_kvm_eoi(apic, vector);
1079
1080         /*
1081          * Not every write EOI will has corresponding ISR,
1082          * one example is when Kernel check timer on setup_IO_APIC
1083          */
1084         if (vector == -1)
1085                 return vector;
1086
1087         apic_clear_isr(vector, apic);
1088         apic_update_ppr(apic);
1089
1090         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1091                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1092
1093         kvm_ioapic_send_eoi(apic, vector);
1094         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1095         return vector;
1096 }
1097
1098 /*
1099  * this interface assumes a trap-like exit, which has already finished
1100  * desired side effect including vISR and vPPR update.
1101  */
1102 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1103 {
1104         struct kvm_lapic *apic = vcpu->arch.apic;
1105
1106         trace_kvm_eoi(apic, vector);
1107
1108         kvm_ioapic_send_eoi(apic, vector);
1109         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1110 }
1111 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1112
1113 static void apic_send_ipi(struct kvm_lapic *apic)
1114 {
1115         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1116         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1117         struct kvm_lapic_irq irq;
1118
1119         irq.vector = icr_low & APIC_VECTOR_MASK;
1120         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1121         irq.dest_mode = icr_low & APIC_DEST_MASK;
1122         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1123         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1124         irq.shorthand = icr_low & APIC_SHORT_MASK;
1125         irq.msi_redir_hint = false;
1126         if (apic_x2apic_mode(apic))
1127                 irq.dest_id = icr_high;
1128         else
1129                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1130
1131         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1132
1133         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1134                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1135                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1136                    "msi_redir_hint 0x%x\n",
1137                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1138                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1139                    irq.vector, irq.msi_redir_hint);
1140
1141         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1142 }
1143
1144 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1145 {
1146         ktime_t remaining, now;
1147         s64 ns;
1148         u32 tmcct;
1149
1150         ASSERT(apic != NULL);
1151
1152         /* if initial count is 0, current count should also be 0 */
1153         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1154                 apic->lapic_timer.period == 0)
1155                 return 0;
1156
1157         now = ktime_get();
1158         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1159         if (ktime_to_ns(remaining) < 0)
1160                 remaining = 0;
1161
1162         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1163         tmcct = div64_u64(ns,
1164                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1165
1166         return tmcct;
1167 }
1168
1169 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1170 {
1171         struct kvm_vcpu *vcpu = apic->vcpu;
1172         struct kvm_run *run = vcpu->run;
1173
1174         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1175         run->tpr_access.rip = kvm_rip_read(vcpu);
1176         run->tpr_access.is_write = write;
1177 }
1178
1179 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1180 {
1181         if (apic->vcpu->arch.tpr_access_reporting)
1182                 __report_tpr_access(apic, write);
1183 }
1184
1185 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1186 {
1187         u32 val = 0;
1188
1189         if (offset >= LAPIC_MMIO_LENGTH)
1190                 return 0;
1191
1192         switch (offset) {
1193         case APIC_ARBPRI:
1194                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1195                 break;
1196
1197         case APIC_TMCCT:        /* Timer CCR */
1198                 if (apic_lvtt_tscdeadline(apic))
1199                         return 0;
1200
1201                 val = apic_get_tmcct(apic);
1202                 break;
1203         case APIC_PROCPRI:
1204                 apic_update_ppr(apic);
1205                 val = kvm_lapic_get_reg(apic, offset);
1206                 break;
1207         case APIC_TASKPRI:
1208                 report_tpr_access(apic, false);
1209                 /* fall thru */
1210         default:
1211                 val = kvm_lapic_get_reg(apic, offset);
1212                 break;
1213         }
1214
1215         return val;
1216 }
1217
1218 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1219 {
1220         return container_of(dev, struct kvm_lapic, dev);
1221 }
1222
1223 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1224                 void *data)
1225 {
1226         unsigned char alignment = offset & 0xf;
1227         u32 result;
1228         /* this bitmask has a bit cleared for each reserved register */
1229         static const u64 rmask = 0x43ff01ffffffe70cULL;
1230
1231         if ((alignment + len) > 4) {
1232                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1233                            offset, len);
1234                 return 1;
1235         }
1236
1237         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1238                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1239                            offset);
1240                 return 1;
1241         }
1242
1243         result = __apic_read(apic, offset & ~0xf);
1244
1245         trace_kvm_apic_read(offset, result);
1246
1247         switch (len) {
1248         case 1:
1249         case 2:
1250         case 4:
1251                 memcpy(data, (char *)&result + alignment, len);
1252                 break;
1253         default:
1254                 printk(KERN_ERR "Local APIC read with len = %x, "
1255                        "should be 1,2, or 4 instead\n", len);
1256                 break;
1257         }
1258         return 0;
1259 }
1260 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1261
1262 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1263 {
1264         return kvm_apic_hw_enabled(apic) &&
1265             addr >= apic->base_address &&
1266             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1267 }
1268
1269 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1270                            gpa_t address, int len, void *data)
1271 {
1272         struct kvm_lapic *apic = to_lapic(this);
1273         u32 offset = address - apic->base_address;
1274
1275         if (!apic_mmio_in_range(apic, address))
1276                 return -EOPNOTSUPP;
1277
1278         kvm_lapic_reg_read(apic, offset, len, data);
1279
1280         return 0;
1281 }
1282
1283 static void update_divide_count(struct kvm_lapic *apic)
1284 {
1285         u32 tmp1, tmp2, tdcr;
1286
1287         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1288         tmp1 = tdcr & 0xf;
1289         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1290         apic->divide_count = 0x1 << (tmp2 & 0x7);
1291
1292         apic_debug("timer divide count is 0x%x\n",
1293                                    apic->divide_count);
1294 }
1295
1296 static void apic_update_lvtt(struct kvm_lapic *apic)
1297 {
1298         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1299                         apic->lapic_timer.timer_mode_mask;
1300
1301         if (apic->lapic_timer.timer_mode != timer_mode) {
1302                 apic->lapic_timer.timer_mode = timer_mode;
1303                 hrtimer_cancel(&apic->lapic_timer.timer);
1304         }
1305 }
1306
1307 static void apic_timer_expired(struct kvm_lapic *apic)
1308 {
1309         struct kvm_vcpu *vcpu = apic->vcpu;
1310         struct swait_queue_head *q = &vcpu->wq;
1311         struct kvm_timer *ktimer = &apic->lapic_timer;
1312
1313         if (atomic_read(&apic->lapic_timer.pending))
1314                 return;
1315
1316         atomic_inc(&apic->lapic_timer.pending);
1317         kvm_set_pending_timer(vcpu);
1318
1319         if (swait_active(q))
1320                 swake_up(q);
1321
1322         if (apic_lvtt_tscdeadline(apic))
1323                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1324 }
1325
1326 /*
1327  * On APICv, this test will cause a busy wait
1328  * during a higher-priority task.
1329  */
1330
1331 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1332 {
1333         struct kvm_lapic *apic = vcpu->arch.apic;
1334         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1335
1336         if (kvm_apic_hw_enabled(apic)) {
1337                 int vec = reg & APIC_VECTOR_MASK;
1338                 void *bitmap = apic->regs + APIC_ISR;
1339
1340                 if (vcpu->arch.apicv_active)
1341                         bitmap = apic->regs + APIC_IRR;
1342
1343                 if (apic_test_vector(vec, bitmap))
1344                         return true;
1345         }
1346         return false;
1347 }
1348
1349 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1350 {
1351         struct kvm_lapic *apic = vcpu->arch.apic;
1352         u64 guest_tsc, tsc_deadline;
1353
1354         if (!lapic_in_kernel(vcpu))
1355                 return;
1356
1357         if (apic->lapic_timer.expired_tscdeadline == 0)
1358                 return;
1359
1360         if (!lapic_timer_int_injected(vcpu))
1361                 return;
1362
1363         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1364         apic->lapic_timer.expired_tscdeadline = 0;
1365         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1366         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1367
1368         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1369         if (guest_tsc < tsc_deadline)
1370                 __delay(min(tsc_deadline - guest_tsc,
1371                         nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1372 }
1373
1374 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1375 {
1376         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1377         u64 ns = 0;
1378         ktime_t expire;
1379         struct kvm_vcpu *vcpu = apic->vcpu;
1380         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1381         unsigned long flags;
1382         ktime_t now;
1383
1384         if (unlikely(!tscdeadline || !this_tsc_khz))
1385                 return;
1386
1387         local_irq_save(flags);
1388
1389         now = ktime_get();
1390         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1391         if (likely(tscdeadline > guest_tsc)) {
1392                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1393                 do_div(ns, this_tsc_khz);
1394                 expire = ktime_add_ns(now, ns);
1395                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1396                 hrtimer_start(&apic->lapic_timer.timer,
1397                                 expire, HRTIMER_MODE_ABS_PINNED);
1398         } else
1399                 apic_timer_expired(apic);
1400
1401         local_irq_restore(flags);
1402 }
1403
1404 static void start_sw_period(struct kvm_lapic *apic)
1405 {
1406         if (!apic->lapic_timer.period)
1407                 return;
1408
1409         if (apic_lvtt_oneshot(apic) &&
1410             ktime_after(ktime_get(),
1411                         apic->lapic_timer.target_expiration)) {
1412                 apic_timer_expired(apic);
1413                 return;
1414         }
1415
1416         hrtimer_start(&apic->lapic_timer.timer,
1417                 apic->lapic_timer.target_expiration,
1418                 HRTIMER_MODE_ABS_PINNED);
1419 }
1420
1421 static bool set_target_expiration(struct kvm_lapic *apic)
1422 {
1423         ktime_t now;
1424         u64 tscl = rdtsc();
1425
1426         now = ktime_get();
1427         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1428                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1429
1430         if (!apic->lapic_timer.period)
1431                 return false;
1432
1433         /*
1434          * Do not allow the guest to program periodic timers with small
1435          * interval, since the hrtimers are not throttled by the host
1436          * scheduler.
1437          */
1438         if (apic_lvtt_period(apic)) {
1439                 s64 min_period = min_timer_period_us * 1000LL;
1440
1441                 if (apic->lapic_timer.period < min_period) {
1442                         pr_info_ratelimited(
1443                             "kvm: vcpu %i: requested %lld ns "
1444                             "lapic timer period limited to %lld ns\n",
1445                             apic->vcpu->vcpu_id,
1446                             apic->lapic_timer.period, min_period);
1447                         apic->lapic_timer.period = min_period;
1448                 }
1449         }
1450
1451         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1452                    PRIx64 ", "
1453                    "timer initial count 0x%x, period %lldns, "
1454                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1455                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1456                    kvm_lapic_get_reg(apic, APIC_TMICT),
1457                    apic->lapic_timer.period,
1458                    ktime_to_ns(ktime_add_ns(now,
1459                                 apic->lapic_timer.period)));
1460
1461         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1462                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1463         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1464
1465         return true;
1466 }
1467
1468 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1469 {
1470         apic->lapic_timer.tscdeadline +=
1471                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1472         apic->lapic_timer.target_expiration =
1473                 ktime_add_ns(apic->lapic_timer.target_expiration,
1474                                 apic->lapic_timer.period);
1475 }
1476
1477 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1478 {
1479         if (!lapic_in_kernel(vcpu))
1480                 return false;
1481
1482         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1483 }
1484 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1485
1486 static void cancel_hv_timer(struct kvm_lapic *apic)
1487 {
1488         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1489         apic->lapic_timer.hv_timer_in_use = false;
1490 }
1491
1492 static bool start_hv_timer(struct kvm_lapic *apic)
1493 {
1494         u64 tscdeadline = apic->lapic_timer.tscdeadline;
1495
1496         if ((atomic_read(&apic->lapic_timer.pending) &&
1497                 !apic_lvtt_period(apic)) ||
1498                 kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) {
1499                 if (apic->lapic_timer.hv_timer_in_use)
1500                         cancel_hv_timer(apic);
1501         } else {
1502                 apic->lapic_timer.hv_timer_in_use = true;
1503                 hrtimer_cancel(&apic->lapic_timer.timer);
1504
1505                 /* In case the sw timer triggered in the window */
1506                 if (atomic_read(&apic->lapic_timer.pending) &&
1507                         !apic_lvtt_period(apic))
1508                         cancel_hv_timer(apic);
1509         }
1510         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id,
1511                         apic->lapic_timer.hv_timer_in_use);
1512         return apic->lapic_timer.hv_timer_in_use;
1513 }
1514
1515 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1516 {
1517         struct kvm_lapic *apic = vcpu->arch.apic;
1518
1519         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1520         WARN_ON(swait_active(&vcpu->wq));
1521         cancel_hv_timer(apic);
1522         apic_timer_expired(apic);
1523
1524         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1525                 advance_periodic_target_expiration(apic);
1526                 if (!start_hv_timer(apic))
1527                         start_sw_period(apic);
1528         }
1529 }
1530 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1531
1532 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1533 {
1534         struct kvm_lapic *apic = vcpu->arch.apic;
1535
1536         WARN_ON(apic->lapic_timer.hv_timer_in_use);
1537
1538         start_hv_timer(apic);
1539 }
1540 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1541
1542 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1543 {
1544         struct kvm_lapic *apic = vcpu->arch.apic;
1545
1546         /* Possibly the TSC deadline timer is not enabled yet */
1547         if (!apic->lapic_timer.hv_timer_in_use)
1548                 return;
1549
1550         cancel_hv_timer(apic);
1551
1552         if (atomic_read(&apic->lapic_timer.pending))
1553                 return;
1554
1555         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1556                 start_sw_period(apic);
1557         else if (apic_lvtt_tscdeadline(apic))
1558                 start_sw_tscdeadline(apic);
1559 }
1560 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1561
1562 static void start_apic_timer(struct kvm_lapic *apic)
1563 {
1564         atomic_set(&apic->lapic_timer.pending, 0);
1565
1566         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1567                 if (set_target_expiration(apic) &&
1568                         !(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1569                         start_sw_period(apic);
1570         } else if (apic_lvtt_tscdeadline(apic)) {
1571                 if (!(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1572                         start_sw_tscdeadline(apic);
1573         }
1574 }
1575
1576 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1577 {
1578         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1579
1580         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1581                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1582                 if (lvt0_in_nmi_mode) {
1583                         apic_debug("Receive NMI setting on APIC_LVT0 "
1584                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1585                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1586                 } else
1587                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1588         }
1589 }
1590
1591 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1592 {
1593         int ret = 0;
1594
1595         trace_kvm_apic_write(reg, val);
1596
1597         switch (reg) {
1598         case APIC_ID:           /* Local APIC ID */
1599                 if (!apic_x2apic_mode(apic))
1600                         kvm_apic_set_xapic_id(apic, val >> 24);
1601                 else
1602                         ret = 1;
1603                 break;
1604
1605         case APIC_TASKPRI:
1606                 report_tpr_access(apic, true);
1607                 apic_set_tpr(apic, val & 0xff);
1608                 break;
1609
1610         case APIC_EOI:
1611                 apic_set_eoi(apic);
1612                 break;
1613
1614         case APIC_LDR:
1615                 if (!apic_x2apic_mode(apic))
1616                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1617                 else
1618                         ret = 1;
1619                 break;
1620
1621         case APIC_DFR:
1622                 if (!apic_x2apic_mode(apic)) {
1623                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1624                         recalculate_apic_map(apic->vcpu->kvm);
1625                 } else
1626                         ret = 1;
1627                 break;
1628
1629         case APIC_SPIV: {
1630                 u32 mask = 0x3ff;
1631                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1632                         mask |= APIC_SPIV_DIRECTED_EOI;
1633                 apic_set_spiv(apic, val & mask);
1634                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1635                         int i;
1636                         u32 lvt_val;
1637
1638                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1639                                 lvt_val = kvm_lapic_get_reg(apic,
1640                                                        APIC_LVTT + 0x10 * i);
1641                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1642                                              lvt_val | APIC_LVT_MASKED);
1643                         }
1644                         apic_update_lvtt(apic);
1645                         atomic_set(&apic->lapic_timer.pending, 0);
1646
1647                 }
1648                 break;
1649         }
1650         case APIC_ICR:
1651                 /* No delay here, so we always clear the pending bit */
1652                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1653                 apic_send_ipi(apic);
1654                 break;
1655
1656         case APIC_ICR2:
1657                 if (!apic_x2apic_mode(apic))
1658                         val &= 0xff000000;
1659                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1660                 break;
1661
1662         case APIC_LVT0:
1663                 apic_manage_nmi_watchdog(apic, val);
1664         case APIC_LVTTHMR:
1665         case APIC_LVTPC:
1666         case APIC_LVT1:
1667         case APIC_LVTERR:
1668                 /* TODO: Check vector */
1669                 if (!kvm_apic_sw_enabled(apic))
1670                         val |= APIC_LVT_MASKED;
1671
1672                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1673                 kvm_lapic_set_reg(apic, reg, val);
1674
1675                 break;
1676
1677         case APIC_LVTT:
1678                 if (!kvm_apic_sw_enabled(apic))
1679                         val |= APIC_LVT_MASKED;
1680                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1681                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1682                 apic_update_lvtt(apic);
1683                 break;
1684
1685         case APIC_TMICT:
1686                 if (apic_lvtt_tscdeadline(apic))
1687                         break;
1688
1689                 hrtimer_cancel(&apic->lapic_timer.timer);
1690                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1691                 start_apic_timer(apic);
1692                 break;
1693
1694         case APIC_TDCR:
1695                 if (val & 4)
1696                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1697                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1698                 update_divide_count(apic);
1699                 break;
1700
1701         case APIC_ESR:
1702                 if (apic_x2apic_mode(apic) && val != 0) {
1703                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1704                         ret = 1;
1705                 }
1706                 break;
1707
1708         case APIC_SELF_IPI:
1709                 if (apic_x2apic_mode(apic)) {
1710                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1711                 } else
1712                         ret = 1;
1713                 break;
1714         default:
1715                 ret = 1;
1716                 break;
1717         }
1718         if (ret)
1719                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1720         return ret;
1721 }
1722 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1723
1724 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1725                             gpa_t address, int len, const void *data)
1726 {
1727         struct kvm_lapic *apic = to_lapic(this);
1728         unsigned int offset = address - apic->base_address;
1729         u32 val;
1730
1731         if (!apic_mmio_in_range(apic, address))
1732                 return -EOPNOTSUPP;
1733
1734         /*
1735          * APIC register must be aligned on 128-bits boundary.
1736          * 32/64/128 bits registers must be accessed thru 32 bits.
1737          * Refer SDM 8.4.1
1738          */
1739         if (len != 4 || (offset & 0xf)) {
1740                 /* Don't shout loud, $infamous_os would cause only noise. */
1741                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1742                 return 0;
1743         }
1744
1745         val = *(u32*)data;
1746
1747         /* too common printing */
1748         if (offset != APIC_EOI)
1749                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1750                            "0x%x\n", __func__, offset, len, val);
1751
1752         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1753
1754         return 0;
1755 }
1756
1757 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1758 {
1759         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1760 }
1761 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1762
1763 /* emulate APIC access in a trap manner */
1764 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1765 {
1766         u32 val = 0;
1767
1768         /* hw has done the conditional check and inst decode */
1769         offset &= 0xff0;
1770
1771         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1772
1773         /* TODO: optimize to just emulate side effect w/o one more write */
1774         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1775 }
1776 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1777
1778 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1779 {
1780         struct kvm_lapic *apic = vcpu->arch.apic;
1781
1782         if (!vcpu->arch.apic)
1783                 return;
1784
1785         hrtimer_cancel(&apic->lapic_timer.timer);
1786
1787         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1788                 static_key_slow_dec_deferred(&apic_hw_disabled);
1789
1790         if (!apic->sw_enabled)
1791                 static_key_slow_dec_deferred(&apic_sw_disabled);
1792
1793         if (apic->regs)
1794                 free_page((unsigned long)apic->regs);
1795
1796         kfree(apic);
1797 }
1798
1799 /*
1800  *----------------------------------------------------------------------
1801  * LAPIC interface
1802  *----------------------------------------------------------------------
1803  */
1804 u64 kvm_get_lapic_target_expiration_tsc(struct kvm_vcpu *vcpu)
1805 {
1806         struct kvm_lapic *apic = vcpu->arch.apic;
1807
1808         if (!lapic_in_kernel(vcpu))
1809                 return 0;
1810
1811         return apic->lapic_timer.tscdeadline;
1812 }
1813
1814 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1815 {
1816         struct kvm_lapic *apic = vcpu->arch.apic;
1817
1818         if (!lapic_in_kernel(vcpu) ||
1819                 !apic_lvtt_tscdeadline(apic))
1820                 return 0;
1821
1822         return apic->lapic_timer.tscdeadline;
1823 }
1824
1825 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1826 {
1827         struct kvm_lapic *apic = vcpu->arch.apic;
1828
1829         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1830                         apic_lvtt_period(apic))
1831                 return;
1832
1833         hrtimer_cancel(&apic->lapic_timer.timer);
1834         apic->lapic_timer.tscdeadline = data;
1835         start_apic_timer(apic);
1836 }
1837
1838 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1839 {
1840         struct kvm_lapic *apic = vcpu->arch.apic;
1841
1842         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1843                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1844 }
1845
1846 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1847 {
1848         u64 tpr;
1849
1850         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1851
1852         return (tpr & 0xf0) >> 4;
1853 }
1854
1855 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1856 {
1857         u64 old_value = vcpu->arch.apic_base;
1858         struct kvm_lapic *apic = vcpu->arch.apic;
1859
1860         if (!apic)
1861                 value |= MSR_IA32_APICBASE_BSP;
1862
1863         vcpu->arch.apic_base = value;
1864
1865         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1866                 kvm_update_cpuid(vcpu);
1867
1868         if (!apic)
1869                 return;
1870
1871         /* update jump label if enable bit changes */
1872         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1873                 if (value & MSR_IA32_APICBASE_ENABLE) {
1874                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1875                         static_key_slow_dec_deferred(&apic_hw_disabled);
1876                 } else {
1877                         static_key_slow_inc(&apic_hw_disabled.key);
1878                         recalculate_apic_map(vcpu->kvm);
1879                 }
1880         }
1881
1882         if ((old_value ^ value) & X2APIC_ENABLE) {
1883                 if (value & X2APIC_ENABLE) {
1884                         kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1885                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1886                 } else
1887                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1888         }
1889
1890         apic->base_address = apic->vcpu->arch.apic_base &
1891                              MSR_IA32_APICBASE_BASE;
1892
1893         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1894              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1895                 pr_warn_once("APIC base relocation is unsupported by KVM");
1896
1897         /* with FSB delivery interrupt, we can restart APIC functionality */
1898         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1899                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1900
1901 }
1902
1903 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1904 {
1905         struct kvm_lapic *apic;
1906         int i;
1907
1908         apic_debug("%s\n", __func__);
1909
1910         ASSERT(vcpu);
1911         apic = vcpu->arch.apic;
1912         ASSERT(apic != NULL);
1913
1914         /* Stop the timer in case it's a reset to an active apic */
1915         hrtimer_cancel(&apic->lapic_timer.timer);
1916
1917         if (!init_event) {
1918                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
1919                                          MSR_IA32_APICBASE_ENABLE);
1920                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1921         }
1922         kvm_apic_set_version(apic->vcpu);
1923
1924         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1925                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1926         apic_update_lvtt(apic);
1927         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1928                 kvm_lapic_set_reg(apic, APIC_LVT0,
1929                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1930         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1931
1932         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
1933         apic_set_spiv(apic, 0xff);
1934         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
1935         if (!apic_x2apic_mode(apic))
1936                 kvm_apic_set_ldr(apic, 0);
1937         kvm_lapic_set_reg(apic, APIC_ESR, 0);
1938         kvm_lapic_set_reg(apic, APIC_ICR, 0);
1939         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1940         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1941         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1942         for (i = 0; i < 8; i++) {
1943                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1944                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1945                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1946         }
1947         apic->irr_pending = vcpu->arch.apicv_active;
1948         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1949         apic->highest_isr_cache = -1;
1950         update_divide_count(apic);
1951         atomic_set(&apic->lapic_timer.pending, 0);
1952         if (kvm_vcpu_is_bsp(vcpu))
1953                 kvm_lapic_set_base(vcpu,
1954                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1955         vcpu->arch.pv_eoi.msr_val = 0;
1956         apic_update_ppr(apic);
1957
1958         vcpu->arch.apic_arb_prio = 0;
1959         vcpu->arch.apic_attention = 0;
1960
1961         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
1962                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1963                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
1964                    vcpu->arch.apic_base, apic->base_address);
1965 }
1966
1967 /*
1968  *----------------------------------------------------------------------
1969  * timer interface
1970  *----------------------------------------------------------------------
1971  */
1972
1973 static bool lapic_is_periodic(struct kvm_lapic *apic)
1974 {
1975         return apic_lvtt_period(apic);
1976 }
1977
1978 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1979 {
1980         struct kvm_lapic *apic = vcpu->arch.apic;
1981
1982         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1983                 return atomic_read(&apic->lapic_timer.pending);
1984
1985         return 0;
1986 }
1987
1988 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1989 {
1990         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
1991         int vector, mode, trig_mode;
1992
1993         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1994                 vector = reg & APIC_VECTOR_MASK;
1995                 mode = reg & APIC_MODE_MASK;
1996                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1997                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1998                                         NULL);
1999         }
2000         return 0;
2001 }
2002
2003 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2004 {
2005         struct kvm_lapic *apic = vcpu->arch.apic;
2006
2007         if (apic)
2008                 kvm_apic_local_deliver(apic, APIC_LVT0);
2009 }
2010
2011 static const struct kvm_io_device_ops apic_mmio_ops = {
2012         .read     = apic_mmio_read,
2013         .write    = apic_mmio_write,
2014 };
2015
2016 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2017 {
2018         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2019         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2020
2021         apic_timer_expired(apic);
2022
2023         if (lapic_is_periodic(apic)) {
2024                 advance_periodic_target_expiration(apic);
2025                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2026                 return HRTIMER_RESTART;
2027         } else
2028                 return HRTIMER_NORESTART;
2029 }
2030
2031 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2032 {
2033         struct kvm_lapic *apic;
2034
2035         ASSERT(vcpu != NULL);
2036         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2037
2038         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2039         if (!apic)
2040                 goto nomem;
2041
2042         vcpu->arch.apic = apic;
2043
2044         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2045         if (!apic->regs) {
2046                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2047                        vcpu->vcpu_id);
2048                 goto nomem_free_apic;
2049         }
2050         apic->vcpu = vcpu;
2051
2052         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2053                      HRTIMER_MODE_ABS_PINNED);
2054         apic->lapic_timer.timer.function = apic_timer_fn;
2055
2056         /*
2057          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2058          * thinking that APIC satet has changed.
2059          */
2060         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2061         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2062         kvm_lapic_reset(vcpu, false);
2063         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2064
2065         return 0;
2066 nomem_free_apic:
2067         kfree(apic);
2068 nomem:
2069         return -ENOMEM;
2070 }
2071
2072 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2073 {
2074         struct kvm_lapic *apic = vcpu->arch.apic;
2075         u32 ppr;
2076
2077         if (!apic_enabled(apic))
2078                 return -1;
2079
2080         __apic_update_ppr(apic, &ppr);
2081         return apic_has_interrupt_for_ppr(apic, ppr);
2082 }
2083
2084 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2085 {
2086         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2087         int r = 0;
2088
2089         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2090                 r = 1;
2091         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2092             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2093                 r = 1;
2094         return r;
2095 }
2096
2097 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2098 {
2099         struct kvm_lapic *apic = vcpu->arch.apic;
2100
2101         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2102                 kvm_apic_local_deliver(apic, APIC_LVTT);
2103                 if (apic_lvtt_tscdeadline(apic))
2104                         apic->lapic_timer.tscdeadline = 0;
2105                 if (apic_lvtt_oneshot(apic)) {
2106                         apic->lapic_timer.tscdeadline = 0;
2107                         apic->lapic_timer.target_expiration = 0;
2108                 }
2109                 atomic_set(&apic->lapic_timer.pending, 0);
2110         }
2111 }
2112
2113 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2114 {
2115         int vector = kvm_apic_has_interrupt(vcpu);
2116         struct kvm_lapic *apic = vcpu->arch.apic;
2117
2118         if (vector == -1)
2119                 return -1;
2120
2121         /*
2122          * We get here even with APIC virtualization enabled, if doing
2123          * nested virtualization and L1 runs with the "acknowledge interrupt
2124          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2125          * because the process would deliver it through the IDT.
2126          */
2127
2128         apic_set_isr(vector, apic);
2129         apic_update_ppr(apic);
2130         apic_clear_irr(vector, apic);
2131
2132         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2133                 apic_clear_isr(vector, apic);
2134                 apic_update_ppr(apic);
2135         }
2136
2137         return vector;
2138 }
2139
2140 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2141                 struct kvm_lapic_state *s, bool set)
2142 {
2143         if (apic_x2apic_mode(vcpu->arch.apic)) {
2144                 u32 *id = (u32 *)(s->regs + APIC_ID);
2145
2146                 if (vcpu->kvm->arch.x2apic_format) {
2147                         if (*id != vcpu->vcpu_id)
2148                                 return -EINVAL;
2149                 } else {
2150                         if (set)
2151                                 *id >>= 24;
2152                         else
2153                                 *id <<= 24;
2154                 }
2155         }
2156
2157         return 0;
2158 }
2159
2160 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2161 {
2162         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2163         return kvm_apic_state_fixup(vcpu, s, false);
2164 }
2165
2166 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2167 {
2168         struct kvm_lapic *apic = vcpu->arch.apic;
2169         int r;
2170
2171
2172         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2173         /* set SPIV separately to get count of SW disabled APICs right */
2174         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2175
2176         r = kvm_apic_state_fixup(vcpu, s, true);
2177         if (r)
2178                 return r;
2179         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2180
2181         recalculate_apic_map(vcpu->kvm);
2182         kvm_apic_set_version(vcpu);
2183
2184         apic_update_ppr(apic);
2185         hrtimer_cancel(&apic->lapic_timer.timer);
2186         apic_update_lvtt(apic);
2187         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2188         update_divide_count(apic);
2189         start_apic_timer(apic);
2190         apic->irr_pending = true;
2191         apic->isr_count = vcpu->arch.apicv_active ?
2192                                 1 : count_vectors(apic->regs + APIC_ISR);
2193         apic->highest_isr_cache = -1;
2194         if (vcpu->arch.apicv_active) {
2195                 if (kvm_x86_ops->apicv_post_state_restore)
2196                         kvm_x86_ops->apicv_post_state_restore(vcpu);
2197                 kvm_x86_ops->hwapic_irr_update(vcpu,
2198                                 apic_find_highest_irr(apic));
2199                 kvm_x86_ops->hwapic_isr_update(vcpu,
2200                                 apic_find_highest_isr(apic));
2201         }
2202         kvm_make_request(KVM_REQ_EVENT, vcpu);
2203         if (ioapic_in_kernel(vcpu->kvm))
2204                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2205
2206         vcpu->arch.apic_arb_prio = 0;
2207
2208         return 0;
2209 }
2210
2211 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2212 {
2213         struct hrtimer *timer;
2214
2215         if (!lapic_in_kernel(vcpu))
2216                 return;
2217
2218         timer = &vcpu->arch.apic->lapic_timer.timer;
2219         if (hrtimer_cancel(timer))
2220                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2221 }
2222
2223 /*
2224  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2225  *
2226  * Detect whether guest triggered PV EOI since the
2227  * last entry. If yes, set EOI on guests's behalf.
2228  * Clear PV EOI in guest memory in any case.
2229  */
2230 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2231                                         struct kvm_lapic *apic)
2232 {
2233         bool pending;
2234         int vector;
2235         /*
2236          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2237          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2238          *
2239          * KVM_APIC_PV_EOI_PENDING is unset:
2240          *      -> host disabled PV EOI.
2241          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2242          *      -> host enabled PV EOI, guest did not execute EOI yet.
2243          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2244          *      -> host enabled PV EOI, guest executed EOI.
2245          */
2246         BUG_ON(!pv_eoi_enabled(vcpu));
2247         pending = pv_eoi_get_pending(vcpu);
2248         /*
2249          * Clear pending bit in any case: it will be set again on vmentry.
2250          * While this might not be ideal from performance point of view,
2251          * this makes sure pv eoi is only enabled when we know it's safe.
2252          */
2253         pv_eoi_clr_pending(vcpu);
2254         if (pending)
2255                 return;
2256         vector = apic_set_eoi(apic);
2257         trace_kvm_pv_eoi(apic, vector);
2258 }
2259
2260 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2261 {
2262         u32 data;
2263
2264         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2265                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2266
2267         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2268                 return;
2269
2270         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2271                                   sizeof(u32)))
2272                 return;
2273
2274         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2275 }
2276
2277 /*
2278  * apic_sync_pv_eoi_to_guest - called before vmentry
2279  *
2280  * Detect whether it's safe to enable PV EOI and
2281  * if yes do so.
2282  */
2283 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2284                                         struct kvm_lapic *apic)
2285 {
2286         if (!pv_eoi_enabled(vcpu) ||
2287             /* IRR set or many bits in ISR: could be nested. */
2288             apic->irr_pending ||
2289             /* Cache not set: could be safe but we don't bother. */
2290             apic->highest_isr_cache == -1 ||
2291             /* Need EOI to update ioapic. */
2292             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2293                 /*
2294                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2295                  * so we need not do anything here.
2296                  */
2297                 return;
2298         }
2299
2300         pv_eoi_set_pending(apic->vcpu);
2301 }
2302
2303 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2304 {
2305         u32 data, tpr;
2306         int max_irr, max_isr;
2307         struct kvm_lapic *apic = vcpu->arch.apic;
2308
2309         apic_sync_pv_eoi_to_guest(vcpu, apic);
2310
2311         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2312                 return;
2313
2314         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2315         max_irr = apic_find_highest_irr(apic);
2316         if (max_irr < 0)
2317                 max_irr = 0;
2318         max_isr = apic_find_highest_isr(apic);
2319         if (max_isr < 0)
2320                 max_isr = 0;
2321         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2322
2323         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2324                                 sizeof(u32));
2325 }
2326
2327 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2328 {
2329         if (vapic_addr) {
2330                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2331                                         &vcpu->arch.apic->vapic_cache,
2332                                         vapic_addr, sizeof(u32)))
2333                         return -EINVAL;
2334                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2335         } else {
2336                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2337         }
2338
2339         vcpu->arch.apic->vapic_addr = vapic_addr;
2340         return 0;
2341 }
2342
2343 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2344 {
2345         struct kvm_lapic *apic = vcpu->arch.apic;
2346         u32 reg = (msr - APIC_BASE_MSR) << 4;
2347
2348         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2349                 return 1;
2350
2351         if (reg == APIC_ICR2)
2352                 return 1;
2353
2354         /* if this is ICR write vector before command */
2355         if (reg == APIC_ICR)
2356                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2357         return kvm_lapic_reg_write(apic, reg, (u32)data);
2358 }
2359
2360 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2361 {
2362         struct kvm_lapic *apic = vcpu->arch.apic;
2363         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2364
2365         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2366                 return 1;
2367
2368         if (reg == APIC_DFR || reg == APIC_ICR2) {
2369                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2370                            reg);
2371                 return 1;
2372         }
2373
2374         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2375                 return 1;
2376         if (reg == APIC_ICR)
2377                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2378
2379         *data = (((u64)high) << 32) | low;
2380
2381         return 0;
2382 }
2383
2384 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2385 {
2386         struct kvm_lapic *apic = vcpu->arch.apic;
2387
2388         if (!lapic_in_kernel(vcpu))
2389                 return 1;
2390
2391         /* if this is ICR write vector before command */
2392         if (reg == APIC_ICR)
2393                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2394         return kvm_lapic_reg_write(apic, reg, (u32)data);
2395 }
2396
2397 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2398 {
2399         struct kvm_lapic *apic = vcpu->arch.apic;
2400         u32 low, high = 0;
2401
2402         if (!lapic_in_kernel(vcpu))
2403                 return 1;
2404
2405         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2406                 return 1;
2407         if (reg == APIC_ICR)
2408                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2409
2410         *data = (((u64)high) << 32) | low;
2411
2412         return 0;
2413 }
2414
2415 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2416 {
2417         u64 addr = data & ~KVM_MSR_ENABLED;
2418         if (!IS_ALIGNED(addr, 4))
2419                 return 1;
2420
2421         vcpu->arch.pv_eoi.msr_val = data;
2422         if (!pv_eoi_enabled(vcpu))
2423                 return 0;
2424         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2425                                          addr, sizeof(u8));
2426 }
2427
2428 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2429 {
2430         struct kvm_lapic *apic = vcpu->arch.apic;
2431         u8 sipi_vector;
2432         unsigned long pe;
2433
2434         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2435                 return;
2436
2437         /*
2438          * INITs are latched while in SMM.  Because an SMM CPU cannot
2439          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2440          * and delay processing of INIT until the next RSM.
2441          */
2442         if (is_smm(vcpu)) {
2443                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2444                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2445                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2446                 return;
2447         }
2448
2449         pe = xchg(&apic->pending_events, 0);
2450         if (test_bit(KVM_APIC_INIT, &pe)) {
2451                 kvm_lapic_reset(vcpu, true);
2452                 kvm_vcpu_reset(vcpu, true);
2453                 if (kvm_vcpu_is_bsp(apic->vcpu))
2454                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2455                 else
2456                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2457         }
2458         if (test_bit(KVM_APIC_SIPI, &pe) &&
2459             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2460                 /* evaluate pending_events before reading the vector */
2461                 smp_rmb();
2462                 sipi_vector = apic->sipi_vector;
2463                 apic_debug("vcpu %d received sipi with vector # %x\n",
2464                          vcpu->vcpu_id, sipi_vector);
2465                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2466                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2467         }
2468 }
2469
2470 void kvm_lapic_init(void)
2471 {
2472         /* do not patch jump label more than once per second */
2473         jump_label_rate_limit(&apic_hw_disabled, HZ);
2474         jump_label_rate_limit(&apic_sw_disabled, HZ);
2475 }