3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
20 #include <linux/kvm_host.h>
21 #include <linux/kvm.h>
23 #include <linux/highmem.h>
24 #include <linux/smp.h>
25 #include <linux/hrtimer.h>
27 #include <linux/module.h>
28 #include <linux/math64.h>
29 #include <asm/processor.h>
32 #include <asm/current.h>
33 #include <asm/apicdef.h>
34 #include <asm/atomic.h>
35 #include "kvm_cache_regs.h"
39 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
41 #define mod_64(x, y) ((x) % (y))
49 #define APIC_BUS_CYCLE_NS 1
51 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
52 #define apic_debug(fmt, arg...)
54 #define APIC_LVT_NUM 6
55 /* 14 is the version for Xeon and Pentium 8.4.8*/
56 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
57 #define LAPIC_MMIO_LENGTH (1 << 12)
58 /* followed define is not in apicdef.h */
59 #define APIC_SHORT_MASK 0xc0000
60 #define APIC_DEST_NOSHORT 0x0
61 #define APIC_DEST_MASK 0x800
62 #define MAX_APIC_VECTOR 256
64 #define VEC_POS(v) ((v) & (32 - 1))
65 #define REG_POS(v) (((v) >> 5) << 4)
67 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
69 return *((u32 *) (apic->regs + reg_off));
72 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
74 *((u32 *) (apic->regs + reg_off)) = val;
77 static inline int apic_test_and_set_vector(int vec, void *bitmap)
79 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
84 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87 static inline void apic_set_vector(int vec, void *bitmap)
89 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92 static inline void apic_clear_vector(int vec, void *bitmap)
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97 static inline int apic_hw_enabled(struct kvm_lapic *apic)
99 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
102 static inline int apic_sw_enabled(struct kvm_lapic *apic)
104 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
107 static inline int apic_enabled(struct kvm_lapic *apic)
109 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
113 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
116 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
117 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
119 static inline int kvm_apic_id(struct kvm_lapic *apic)
121 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
124 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
126 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
129 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
131 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
134 static inline int apic_lvtt_period(struct kvm_lapic *apic)
136 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
139 static inline int apic_lvt_nmi_mode(u32 lvt_val)
141 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
144 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
145 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
146 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
147 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
148 LINT_MASK, LINT_MASK, /* LVT0-1 */
149 LVT_MASK /* LVTERR */
152 static int find_highest_vector(void *bitmap)
155 int word_offset = MAX_APIC_VECTOR >> 5;
157 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
160 if (likely(!word_offset && !word[0]))
163 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
166 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
168 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
171 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
173 apic_clear_vector(vec, apic->regs + APIC_IRR);
176 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
180 result = find_highest_vector(apic->regs + APIC_IRR);
181 ASSERT(result == -1 || result >= 16);
186 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
188 struct kvm_lapic *apic = vcpu->arch.apic;
193 highest_irr = apic_find_highest_irr(apic);
198 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
199 int vector, int level, int trig_mode);
201 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
203 struct kvm_lapic *apic = vcpu->arch.apic;
205 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
206 irq->level, irq->trig_mode);
209 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
213 result = find_highest_vector(apic->regs + APIC_ISR);
214 ASSERT(result == -1 || result >= 16);
219 static void apic_update_ppr(struct kvm_lapic *apic)
224 tpr = apic_get_reg(apic, APIC_TASKPRI);
225 isr = apic_find_highest_isr(apic);
226 isrv = (isr != -1) ? isr : 0;
228 if ((tpr & 0xf0) >= (isrv & 0xf0))
233 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
234 apic, ppr, isr, isrv);
236 apic_set_reg(apic, APIC_PROCPRI, ppr);
239 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
241 apic_set_reg(apic, APIC_TASKPRI, tpr);
242 apic_update_ppr(apic);
245 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
247 return dest == 0xff || kvm_apic_id(apic) == dest;
250 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
255 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
257 switch (apic_get_reg(apic, APIC_DFR)) {
259 if (logical_id & mda)
262 case APIC_DFR_CLUSTER:
263 if (((logical_id >> 4) == (mda >> 0x4))
264 && (logical_id & mda & 0xf))
268 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
269 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
276 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
277 int short_hand, int dest, int dest_mode)
280 struct kvm_lapic *target = vcpu->arch.apic;
282 apic_debug("target %p, source %p, dest 0x%x, "
283 "dest_mode 0x%x, short_hand 0x%x\n",
284 target, source, dest, dest_mode, short_hand);
287 switch (short_hand) {
288 case APIC_DEST_NOSHORT:
291 result = kvm_apic_match_physical_addr(target, dest);
294 result = kvm_apic_match_logical_addr(target, dest);
297 result = (target == source);
299 case APIC_DEST_ALLINC:
302 case APIC_DEST_ALLBUT:
303 result = (target != source);
306 printk(KERN_WARNING "Bad dest shorthand value %x\n",
315 * Add a pending IRQ into lapic.
316 * Return 1 if successfully added and 0 if discarded.
318 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
319 int vector, int level, int trig_mode)
322 struct kvm_vcpu *vcpu = apic->vcpu;
324 switch (delivery_mode) {
326 vcpu->arch.apic_arb_prio++;
328 /* FIXME add logic for vcpu on reset */
329 if (unlikely(!apic_enabled(apic)))
332 result = !apic_test_and_set_irr(vector, apic);
335 apic_debug("level trig mode repeatedly for "
336 "vector %d", vector);
341 apic_debug("level trig mode for vector %d", vector);
342 apic_set_vector(vector, apic->regs + APIC_TMR);
344 apic_clear_vector(vector, apic->regs + APIC_TMR);
349 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
353 printk(KERN_DEBUG "Ignoring guest SMI\n");
358 kvm_inject_nmi(vcpu);
365 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
367 "INIT on a runnable vcpu %d\n",
369 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
372 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
377 case APIC_DM_STARTUP:
378 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
379 vcpu->vcpu_id, vector);
380 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
382 vcpu->arch.sipi_vector = vector;
383 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
390 * Should only be called by kvm_apic_local_deliver() with LVT0,
391 * before NMI watchdog was enabled. Already handled by
392 * kvm_apic_accept_pic_intr().
397 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
404 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
406 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
409 static void apic_set_eoi(struct kvm_lapic *apic)
411 int vector = apic_find_highest_isr(apic);
414 * Not every write EOI will has corresponding ISR,
415 * one example is when Kernel check timer on setup_IO_APIC
420 apic_clear_vector(vector, apic->regs + APIC_ISR);
421 apic_update_ppr(apic);
423 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
424 trigger_mode = IOAPIC_LEVEL_TRIG;
426 trigger_mode = IOAPIC_EDGE_TRIG;
427 mutex_lock(&apic->vcpu->kvm->irq_lock);
428 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
429 mutex_unlock(&apic->vcpu->kvm->irq_lock);
432 static void apic_send_ipi(struct kvm_lapic *apic)
434 u32 icr_low = apic_get_reg(apic, APIC_ICR);
435 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
436 struct kvm_lapic_irq irq;
438 irq.vector = icr_low & APIC_VECTOR_MASK;
439 irq.delivery_mode = icr_low & APIC_MODE_MASK;
440 irq.dest_mode = icr_low & APIC_DEST_MASK;
441 irq.level = icr_low & APIC_INT_ASSERT;
442 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
443 irq.shorthand = icr_low & APIC_SHORT_MASK;
444 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
446 apic_debug("icr_high 0x%x, icr_low 0x%x, "
447 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
448 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
449 icr_high, icr_low, irq.shorthand, irq.dest_id,
450 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
453 mutex_lock(&apic->vcpu->kvm->irq_lock);
454 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
455 mutex_unlock(&apic->vcpu->kvm->irq_lock);
458 static u32 apic_get_tmcct(struct kvm_lapic *apic)
464 ASSERT(apic != NULL);
466 /* if initial count is 0, current count should also be 0 */
467 if (apic_get_reg(apic, APIC_TMICT) == 0)
470 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
471 if (ktime_to_ns(remaining) < 0)
472 remaining = ktime_set(0, 0);
474 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
475 tmcct = div64_u64(ns,
476 (APIC_BUS_CYCLE_NS * apic->divide_count));
481 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
483 struct kvm_vcpu *vcpu = apic->vcpu;
484 struct kvm_run *run = vcpu->run;
486 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
487 run->tpr_access.rip = kvm_rip_read(vcpu);
488 run->tpr_access.is_write = write;
491 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
493 if (apic->vcpu->arch.tpr_access_reporting)
494 __report_tpr_access(apic, write);
497 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
501 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
503 if (offset >= LAPIC_MMIO_LENGTH)
508 printk(KERN_WARNING "Access APIC ARBPRI register "
509 "which is for P6\n");
512 case APIC_TMCCT: /* Timer CCR */
513 val = apic_get_tmcct(apic);
517 report_tpr_access(apic, false);
520 apic_update_ppr(apic);
521 val = apic_get_reg(apic, offset);
528 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
530 return container_of(dev, struct kvm_lapic, dev);
533 static void apic_mmio_read(struct kvm_io_device *this,
534 gpa_t address, int len, void *data)
536 struct kvm_lapic *apic = to_lapic(this);
537 unsigned int offset = address - apic->base_address;
538 unsigned char alignment = offset & 0xf;
541 if ((alignment + len) > 4) {
542 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
543 (unsigned long)address, len);
546 result = __apic_read(apic, offset & ~0xf);
552 memcpy(data, (char *)&result + alignment, len);
555 printk(KERN_ERR "Local APIC read with len = %x, "
556 "should be 1,2, or 4 instead\n", len);
561 static void update_divide_count(struct kvm_lapic *apic)
563 u32 tmp1, tmp2, tdcr;
565 tdcr = apic_get_reg(apic, APIC_TDCR);
567 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
568 apic->divide_count = 0x1 << (tmp2 & 0x7);
570 apic_debug("timer divide count is 0x%x\n",
574 static void start_apic_timer(struct kvm_lapic *apic)
576 ktime_t now = apic->lapic_timer.timer.base->get_time();
578 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
579 APIC_BUS_CYCLE_NS * apic->divide_count;
580 atomic_set(&apic->lapic_timer.pending, 0);
582 if (!apic->lapic_timer.period)
585 hrtimer_start(&apic->lapic_timer.timer,
586 ktime_add_ns(now, apic->lapic_timer.period),
589 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
591 "timer initial count 0x%x, period %lldns, "
592 "expire @ 0x%016" PRIx64 ".\n", __func__,
593 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
594 apic_get_reg(apic, APIC_TMICT),
595 apic->lapic_timer.period,
596 ktime_to_ns(ktime_add_ns(now,
597 apic->lapic_timer.period)));
600 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
602 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
604 if (apic_lvt_nmi_mode(lvt0_val)) {
605 if (!nmi_wd_enabled) {
606 apic_debug("Receive NMI setting on APIC_LVT0 "
607 "for cpu %d\n", apic->vcpu->vcpu_id);
608 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
610 } else if (nmi_wd_enabled)
611 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
614 static void apic_mmio_write(struct kvm_io_device *this,
615 gpa_t address, int len, const void *data)
617 struct kvm_lapic *apic = to_lapic(this);
618 unsigned int offset = address - apic->base_address;
619 unsigned char alignment = offset & 0xf;
623 * APIC register must be aligned on 128-bits boundary.
624 * 32/64/128 bits registers must be accessed thru 32 bits.
627 if (len != 4 || alignment) {
628 /* Don't shout loud, $infamous_os would cause only noise. */
629 apic_debug("apic write: bad size=%d %lx\n",
636 /* too common printing */
637 if (offset != APIC_EOI)
638 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
639 "0x%x\n", __func__, offset, len, val);
643 KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
646 case APIC_ID: /* Local APIC ID */
647 apic_set_reg(apic, APIC_ID, val);
651 report_tpr_access(apic, true);
652 apic_set_tpr(apic, val & 0xff);
660 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
664 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
668 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
669 if (!(val & APIC_SPIV_APIC_ENABLED)) {
673 for (i = 0; i < APIC_LVT_NUM; i++) {
674 lvt_val = apic_get_reg(apic,
675 APIC_LVTT + 0x10 * i);
676 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
677 lvt_val | APIC_LVT_MASKED);
679 atomic_set(&apic->lapic_timer.pending, 0);
685 /* No delay here, so we always clear the pending bit */
686 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
691 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
695 apic_manage_nmi_watchdog(apic, val);
701 /* TODO: Check vector */
702 if (!apic_sw_enabled(apic))
703 val |= APIC_LVT_MASKED;
705 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
706 apic_set_reg(apic, offset, val);
711 hrtimer_cancel(&apic->lapic_timer.timer);
712 apic_set_reg(apic, APIC_TMICT, val);
713 start_apic_timer(apic);
718 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
719 apic_set_reg(apic, APIC_TDCR, val);
720 update_divide_count(apic);
724 apic_debug("Local APIC Write to read-only register %x\n",
731 static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
734 struct kvm_lapic *apic = to_lapic(this);
738 if (apic_hw_enabled(apic) &&
739 (addr >= apic->base_address) &&
740 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
746 void kvm_free_lapic(struct kvm_vcpu *vcpu)
748 if (!vcpu->arch.apic)
751 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
753 if (vcpu->arch.apic->regs_page)
754 __free_page(vcpu->arch.apic->regs_page);
756 kfree(vcpu->arch.apic);
760 *----------------------------------------------------------------------
762 *----------------------------------------------------------------------
765 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
767 struct kvm_lapic *apic = vcpu->arch.apic;
771 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
772 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
775 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
777 struct kvm_lapic *apic = vcpu->arch.apic;
782 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
784 return (tpr & 0xf0) >> 4;
787 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
789 struct kvm_lapic *apic = vcpu->arch.apic;
792 value |= MSR_IA32_APICBASE_BSP;
793 vcpu->arch.apic_base = value;
797 if (!kvm_vcpu_is_bsp(apic->vcpu))
798 value &= ~MSR_IA32_APICBASE_BSP;
800 vcpu->arch.apic_base = value;
801 apic->base_address = apic->vcpu->arch.apic_base &
802 MSR_IA32_APICBASE_BASE;
804 /* with FSB delivery interrupt, we can restart APIC functionality */
805 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
806 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
810 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
812 struct kvm_lapic *apic;
815 apic_debug("%s\n", __func__);
818 apic = vcpu->arch.apic;
819 ASSERT(apic != NULL);
821 /* Stop the timer in case it's a reset to an active apic */
822 hrtimer_cancel(&apic->lapic_timer.timer);
824 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
825 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
827 for (i = 0; i < APIC_LVT_NUM; i++)
828 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
829 apic_set_reg(apic, APIC_LVT0,
830 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
832 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
833 apic_set_reg(apic, APIC_SPIV, 0xff);
834 apic_set_reg(apic, APIC_TASKPRI, 0);
835 apic_set_reg(apic, APIC_LDR, 0);
836 apic_set_reg(apic, APIC_ESR, 0);
837 apic_set_reg(apic, APIC_ICR, 0);
838 apic_set_reg(apic, APIC_ICR2, 0);
839 apic_set_reg(apic, APIC_TDCR, 0);
840 apic_set_reg(apic, APIC_TMICT, 0);
841 for (i = 0; i < 8; i++) {
842 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
843 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
844 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
846 update_divide_count(apic);
847 atomic_set(&apic->lapic_timer.pending, 0);
848 if (kvm_vcpu_is_bsp(vcpu))
849 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
850 apic_update_ppr(apic);
852 vcpu->arch.apic_arb_prio = 0;
854 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
855 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
856 vcpu, kvm_apic_id(apic),
857 vcpu->arch.apic_base, apic->base_address);
860 bool kvm_apic_present(struct kvm_vcpu *vcpu)
862 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
865 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
867 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
871 *----------------------------------------------------------------------
873 *----------------------------------------------------------------------
876 static bool lapic_is_periodic(struct kvm_timer *ktimer)
878 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
880 return apic_lvtt_period(apic);
883 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
885 struct kvm_lapic *lapic = vcpu->arch.apic;
887 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
888 return atomic_read(&lapic->lapic_timer.pending);
893 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
895 u32 reg = apic_get_reg(apic, lvt_type);
896 int vector, mode, trig_mode;
898 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
899 vector = reg & APIC_VECTOR_MASK;
900 mode = reg & APIC_MODE_MASK;
901 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
902 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
907 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
909 struct kvm_lapic *apic = vcpu->arch.apic;
912 kvm_apic_local_deliver(apic, APIC_LVT0);
915 static struct kvm_timer_ops lapic_timer_ops = {
916 .is_periodic = lapic_is_periodic,
919 static const struct kvm_io_device_ops apic_mmio_ops = {
920 .read = apic_mmio_read,
921 .write = apic_mmio_write,
922 .in_range = apic_mmio_range,
925 int kvm_create_lapic(struct kvm_vcpu *vcpu)
927 struct kvm_lapic *apic;
929 ASSERT(vcpu != NULL);
930 apic_debug("apic_init %d\n", vcpu->vcpu_id);
932 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
936 vcpu->arch.apic = apic;
938 apic->regs_page = alloc_page(GFP_KERNEL);
939 if (apic->regs_page == NULL) {
940 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
942 goto nomem_free_apic;
944 apic->regs = page_address(apic->regs_page);
945 memset(apic->regs, 0, PAGE_SIZE);
948 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
950 apic->lapic_timer.timer.function = kvm_timer_fn;
951 apic->lapic_timer.t_ops = &lapic_timer_ops;
952 apic->lapic_timer.kvm = vcpu->kvm;
953 apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
955 apic->base_address = APIC_DEFAULT_PHYS_BASE;
956 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
958 kvm_lapic_reset(vcpu);
959 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
968 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
970 struct kvm_lapic *apic = vcpu->arch.apic;
973 if (!apic || !apic_enabled(apic))
976 apic_update_ppr(apic);
977 highest_irr = apic_find_highest_irr(apic);
978 if ((highest_irr == -1) ||
979 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
984 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
986 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
989 if (kvm_vcpu_is_bsp(vcpu)) {
990 if (!apic_hw_enabled(vcpu->arch.apic))
992 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
993 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
999 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1001 struct kvm_lapic *apic = vcpu->arch.apic;
1003 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1004 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1005 atomic_dec(&apic->lapic_timer.pending);
1009 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1011 int vector = kvm_apic_has_interrupt(vcpu);
1012 struct kvm_lapic *apic = vcpu->arch.apic;
1017 apic_set_vector(vector, apic->regs + APIC_ISR);
1018 apic_update_ppr(apic);
1019 apic_clear_irr(vector, apic);
1023 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1025 struct kvm_lapic *apic = vcpu->arch.apic;
1027 apic->base_address = vcpu->arch.apic_base &
1028 MSR_IA32_APICBASE_BASE;
1029 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1030 apic_update_ppr(apic);
1031 hrtimer_cancel(&apic->lapic_timer.timer);
1032 update_divide_count(apic);
1033 start_apic_timer(apic);
1036 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1038 struct kvm_lapic *apic = vcpu->arch.apic;
1039 struct hrtimer *timer;
1044 timer = &apic->lapic_timer.timer;
1045 if (hrtimer_cancel(timer))
1046 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1049 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1054 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1057 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1058 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1059 kunmap_atomic(vapic, KM_USER0);
1061 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1064 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1067 int max_irr, max_isr;
1068 struct kvm_lapic *apic;
1071 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1074 apic = vcpu->arch.apic;
1075 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1076 max_irr = apic_find_highest_irr(apic);
1079 max_isr = apic_find_highest_isr(apic);
1082 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1084 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1085 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1086 kunmap_atomic(vapic, KM_USER0);
1089 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1091 if (!irqchip_in_kernel(vcpu->kvm))
1094 vcpu->arch.apic->vapic_addr = vapic_addr;