3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
49 #define mod_64(x, y) ((x) % (y))
57 #define APIC_BUS_CYCLE_NS 1
59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
60 #define apic_debug(fmt, arg...)
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 static inline int apic_test_vector(int vec, void *bitmap)
77 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
80 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
82 struct kvm_lapic *apic = vcpu->arch.apic;
84 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
85 apic_test_vector(vector, apic->regs + APIC_IRR);
88 static inline void apic_clear_vector(int vec, void *bitmap)
90 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
93 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
95 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
98 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
100 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
103 struct static_key_deferred apic_hw_disabled __read_mostly;
104 struct static_key_deferred apic_sw_disabled __read_mostly;
106 static inline int apic_enabled(struct kvm_lapic *apic)
108 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
112 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
115 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
116 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
118 /* The logical map is definitely wrong if we have multiple
119 * modes at the same time. (Physical map is always right.)
121 static inline bool kvm_apic_logical_map_valid(struct kvm_apic_map *map)
123 return !(map->mode & (map->mode - 1));
127 apic_logical_id(struct kvm_apic_map *map, u32 dest_id, u16 *cid, u16 *lid)
131 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_CLUSTER != 4);
132 BUILD_BUG_ON(KVM_APIC_MODE_XAPIC_FLAT != 8);
133 BUILD_BUG_ON(KVM_APIC_MODE_X2APIC != 16);
134 lid_bits = map->mode;
136 *cid = dest_id >> lid_bits;
137 *lid = dest_id & ((1 << lid_bits) - 1);
140 static void recalculate_apic_map(struct kvm *kvm)
142 struct kvm_apic_map *new, *old = NULL;
143 struct kvm_vcpu *vcpu;
146 new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
148 mutex_lock(&kvm->arch.apic_map_lock);
153 kvm_for_each_vcpu(i, vcpu, kvm) {
154 struct kvm_lapic *apic = vcpu->arch.apic;
158 if (!kvm_apic_present(vcpu))
161 aid = kvm_apic_id(apic);
162 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
164 if (aid < ARRAY_SIZE(new->phys_map))
165 new->phys_map[aid] = apic;
167 if (apic_x2apic_mode(apic)) {
168 new->mode |= KVM_APIC_MODE_X2APIC;
170 ldr = GET_APIC_LOGICAL_ID(ldr);
171 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
172 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
174 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
177 if (!kvm_apic_logical_map_valid(new))
180 apic_logical_id(new, ldr, &cid, &lid);
182 if (lid && cid < ARRAY_SIZE(new->logical_map))
183 new->logical_map[cid][ffs(lid) - 1] = apic;
186 old = rcu_dereference_protected(kvm->arch.apic_map,
187 lockdep_is_held(&kvm->arch.apic_map_lock));
188 rcu_assign_pointer(kvm->arch.apic_map, new);
189 mutex_unlock(&kvm->arch.apic_map_lock);
194 kvm_make_scan_ioapic_request(kvm);
197 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
199 bool enabled = val & APIC_SPIV_APIC_ENABLED;
201 kvm_lapic_set_reg(apic, APIC_SPIV, val);
203 if (enabled != apic->sw_enabled) {
204 apic->sw_enabled = enabled;
206 static_key_slow_dec_deferred(&apic_sw_disabled);
207 recalculate_apic_map(apic->vcpu->kvm);
209 static_key_slow_inc(&apic_sw_disabled.key);
213 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
215 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
216 recalculate_apic_map(apic->vcpu->kvm);
219 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
221 kvm_lapic_set_reg(apic, APIC_LDR, id);
222 recalculate_apic_map(apic->vcpu->kvm);
225 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
227 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
229 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
230 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
231 recalculate_apic_map(apic->vcpu->kvm);
234 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
236 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
239 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
241 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
244 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
246 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
249 static inline int apic_lvtt_period(struct kvm_lapic *apic)
251 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
254 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
256 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
259 static inline int apic_lvt_nmi_mode(u32 lvt_val)
261 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
264 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
266 struct kvm_lapic *apic = vcpu->arch.apic;
267 struct kvm_cpuid_entry2 *feat;
268 u32 v = APIC_VERSION;
270 if (!lapic_in_kernel(vcpu))
273 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
274 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
275 v |= APIC_LVR_DIRECTED_EOI;
276 kvm_lapic_set_reg(apic, APIC_LVR, v);
279 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
280 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
281 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
282 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
283 LINT_MASK, LINT_MASK, /* LVT0-1 */
284 LVT_MASK /* LVTERR */
287 static int find_highest_vector(void *bitmap)
292 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
293 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
294 reg = bitmap + REG_POS(vec);
296 return fls(*reg) - 1 + vec;
302 static u8 count_vectors(void *bitmap)
308 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
309 reg = bitmap + REG_POS(vec);
310 count += hweight32(*reg);
316 void __kvm_apic_update_irr(u32 *pir, void *regs)
320 for (i = 0; i <= 7; i++) {
321 pir_val = xchg(&pir[i], 0);
323 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
326 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
328 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
330 struct kvm_lapic *apic = vcpu->arch.apic;
332 __kvm_apic_update_irr(pir, apic->regs);
334 kvm_make_request(KVM_REQ_EVENT, vcpu);
336 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
338 static inline int apic_search_irr(struct kvm_lapic *apic)
340 return find_highest_vector(apic->regs + APIC_IRR);
343 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
348 * Note that irr_pending is just a hint. It will be always
349 * true with virtual interrupt delivery enabled.
351 if (!apic->irr_pending)
354 if (apic->vcpu->arch.apicv_active)
355 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
356 result = apic_search_irr(apic);
357 ASSERT(result == -1 || result >= 16);
362 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
364 struct kvm_vcpu *vcpu;
368 if (unlikely(vcpu->arch.apicv_active)) {
369 /* try to update RVI */
370 apic_clear_vector(vec, apic->regs + APIC_IRR);
371 kvm_make_request(KVM_REQ_EVENT, vcpu);
373 apic->irr_pending = false;
374 apic_clear_vector(vec, apic->regs + APIC_IRR);
375 if (apic_search_irr(apic) != -1)
376 apic->irr_pending = true;
380 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
382 struct kvm_vcpu *vcpu;
384 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
390 * With APIC virtualization enabled, all caching is disabled
391 * because the processor can modify ISR under the hood. Instead
394 if (unlikely(vcpu->arch.apicv_active))
395 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
398 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
400 * ISR (in service register) bit is set when injecting an interrupt.
401 * The highest vector is injected. Thus the latest bit set matches
402 * the highest bit in ISR.
404 apic->highest_isr_cache = vec;
408 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
413 * Note that isr_count is always 1, and highest_isr_cache
414 * is always -1, with APIC virtualization enabled.
416 if (!apic->isr_count)
418 if (likely(apic->highest_isr_cache != -1))
419 return apic->highest_isr_cache;
421 result = find_highest_vector(apic->regs + APIC_ISR);
422 ASSERT(result == -1 || result >= 16);
427 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
429 struct kvm_vcpu *vcpu;
430 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
436 * We do get here for APIC virtualization enabled if the guest
437 * uses the Hyper-V APIC enlightenment. In this case we may need
438 * to trigger a new interrupt delivery by writing the SVI field;
439 * on the other hand isr_count and highest_isr_cache are unused
440 * and must be left alone.
442 if (unlikely(vcpu->arch.apicv_active))
443 kvm_x86_ops->hwapic_isr_update(vcpu,
444 apic_find_highest_isr(apic));
447 BUG_ON(apic->isr_count < 0);
448 apic->highest_isr_cache = -1;
452 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
454 /* This may race with setting of irr in __apic_accept_irq() and
455 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
456 * will cause vmexit immediately and the value will be recalculated
457 * on the next vmentry.
459 return apic_find_highest_irr(vcpu->arch.apic);
462 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
463 int vector, int level, int trig_mode,
464 struct dest_map *dest_map);
466 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
467 struct dest_map *dest_map)
469 struct kvm_lapic *apic = vcpu->arch.apic;
471 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
472 irq->level, irq->trig_mode, dest_map);
475 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
478 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
482 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
485 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
489 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
491 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
494 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
497 if (pv_eoi_get_user(vcpu, &val) < 0)
498 apic_debug("Can't read EOI MSR value: 0x%llx\n",
499 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
503 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
505 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
506 apic_debug("Can't set EOI MSR value: 0x%llx\n",
507 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
510 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
513 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
515 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
516 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
517 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
520 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
523 static void apic_update_ppr(struct kvm_lapic *apic)
525 u32 tpr, isrv, ppr, old_ppr;
528 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
529 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
530 isr = apic_find_highest_isr(apic);
531 isrv = (isr != -1) ? isr : 0;
533 if ((tpr & 0xf0) >= (isrv & 0xf0))
538 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
539 apic, ppr, isr, isrv);
541 if (old_ppr != ppr) {
542 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
544 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
548 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
550 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
551 apic_update_ppr(apic);
554 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
556 if (apic_x2apic_mode(apic))
557 return mda == X2APIC_BROADCAST;
559 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
562 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
564 if (kvm_apic_broadcast(apic, mda))
567 if (apic_x2apic_mode(apic))
568 return mda == kvm_apic_id(apic);
570 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
573 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
577 if (kvm_apic_broadcast(apic, mda))
580 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
582 if (apic_x2apic_mode(apic))
583 return ((logical_id >> 16) == (mda >> 16))
584 && (logical_id & mda & 0xffff) != 0;
586 logical_id = GET_APIC_LOGICAL_ID(logical_id);
587 mda = GET_APIC_DEST_FIELD(mda);
589 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
591 return (logical_id & mda) != 0;
592 case APIC_DFR_CLUSTER:
593 return ((logical_id >> 4) == (mda >> 4))
594 && (logical_id & mda & 0xf) != 0;
596 apic_debug("Bad DFR vcpu %d: %08x\n",
597 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
602 /* KVM APIC implementation has two quirks
603 * - dest always begins at 0 while xAPIC MDA has offset 24,
604 * - IOxAPIC messages have to be delivered (directly) to x2APIC.
606 static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source,
607 struct kvm_lapic *target)
609 bool ipi = source != NULL;
610 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
612 if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda)
613 return X2APIC_BROADCAST;
615 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
618 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
619 int short_hand, unsigned int dest, int dest_mode)
621 struct kvm_lapic *target = vcpu->arch.apic;
622 u32 mda = kvm_apic_mda(dest, source, target);
624 apic_debug("target %p, source %p, dest 0x%x, "
625 "dest_mode 0x%x, short_hand 0x%x\n",
626 target, source, dest, dest_mode, short_hand);
629 switch (short_hand) {
630 case APIC_DEST_NOSHORT:
631 if (dest_mode == APIC_DEST_PHYSICAL)
632 return kvm_apic_match_physical_addr(target, mda);
634 return kvm_apic_match_logical_addr(target, mda);
636 return target == source;
637 case APIC_DEST_ALLINC:
639 case APIC_DEST_ALLBUT:
640 return target != source;
642 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
647 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
649 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
650 const unsigned long *bitmap, u32 bitmap_size)
655 mod = vector % dest_vcpus;
657 for (i = 0; i <= mod; i++) {
658 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
659 BUG_ON(idx == bitmap_size);
665 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
667 if (!kvm->arch.disabled_lapic_found) {
668 kvm->arch.disabled_lapic_found = true;
670 "Disabled LAPIC found during irq injection\n");
674 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
675 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
677 struct kvm_apic_map *map;
678 unsigned long bitmap = 1;
679 struct kvm_lapic **dst;
681 bool ret, x2apic_ipi;
685 if (irq->shorthand == APIC_DEST_SELF) {
686 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
693 x2apic_ipi = src && apic_x2apic_mode(src);
694 if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST))
699 map = rcu_dereference(kvm->arch.apic_map);
706 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
707 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
710 dst = &map->phys_map[irq->dest_id];
714 if (!kvm_apic_logical_map_valid(map)) {
719 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
721 if (cid >= ARRAY_SIZE(map->logical_map))
724 dst = map->logical_map[cid];
726 if (!kvm_lowest_prio_delivery(irq))
729 if (!kvm_vector_hashing_enabled()) {
731 for_each_set_bit(i, &bitmap, 16) {
736 else if (kvm_apic_compare_prio(dst[i]->vcpu,
740 bitmap = (l >= 0) ? 1 << l : 0;
743 unsigned int dest_vcpus;
745 dest_vcpus = hweight16(bitmap);
749 idx = kvm_vector_to_index(irq->vector,
750 dest_vcpus, &bitmap, 16);
753 kvm_apic_disabled_lapic_found(kvm);
757 bitmap = (idx >= 0) ? 1 << idx : 0;
762 for_each_set_bit(i, &bitmap, 16) {
767 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
775 * This routine tries to handler interrupts in posted mode, here is how
776 * it deals with different cases:
777 * - For single-destination interrupts, handle it in posted mode
778 * - Else if vector hashing is enabled and it is a lowest-priority
779 * interrupt, handle it in posted mode and use the following mechanism
780 * to find the destinaiton vCPU.
781 * 1. For lowest-priority interrupts, store all the possible
782 * destination vCPUs in an array.
783 * 2. Use "guest vector % max number of destination vCPUs" to find
784 * the right destination vCPU in the array for the lowest-priority
786 * - Otherwise, use remapped mode to inject the interrupt.
788 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
789 struct kvm_vcpu **dest_vcpu)
791 struct kvm_apic_map *map;
793 struct kvm_lapic *dst = NULL;
799 map = rcu_dereference(kvm->arch.apic_map);
804 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
805 if (irq->dest_id == 0xFF)
808 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
811 dst = map->phys_map[irq->dest_id];
812 if (dst && kvm_apic_present(dst->vcpu))
813 *dest_vcpu = dst->vcpu;
818 unsigned long bitmap = 1;
821 if (!kvm_apic_logical_map_valid(map))
824 apic_logical_id(map, irq->dest_id, &cid, (u16 *)&bitmap);
826 if (cid >= ARRAY_SIZE(map->logical_map))
829 if (kvm_vector_hashing_enabled() &&
830 kvm_lowest_prio_delivery(irq)) {
832 unsigned int dest_vcpus;
834 dest_vcpus = hweight16(bitmap);
838 idx = kvm_vector_to_index(irq->vector, dest_vcpus,
841 dst = map->logical_map[cid][idx];
843 kvm_apic_disabled_lapic_found(kvm);
847 *dest_vcpu = dst->vcpu;
849 for_each_set_bit(i, &bitmap, 16) {
850 dst = map->logical_map[cid][i];
855 if (dst && kvm_apic_present(dst->vcpu))
856 *dest_vcpu = dst->vcpu;
869 * Add a pending IRQ into lapic.
870 * Return 1 if successfully added and 0 if discarded.
872 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
873 int vector, int level, int trig_mode,
874 struct dest_map *dest_map)
877 struct kvm_vcpu *vcpu = apic->vcpu;
879 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
881 switch (delivery_mode) {
883 vcpu->arch.apic_arb_prio++;
885 if (unlikely(trig_mode && !level))
888 /* FIXME add logic for vcpu on reset */
889 if (unlikely(!apic_enabled(apic)))
895 __set_bit(vcpu->vcpu_id, dest_map->map);
896 dest_map->vectors[vcpu->vcpu_id] = vector;
899 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
901 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
903 apic_clear_vector(vector, apic->regs + APIC_TMR);
906 if (vcpu->arch.apicv_active)
907 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
909 kvm_lapic_set_irr(vector, apic);
911 kvm_make_request(KVM_REQ_EVENT, vcpu);
918 vcpu->arch.pv.pv_unhalted = 1;
919 kvm_make_request(KVM_REQ_EVENT, vcpu);
925 kvm_make_request(KVM_REQ_SMI, vcpu);
931 kvm_inject_nmi(vcpu);
936 if (!trig_mode || level) {
938 /* assumes that there are only KVM_APIC_INIT/SIPI */
939 apic->pending_events = (1UL << KVM_APIC_INIT);
940 /* make sure pending_events is visible before sending
943 kvm_make_request(KVM_REQ_EVENT, vcpu);
946 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
951 case APIC_DM_STARTUP:
952 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
953 vcpu->vcpu_id, vector);
955 apic->sipi_vector = vector;
956 /* make sure sipi_vector is visible for the receiver */
958 set_bit(KVM_APIC_SIPI, &apic->pending_events);
959 kvm_make_request(KVM_REQ_EVENT, vcpu);
965 * Should only be called by kvm_apic_local_deliver() with LVT0,
966 * before NMI watchdog was enabled. Already handled by
967 * kvm_apic_accept_pic_intr().
972 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
979 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
981 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
984 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
986 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
989 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
993 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
994 if (!kvm_ioapic_handles_vector(apic, vector))
997 /* Request a KVM exit to inform the userspace IOAPIC. */
998 if (irqchip_split(apic->vcpu->kvm)) {
999 apic->vcpu->arch.pending_ioapic_eoi = vector;
1000 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1004 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1005 trigger_mode = IOAPIC_LEVEL_TRIG;
1007 trigger_mode = IOAPIC_EDGE_TRIG;
1009 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1012 static int apic_set_eoi(struct kvm_lapic *apic)
1014 int vector = apic_find_highest_isr(apic);
1016 trace_kvm_eoi(apic, vector);
1019 * Not every write EOI will has corresponding ISR,
1020 * one example is when Kernel check timer on setup_IO_APIC
1025 apic_clear_isr(vector, apic);
1026 apic_update_ppr(apic);
1028 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1029 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1031 kvm_ioapic_send_eoi(apic, vector);
1032 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1037 * this interface assumes a trap-like exit, which has already finished
1038 * desired side effect including vISR and vPPR update.
1040 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1042 struct kvm_lapic *apic = vcpu->arch.apic;
1044 trace_kvm_eoi(apic, vector);
1046 kvm_ioapic_send_eoi(apic, vector);
1047 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1049 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1051 static void apic_send_ipi(struct kvm_lapic *apic)
1053 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1054 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1055 struct kvm_lapic_irq irq;
1057 irq.vector = icr_low & APIC_VECTOR_MASK;
1058 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1059 irq.dest_mode = icr_low & APIC_DEST_MASK;
1060 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1061 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1062 irq.shorthand = icr_low & APIC_SHORT_MASK;
1063 irq.msi_redir_hint = false;
1064 if (apic_x2apic_mode(apic))
1065 irq.dest_id = icr_high;
1067 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1069 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1071 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1072 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1073 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1074 "msi_redir_hint 0x%x\n",
1075 icr_high, icr_low, irq.shorthand, irq.dest_id,
1076 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1077 irq.vector, irq.msi_redir_hint);
1079 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1082 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1088 ASSERT(apic != NULL);
1090 /* if initial count is 0, current count should also be 0 */
1091 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1092 apic->lapic_timer.period == 0)
1095 remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
1096 if (ktime_to_ns(remaining) < 0)
1097 remaining = ktime_set(0, 0);
1099 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1100 tmcct = div64_u64(ns,
1101 (APIC_BUS_CYCLE_NS * apic->divide_count));
1106 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1108 struct kvm_vcpu *vcpu = apic->vcpu;
1109 struct kvm_run *run = vcpu->run;
1111 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1112 run->tpr_access.rip = kvm_rip_read(vcpu);
1113 run->tpr_access.is_write = write;
1116 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1118 if (apic->vcpu->arch.tpr_access_reporting)
1119 __report_tpr_access(apic, write);
1122 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1126 if (offset >= LAPIC_MMIO_LENGTH)
1131 if (apic_x2apic_mode(apic))
1132 val = kvm_apic_id(apic);
1134 val = kvm_apic_id(apic) << 24;
1137 apic_debug("Access APIC ARBPRI register which is for P6\n");
1140 case APIC_TMCCT: /* Timer CCR */
1141 if (apic_lvtt_tscdeadline(apic))
1144 val = apic_get_tmcct(apic);
1147 apic_update_ppr(apic);
1148 val = kvm_lapic_get_reg(apic, offset);
1151 report_tpr_access(apic, false);
1154 val = kvm_lapic_get_reg(apic, offset);
1161 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1163 return container_of(dev, struct kvm_lapic, dev);
1166 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1169 unsigned char alignment = offset & 0xf;
1171 /* this bitmask has a bit cleared for each reserved register */
1172 static const u64 rmask = 0x43ff01ffffffe70cULL;
1174 if ((alignment + len) > 4) {
1175 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1180 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1181 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1186 result = __apic_read(apic, offset & ~0xf);
1188 trace_kvm_apic_read(offset, result);
1194 memcpy(data, (char *)&result + alignment, len);
1197 printk(KERN_ERR "Local APIC read with len = %x, "
1198 "should be 1,2, or 4 instead\n", len);
1203 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1205 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1207 return kvm_apic_hw_enabled(apic) &&
1208 addr >= apic->base_address &&
1209 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1212 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1213 gpa_t address, int len, void *data)
1215 struct kvm_lapic *apic = to_lapic(this);
1216 u32 offset = address - apic->base_address;
1218 if (!apic_mmio_in_range(apic, address))
1221 kvm_lapic_reg_read(apic, offset, len, data);
1226 static void update_divide_count(struct kvm_lapic *apic)
1228 u32 tmp1, tmp2, tdcr;
1230 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1232 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1233 apic->divide_count = 0x1 << (tmp2 & 0x7);
1235 apic_debug("timer divide count is 0x%x\n",
1236 apic->divide_count);
1239 static void apic_update_lvtt(struct kvm_lapic *apic)
1241 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1242 apic->lapic_timer.timer_mode_mask;
1244 if (apic->lapic_timer.timer_mode != timer_mode) {
1245 apic->lapic_timer.timer_mode = timer_mode;
1246 hrtimer_cancel(&apic->lapic_timer.timer);
1250 static void apic_timer_expired(struct kvm_lapic *apic)
1252 struct kvm_vcpu *vcpu = apic->vcpu;
1253 struct swait_queue_head *q = &vcpu->wq;
1254 struct kvm_timer *ktimer = &apic->lapic_timer;
1256 if (atomic_read(&apic->lapic_timer.pending))
1259 atomic_inc(&apic->lapic_timer.pending);
1260 kvm_set_pending_timer(vcpu);
1262 if (swait_active(q))
1265 if (apic_lvtt_tscdeadline(apic))
1266 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1270 * On APICv, this test will cause a busy wait
1271 * during a higher-priority task.
1274 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1276 struct kvm_lapic *apic = vcpu->arch.apic;
1277 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1279 if (kvm_apic_hw_enabled(apic)) {
1280 int vec = reg & APIC_VECTOR_MASK;
1281 void *bitmap = apic->regs + APIC_ISR;
1283 if (vcpu->arch.apicv_active)
1284 bitmap = apic->regs + APIC_IRR;
1286 if (apic_test_vector(vec, bitmap))
1292 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1294 struct kvm_lapic *apic = vcpu->arch.apic;
1295 u64 guest_tsc, tsc_deadline;
1297 if (!lapic_in_kernel(vcpu))
1300 if (apic->lapic_timer.expired_tscdeadline == 0)
1303 if (!lapic_timer_int_injected(vcpu))
1306 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1307 apic->lapic_timer.expired_tscdeadline = 0;
1308 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1309 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1311 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1312 if (guest_tsc < tsc_deadline)
1313 __delay(tsc_deadline - guest_tsc);
1316 static void start_apic_timer(struct kvm_lapic *apic)
1320 atomic_set(&apic->lapic_timer.pending, 0);
1322 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1323 /* lapic timer in oneshot or periodic mode */
1324 now = apic->lapic_timer.timer.base->get_time();
1325 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1326 * APIC_BUS_CYCLE_NS * apic->divide_count;
1328 if (!apic->lapic_timer.period)
1331 * Do not allow the guest to program periodic timers with small
1332 * interval, since the hrtimers are not throttled by the host
1335 if (apic_lvtt_period(apic)) {
1336 s64 min_period = min_timer_period_us * 1000LL;
1338 if (apic->lapic_timer.period < min_period) {
1339 pr_info_ratelimited(
1340 "kvm: vcpu %i: requested %lld ns "
1341 "lapic timer period limited to %lld ns\n",
1342 apic->vcpu->vcpu_id,
1343 apic->lapic_timer.period, min_period);
1344 apic->lapic_timer.period = min_period;
1348 hrtimer_start(&apic->lapic_timer.timer,
1349 ktime_add_ns(now, apic->lapic_timer.period),
1350 HRTIMER_MODE_ABS_PINNED);
1352 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1354 "timer initial count 0x%x, period %lldns, "
1355 "expire @ 0x%016" PRIx64 ".\n", __func__,
1356 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1357 kvm_lapic_get_reg(apic, APIC_TMICT),
1358 apic->lapic_timer.period,
1359 ktime_to_ns(ktime_add_ns(now,
1360 apic->lapic_timer.period)));
1361 } else if (apic_lvtt_tscdeadline(apic)) {
1362 /* lapic timer in tsc deadline mode */
1363 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1366 struct kvm_vcpu *vcpu = apic->vcpu;
1367 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1368 unsigned long flags;
1370 if (unlikely(!tscdeadline || !this_tsc_khz))
1373 local_irq_save(flags);
1375 now = apic->lapic_timer.timer.base->get_time();
1376 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1377 if (likely(tscdeadline > guest_tsc)) {
1378 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1379 do_div(ns, this_tsc_khz);
1380 expire = ktime_add_ns(now, ns);
1381 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1382 hrtimer_start(&apic->lapic_timer.timer,
1383 expire, HRTIMER_MODE_ABS_PINNED);
1385 apic_timer_expired(apic);
1387 local_irq_restore(flags);
1391 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1393 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1395 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1396 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1397 if (lvt0_in_nmi_mode) {
1398 apic_debug("Receive NMI setting on APIC_LVT0 "
1399 "for cpu %d\n", apic->vcpu->vcpu_id);
1400 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1402 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1406 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1410 trace_kvm_apic_write(reg, val);
1413 case APIC_ID: /* Local APIC ID */
1414 if (!apic_x2apic_mode(apic))
1415 kvm_apic_set_id(apic, val >> 24);
1421 report_tpr_access(apic, true);
1422 apic_set_tpr(apic, val & 0xff);
1430 if (!apic_x2apic_mode(apic))
1431 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1437 if (!apic_x2apic_mode(apic)) {
1438 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1439 recalculate_apic_map(apic->vcpu->kvm);
1446 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1447 mask |= APIC_SPIV_DIRECTED_EOI;
1448 apic_set_spiv(apic, val & mask);
1449 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1453 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1454 lvt_val = kvm_lapic_get_reg(apic,
1455 APIC_LVTT + 0x10 * i);
1456 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1457 lvt_val | APIC_LVT_MASKED);
1459 apic_update_lvtt(apic);
1460 atomic_set(&apic->lapic_timer.pending, 0);
1466 /* No delay here, so we always clear the pending bit */
1467 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1468 apic_send_ipi(apic);
1472 if (!apic_x2apic_mode(apic))
1474 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1478 apic_manage_nmi_watchdog(apic, val);
1483 /* TODO: Check vector */
1484 if (!kvm_apic_sw_enabled(apic))
1485 val |= APIC_LVT_MASKED;
1487 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1488 kvm_lapic_set_reg(apic, reg, val);
1493 if (!kvm_apic_sw_enabled(apic))
1494 val |= APIC_LVT_MASKED;
1495 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1496 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1497 apic_update_lvtt(apic);
1501 if (apic_lvtt_tscdeadline(apic))
1504 hrtimer_cancel(&apic->lapic_timer.timer);
1505 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1506 start_apic_timer(apic);
1511 apic_debug("KVM_WRITE:TDCR %x\n", val);
1512 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1513 update_divide_count(apic);
1517 if (apic_x2apic_mode(apic) && val != 0) {
1518 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1524 if (apic_x2apic_mode(apic)) {
1525 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1534 apic_debug("Local APIC Write to read-only register %x\n", reg);
1537 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1539 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1540 gpa_t address, int len, const void *data)
1542 struct kvm_lapic *apic = to_lapic(this);
1543 unsigned int offset = address - apic->base_address;
1546 if (!apic_mmio_in_range(apic, address))
1550 * APIC register must be aligned on 128-bits boundary.
1551 * 32/64/128 bits registers must be accessed thru 32 bits.
1554 if (len != 4 || (offset & 0xf)) {
1555 /* Don't shout loud, $infamous_os would cause only noise. */
1556 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1562 /* too common printing */
1563 if (offset != APIC_EOI)
1564 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1565 "0x%x\n", __func__, offset, len, val);
1567 kvm_lapic_reg_write(apic, offset & 0xff0, val);
1572 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1574 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1576 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1578 /* emulate APIC access in a trap manner */
1579 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1583 /* hw has done the conditional check and inst decode */
1586 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1588 /* TODO: optimize to just emulate side effect w/o one more write */
1589 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1591 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1593 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1595 struct kvm_lapic *apic = vcpu->arch.apic;
1597 if (!vcpu->arch.apic)
1600 hrtimer_cancel(&apic->lapic_timer.timer);
1602 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1603 static_key_slow_dec_deferred(&apic_hw_disabled);
1605 if (!apic->sw_enabled)
1606 static_key_slow_dec_deferred(&apic_sw_disabled);
1609 free_page((unsigned long)apic->regs);
1615 *----------------------------------------------------------------------
1617 *----------------------------------------------------------------------
1620 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1622 struct kvm_lapic *apic = vcpu->arch.apic;
1624 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1625 apic_lvtt_period(apic))
1628 return apic->lapic_timer.tscdeadline;
1631 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1633 struct kvm_lapic *apic = vcpu->arch.apic;
1635 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1636 apic_lvtt_period(apic))
1639 hrtimer_cancel(&apic->lapic_timer.timer);
1640 apic->lapic_timer.tscdeadline = data;
1641 start_apic_timer(apic);
1644 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1646 struct kvm_lapic *apic = vcpu->arch.apic;
1648 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1649 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1652 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1656 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1658 return (tpr & 0xf0) >> 4;
1661 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1663 u64 old_value = vcpu->arch.apic_base;
1664 struct kvm_lapic *apic = vcpu->arch.apic;
1667 value |= MSR_IA32_APICBASE_BSP;
1668 vcpu->arch.apic_base = value;
1672 vcpu->arch.apic_base = value;
1674 /* update jump label if enable bit changes */
1675 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1676 if (value & MSR_IA32_APICBASE_ENABLE)
1677 static_key_slow_dec_deferred(&apic_hw_disabled);
1679 static_key_slow_inc(&apic_hw_disabled.key);
1680 recalculate_apic_map(vcpu->kvm);
1683 if ((old_value ^ value) & X2APIC_ENABLE) {
1684 if (value & X2APIC_ENABLE) {
1685 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1686 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1688 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1691 apic->base_address = apic->vcpu->arch.apic_base &
1692 MSR_IA32_APICBASE_BASE;
1694 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1695 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1696 pr_warn_once("APIC base relocation is unsupported by KVM");
1698 /* with FSB delivery interrupt, we can restart APIC functionality */
1699 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1700 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1704 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1706 struct kvm_lapic *apic;
1709 apic_debug("%s\n", __func__);
1712 apic = vcpu->arch.apic;
1713 ASSERT(apic != NULL);
1715 /* Stop the timer in case it's a reset to an active apic */
1716 hrtimer_cancel(&apic->lapic_timer.timer);
1719 kvm_apic_set_id(apic, vcpu->vcpu_id);
1720 kvm_apic_set_version(apic->vcpu);
1722 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1723 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1724 apic_update_lvtt(apic);
1725 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1726 kvm_lapic_set_reg(apic, APIC_LVT0,
1727 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1728 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1730 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
1731 apic_set_spiv(apic, 0xff);
1732 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
1733 if (!apic_x2apic_mode(apic))
1734 kvm_apic_set_ldr(apic, 0);
1735 kvm_lapic_set_reg(apic, APIC_ESR, 0);
1736 kvm_lapic_set_reg(apic, APIC_ICR, 0);
1737 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1738 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1739 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1740 for (i = 0; i < 8; i++) {
1741 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1742 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1743 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1745 apic->irr_pending = vcpu->arch.apicv_active;
1746 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1747 apic->highest_isr_cache = -1;
1748 update_divide_count(apic);
1749 atomic_set(&apic->lapic_timer.pending, 0);
1750 if (kvm_vcpu_is_bsp(vcpu))
1751 kvm_lapic_set_base(vcpu,
1752 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1753 vcpu->arch.pv_eoi.msr_val = 0;
1754 apic_update_ppr(apic);
1756 vcpu->arch.apic_arb_prio = 0;
1757 vcpu->arch.apic_attention = 0;
1759 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1760 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1761 vcpu, kvm_apic_id(apic),
1762 vcpu->arch.apic_base, apic->base_address);
1766 *----------------------------------------------------------------------
1768 *----------------------------------------------------------------------
1771 static bool lapic_is_periodic(struct kvm_lapic *apic)
1773 return apic_lvtt_period(apic);
1776 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1778 struct kvm_lapic *apic = vcpu->arch.apic;
1780 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1781 return atomic_read(&apic->lapic_timer.pending);
1786 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1788 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
1789 int vector, mode, trig_mode;
1791 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1792 vector = reg & APIC_VECTOR_MASK;
1793 mode = reg & APIC_MODE_MASK;
1794 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1795 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1801 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1803 struct kvm_lapic *apic = vcpu->arch.apic;
1806 kvm_apic_local_deliver(apic, APIC_LVT0);
1809 static const struct kvm_io_device_ops apic_mmio_ops = {
1810 .read = apic_mmio_read,
1811 .write = apic_mmio_write,
1814 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1816 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1817 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1819 apic_timer_expired(apic);
1821 if (lapic_is_periodic(apic)) {
1822 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1823 return HRTIMER_RESTART;
1825 return HRTIMER_NORESTART;
1828 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1830 struct kvm_lapic *apic;
1832 ASSERT(vcpu != NULL);
1833 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1835 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1839 vcpu->arch.apic = apic;
1841 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1843 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1845 goto nomem_free_apic;
1849 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1850 HRTIMER_MODE_ABS_PINNED);
1851 apic->lapic_timer.timer.function = apic_timer_fn;
1854 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1855 * thinking that APIC satet has changed.
1857 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1858 kvm_lapic_set_base(vcpu,
1859 APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1861 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1862 kvm_lapic_reset(vcpu, false);
1863 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1872 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1874 struct kvm_lapic *apic = vcpu->arch.apic;
1877 if (!apic_enabled(apic))
1880 apic_update_ppr(apic);
1881 highest_irr = apic_find_highest_irr(apic);
1882 if ((highest_irr == -1) ||
1883 ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI)))
1888 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1890 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
1893 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1895 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1896 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1901 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1903 struct kvm_lapic *apic = vcpu->arch.apic;
1905 if (atomic_read(&apic->lapic_timer.pending) > 0) {
1906 kvm_apic_local_deliver(apic, APIC_LVTT);
1907 if (apic_lvtt_tscdeadline(apic))
1908 apic->lapic_timer.tscdeadline = 0;
1909 atomic_set(&apic->lapic_timer.pending, 0);
1913 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1915 int vector = kvm_apic_has_interrupt(vcpu);
1916 struct kvm_lapic *apic = vcpu->arch.apic;
1922 * We get here even with APIC virtualization enabled, if doing
1923 * nested virtualization and L1 runs with the "acknowledge interrupt
1924 * on exit" mode. Then we cannot inject the interrupt via RVI,
1925 * because the process would deliver it through the IDT.
1928 apic_set_isr(vector, apic);
1929 apic_update_ppr(apic);
1930 apic_clear_irr(vector, apic);
1932 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
1933 apic_clear_isr(vector, apic);
1934 apic_update_ppr(apic);
1940 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1941 struct kvm_lapic_state *s)
1943 struct kvm_lapic *apic = vcpu->arch.apic;
1945 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1946 /* set SPIV separately to get count of SW disabled APICs right */
1947 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1948 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1949 /* call kvm_apic_set_id() to put apic into apic_map */
1950 kvm_apic_set_id(apic, kvm_apic_id(apic));
1951 kvm_apic_set_version(vcpu);
1953 apic_update_ppr(apic);
1954 hrtimer_cancel(&apic->lapic_timer.timer);
1955 apic_update_lvtt(apic);
1956 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1957 update_divide_count(apic);
1958 start_apic_timer(apic);
1959 apic->irr_pending = true;
1960 apic->isr_count = vcpu->arch.apicv_active ?
1961 1 : count_vectors(apic->regs + APIC_ISR);
1962 apic->highest_isr_cache = -1;
1963 if (vcpu->arch.apicv_active) {
1964 if (kvm_x86_ops->apicv_post_state_restore)
1965 kvm_x86_ops->apicv_post_state_restore(vcpu);
1966 kvm_x86_ops->hwapic_irr_update(vcpu,
1967 apic_find_highest_irr(apic));
1968 kvm_x86_ops->hwapic_isr_update(vcpu,
1969 apic_find_highest_isr(apic));
1971 kvm_make_request(KVM_REQ_EVENT, vcpu);
1972 if (ioapic_in_kernel(vcpu->kvm))
1973 kvm_rtc_eoi_tracking_restore_one(vcpu);
1975 vcpu->arch.apic_arb_prio = 0;
1978 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1980 struct hrtimer *timer;
1982 if (!lapic_in_kernel(vcpu))
1985 timer = &vcpu->arch.apic->lapic_timer.timer;
1986 if (hrtimer_cancel(timer))
1987 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
1991 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1993 * Detect whether guest triggered PV EOI since the
1994 * last entry. If yes, set EOI on guests's behalf.
1995 * Clear PV EOI in guest memory in any case.
1997 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1998 struct kvm_lapic *apic)
2003 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2004 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2006 * KVM_APIC_PV_EOI_PENDING is unset:
2007 * -> host disabled PV EOI.
2008 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2009 * -> host enabled PV EOI, guest did not execute EOI yet.
2010 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2011 * -> host enabled PV EOI, guest executed EOI.
2013 BUG_ON(!pv_eoi_enabled(vcpu));
2014 pending = pv_eoi_get_pending(vcpu);
2016 * Clear pending bit in any case: it will be set again on vmentry.
2017 * While this might not be ideal from performance point of view,
2018 * this makes sure pv eoi is only enabled when we know it's safe.
2020 pv_eoi_clr_pending(vcpu);
2023 vector = apic_set_eoi(apic);
2024 trace_kvm_pv_eoi(apic, vector);
2027 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2031 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2032 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2034 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2037 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2041 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2045 * apic_sync_pv_eoi_to_guest - called before vmentry
2047 * Detect whether it's safe to enable PV EOI and
2050 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2051 struct kvm_lapic *apic)
2053 if (!pv_eoi_enabled(vcpu) ||
2054 /* IRR set or many bits in ISR: could be nested. */
2055 apic->irr_pending ||
2056 /* Cache not set: could be safe but we don't bother. */
2057 apic->highest_isr_cache == -1 ||
2058 /* Need EOI to update ioapic. */
2059 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2061 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2062 * so we need not do anything here.
2067 pv_eoi_set_pending(apic->vcpu);
2070 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2073 int max_irr, max_isr;
2074 struct kvm_lapic *apic = vcpu->arch.apic;
2076 apic_sync_pv_eoi_to_guest(vcpu, apic);
2078 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2081 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2082 max_irr = apic_find_highest_irr(apic);
2085 max_isr = apic_find_highest_isr(apic);
2088 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2090 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2094 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2097 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2098 &vcpu->arch.apic->vapic_cache,
2099 vapic_addr, sizeof(u32)))
2101 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2103 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2106 vcpu->arch.apic->vapic_addr = vapic_addr;
2110 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2112 struct kvm_lapic *apic = vcpu->arch.apic;
2113 u32 reg = (msr - APIC_BASE_MSR) << 4;
2115 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2118 if (reg == APIC_ICR2)
2121 /* if this is ICR write vector before command */
2122 if (reg == APIC_ICR)
2123 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2124 return kvm_lapic_reg_write(apic, reg, (u32)data);
2127 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2129 struct kvm_lapic *apic = vcpu->arch.apic;
2130 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2132 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2135 if (reg == APIC_DFR || reg == APIC_ICR2) {
2136 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2141 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2143 if (reg == APIC_ICR)
2144 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2146 *data = (((u64)high) << 32) | low;
2151 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2153 struct kvm_lapic *apic = vcpu->arch.apic;
2155 if (!lapic_in_kernel(vcpu))
2158 /* if this is ICR write vector before command */
2159 if (reg == APIC_ICR)
2160 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2161 return kvm_lapic_reg_write(apic, reg, (u32)data);
2164 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2166 struct kvm_lapic *apic = vcpu->arch.apic;
2169 if (!lapic_in_kernel(vcpu))
2172 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2174 if (reg == APIC_ICR)
2175 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2177 *data = (((u64)high) << 32) | low;
2182 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2184 u64 addr = data & ~KVM_MSR_ENABLED;
2185 if (!IS_ALIGNED(addr, 4))
2188 vcpu->arch.pv_eoi.msr_val = data;
2189 if (!pv_eoi_enabled(vcpu))
2191 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2195 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2197 struct kvm_lapic *apic = vcpu->arch.apic;
2201 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2205 * INITs are latched while in SMM. Because an SMM CPU cannot
2206 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2207 * and delay processing of INIT until the next RSM.
2210 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2211 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2212 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2216 pe = xchg(&apic->pending_events, 0);
2217 if (test_bit(KVM_APIC_INIT, &pe)) {
2218 kvm_lapic_reset(vcpu, true);
2219 kvm_vcpu_reset(vcpu, true);
2220 if (kvm_vcpu_is_bsp(apic->vcpu))
2221 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2223 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2225 if (test_bit(KVM_APIC_SIPI, &pe) &&
2226 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2227 /* evaluate pending_events before reading the vector */
2229 sipi_vector = apic->sipi_vector;
2230 apic_debug("vcpu %d received sipi with vector # %x\n",
2231 vcpu->vcpu_id, sipi_vector);
2232 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2233 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2237 void kvm_lapic_init(void)
2239 /* do not patch jump label more than once per second */
2240 jump_label_rate_limit(&apic_hw_disabled, HZ);
2241 jump_label_rate_limit(&apic_sw_disabled, HZ);