2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
66 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
71 #define pgprintk(x...) do { } while (0)
72 #define rmap_printk(x...) do { } while (0)
78 module_param(dbg, bool, 0644);
82 #define ASSERT(x) do { } while (0)
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
91 #define PTE_PREFETCH_NUM 8
93 #define PT_FIRST_AVAIL_BITS_SHIFT 10
94 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
96 #define PT64_LEVEL_BITS 9
98 #define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
101 #define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105 #define PT32_LEVEL_BITS 10
107 #define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
110 #define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
114 #define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
118 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119 #define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121 #define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124 #define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
128 #define PT32_BASE_ADDR_MASK PAGE_MASK
129 #define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131 #define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
135 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
138 #define ACC_EXEC_MASK 1
139 #define ACC_WRITE_MASK PT_WRITABLE_MASK
140 #define ACC_USER_MASK PT_USER_MASK
141 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
143 #include <trace/events/kvm.h>
145 #define CREATE_TRACE_POINTS
146 #include "mmutrace.h"
148 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
151 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
153 /* make pte_list_desc fit well in cache line */
154 #define PTE_LIST_EXT 3
156 struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
161 struct kvm_shadow_walk_iterator {
169 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
174 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
180 static struct kmem_cache *pte_list_desc_cache;
181 static struct kmem_cache *mmu_page_header_cache;
182 static struct percpu_counter kvm_total_used_mmu_pages;
184 static u64 __read_mostly shadow_nx_mask;
185 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186 static u64 __read_mostly shadow_user_mask;
187 static u64 __read_mostly shadow_accessed_mask;
188 static u64 __read_mostly shadow_dirty_mask;
189 static u64 __read_mostly shadow_mmio_mask;
191 static void mmu_spte_set(u64 *sptep, u64 spte);
192 static void mmu_free_roots(struct kvm_vcpu *vcpu);
194 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
196 shadow_mmio_mask = mmio_mask;
198 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
201 * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number,
202 * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation
205 #define MMIO_SPTE_GEN_LOW_SHIFT 3
206 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
208 #define MMIO_GEN_LOW_SHIFT 9
209 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 1)
210 #define MMIO_MAX_GEN ((1 << 19) - 1)
212 static u64 generation_mmio_spte_mask(unsigned int gen)
216 WARN_ON(gen > MMIO_MAX_GEN);
218 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
219 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
223 static unsigned int get_mmio_spte_generation(u64 spte)
227 spte &= ~shadow_mmio_mask;
229 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
230 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
234 static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
237 struct kvm_mmu_page *sp = page_header(__pa(sptep));
238 u64 mask = generation_mmio_spte_mask(0);
240 access &= ACC_WRITE_MASK | ACC_USER_MASK;
241 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
242 sp->mmio_cached = true;
244 trace_mark_mmio_spte(sptep, gfn, access, 0);
245 mmu_spte_set(sptep, mask);
248 static bool is_mmio_spte(u64 spte)
250 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
253 static gfn_t get_mmio_spte_gfn(u64 spte)
255 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
256 return (spte & ~mask) >> PAGE_SHIFT;
259 static unsigned get_mmio_spte_access(u64 spte)
261 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
262 return (spte & ~mask) & ~PAGE_MASK;
265 static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
266 pfn_t pfn, unsigned access)
268 if (unlikely(is_noslot_pfn(pfn))) {
269 mark_mmio_spte(kvm, sptep, gfn, access);
276 static inline u64 rsvd_bits(int s, int e)
278 return ((1ULL << (e - s + 1)) - 1) << s;
281 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
282 u64 dirty_mask, u64 nx_mask, u64 x_mask)
284 shadow_user_mask = user_mask;
285 shadow_accessed_mask = accessed_mask;
286 shadow_dirty_mask = dirty_mask;
287 shadow_nx_mask = nx_mask;
288 shadow_x_mask = x_mask;
290 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
292 static int is_cpuid_PSE36(void)
297 static int is_nx(struct kvm_vcpu *vcpu)
299 return vcpu->arch.efer & EFER_NX;
302 static int is_shadow_present_pte(u64 pte)
304 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
307 static int is_large_pte(u64 pte)
309 return pte & PT_PAGE_SIZE_MASK;
312 static int is_dirty_gpte(unsigned long pte)
314 return pte & PT_DIRTY_MASK;
317 static int is_rmap_spte(u64 pte)
319 return is_shadow_present_pte(pte);
322 static int is_last_spte(u64 pte, int level)
324 if (level == PT_PAGE_TABLE_LEVEL)
326 if (is_large_pte(pte))
331 static pfn_t spte_to_pfn(u64 pte)
333 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
336 static gfn_t pse36_gfn_delta(u32 gpte)
338 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
340 return (gpte & PT32_DIR_PSE36_MASK) << shift;
344 static void __set_spte(u64 *sptep, u64 spte)
349 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
354 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
356 return xchg(sptep, spte);
359 static u64 __get_spte_lockless(u64 *sptep)
361 return ACCESS_ONCE(*sptep);
364 static bool __check_direct_spte_mmio_pf(u64 spte)
366 /* It is valid if the spte is zapped. */
378 static void count_spte_clear(u64 *sptep, u64 spte)
380 struct kvm_mmu_page *sp = page_header(__pa(sptep));
382 if (is_shadow_present_pte(spte))
385 /* Ensure the spte is completely set before we increase the count */
387 sp->clear_spte_count++;
390 static void __set_spte(u64 *sptep, u64 spte)
392 union split_spte *ssptep, sspte;
394 ssptep = (union split_spte *)sptep;
395 sspte = (union split_spte)spte;
397 ssptep->spte_high = sspte.spte_high;
400 * If we map the spte from nonpresent to present, We should store
401 * the high bits firstly, then set present bit, so cpu can not
402 * fetch this spte while we are setting the spte.
406 ssptep->spte_low = sspte.spte_low;
409 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
411 union split_spte *ssptep, sspte;
413 ssptep = (union split_spte *)sptep;
414 sspte = (union split_spte)spte;
416 ssptep->spte_low = sspte.spte_low;
419 * If we map the spte from present to nonpresent, we should clear
420 * present bit firstly to avoid vcpu fetch the old high bits.
424 ssptep->spte_high = sspte.spte_high;
425 count_spte_clear(sptep, spte);
428 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
430 union split_spte *ssptep, sspte, orig;
432 ssptep = (union split_spte *)sptep;
433 sspte = (union split_spte)spte;
435 /* xchg acts as a barrier before the setting of the high bits */
436 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
437 orig.spte_high = ssptep->spte_high;
438 ssptep->spte_high = sspte.spte_high;
439 count_spte_clear(sptep, spte);
445 * The idea using the light way get the spte on x86_32 guest is from
446 * gup_get_pte(arch/x86/mm/gup.c).
447 * The difference is we can not catch the spte tlb flush if we leave
448 * guest mode, so we emulate it by increase clear_spte_count when spte
451 static u64 __get_spte_lockless(u64 *sptep)
453 struct kvm_mmu_page *sp = page_header(__pa(sptep));
454 union split_spte spte, *orig = (union split_spte *)sptep;
458 count = sp->clear_spte_count;
461 spte.spte_low = orig->spte_low;
464 spte.spte_high = orig->spte_high;
467 if (unlikely(spte.spte_low != orig->spte_low ||
468 count != sp->clear_spte_count))
474 static bool __check_direct_spte_mmio_pf(u64 spte)
476 union split_spte sspte = (union split_spte)spte;
477 u32 high_mmio_mask = shadow_mmio_mask >> 32;
479 /* It is valid if the spte is zapped. */
483 /* It is valid if the spte is being zapped. */
484 if (sspte.spte_low == 0ull &&
485 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
492 static bool spte_is_locklessly_modifiable(u64 spte)
494 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
495 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
498 static bool spte_has_volatile_bits(u64 spte)
501 * Always atomicly update spte if it can be updated
502 * out of mmu-lock, it can ensure dirty bit is not lost,
503 * also, it can help us to get a stable is_writable_pte()
504 * to ensure tlb flush is not missed.
506 if (spte_is_locklessly_modifiable(spte))
509 if (!shadow_accessed_mask)
512 if (!is_shadow_present_pte(spte))
515 if ((spte & shadow_accessed_mask) &&
516 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
522 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
524 return (old_spte & bit_mask) && !(new_spte & bit_mask);
527 /* Rules for using mmu_spte_set:
528 * Set the sptep from nonpresent to present.
529 * Note: the sptep being assigned *must* be either not present
530 * or in a state where the hardware will not attempt to update
533 static void mmu_spte_set(u64 *sptep, u64 new_spte)
535 WARN_ON(is_shadow_present_pte(*sptep));
536 __set_spte(sptep, new_spte);
539 /* Rules for using mmu_spte_update:
540 * Update the state bits, it means the mapped pfn is not changged.
542 * Whenever we overwrite a writable spte with a read-only one we
543 * should flush remote TLBs. Otherwise rmap_write_protect
544 * will find a read-only spte, even though the writable spte
545 * might be cached on a CPU's TLB, the return value indicates this
548 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
550 u64 old_spte = *sptep;
553 WARN_ON(!is_rmap_spte(new_spte));
555 if (!is_shadow_present_pte(old_spte)) {
556 mmu_spte_set(sptep, new_spte);
560 if (!spte_has_volatile_bits(old_spte))
561 __update_clear_spte_fast(sptep, new_spte);
563 old_spte = __update_clear_spte_slow(sptep, new_spte);
566 * For the spte updated out of mmu-lock is safe, since
567 * we always atomicly update it, see the comments in
568 * spte_has_volatile_bits().
570 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
573 if (!shadow_accessed_mask)
576 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
577 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
578 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
579 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
585 * Rules for using mmu_spte_clear_track_bits:
586 * It sets the sptep from present to nonpresent, and track the
587 * state bits, it is used to clear the last level sptep.
589 static int mmu_spte_clear_track_bits(u64 *sptep)
592 u64 old_spte = *sptep;
594 if (!spte_has_volatile_bits(old_spte))
595 __update_clear_spte_fast(sptep, 0ull);
597 old_spte = __update_clear_spte_slow(sptep, 0ull);
599 if (!is_rmap_spte(old_spte))
602 pfn = spte_to_pfn(old_spte);
605 * KVM does not hold the refcount of the page used by
606 * kvm mmu, before reclaiming the page, we should
607 * unmap it from mmu first.
609 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
611 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
612 kvm_set_pfn_accessed(pfn);
613 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
614 kvm_set_pfn_dirty(pfn);
619 * Rules for using mmu_spte_clear_no_track:
620 * Directly clear spte without caring the state bits of sptep,
621 * it is used to set the upper level spte.
623 static void mmu_spte_clear_no_track(u64 *sptep)
625 __update_clear_spte_fast(sptep, 0ull);
628 static u64 mmu_spte_get_lockless(u64 *sptep)
630 return __get_spte_lockless(sptep);
633 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
636 * Prevent page table teardown by making any free-er wait during
637 * kvm_flush_remote_tlbs() IPI to all active vcpus.
640 vcpu->mode = READING_SHADOW_PAGE_TABLES;
642 * Make sure a following spte read is not reordered ahead of the write
648 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
651 * Make sure the write to vcpu->mode is not reordered in front of
652 * reads to sptes. If it does, kvm_commit_zap_page() can see us
653 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
656 vcpu->mode = OUTSIDE_GUEST_MODE;
660 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
661 struct kmem_cache *base_cache, int min)
665 if (cache->nobjs >= min)
667 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
668 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
671 cache->objects[cache->nobjs++] = obj;
676 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
681 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
682 struct kmem_cache *cache)
685 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
688 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
693 if (cache->nobjs >= min)
695 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
696 page = (void *)__get_free_page(GFP_KERNEL);
699 cache->objects[cache->nobjs++] = page;
704 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
707 free_page((unsigned long)mc->objects[--mc->nobjs]);
710 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
715 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
718 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
721 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
722 mmu_page_header_cache, 4);
727 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
729 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
730 pte_list_desc_cache);
731 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
732 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
733 mmu_page_header_cache);
736 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
741 p = mc->objects[--mc->nobjs];
745 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
747 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
750 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
752 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
755 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
757 if (!sp->role.direct)
758 return sp->gfns[index];
760 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
763 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
766 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
768 sp->gfns[index] = gfn;
772 * Return the pointer to the large page information for a given gfn,
773 * handling slots that are not large page aligned.
775 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
776 struct kvm_memory_slot *slot,
781 idx = gfn_to_index(gfn, slot->base_gfn, level);
782 return &slot->arch.lpage_info[level - 2][idx];
785 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
787 struct kvm_memory_slot *slot;
788 struct kvm_lpage_info *linfo;
791 slot = gfn_to_memslot(kvm, gfn);
792 for (i = PT_DIRECTORY_LEVEL;
793 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
794 linfo = lpage_info_slot(gfn, slot, i);
795 linfo->write_count += 1;
797 kvm->arch.indirect_shadow_pages++;
800 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
802 struct kvm_memory_slot *slot;
803 struct kvm_lpage_info *linfo;
806 slot = gfn_to_memslot(kvm, gfn);
807 for (i = PT_DIRECTORY_LEVEL;
808 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
809 linfo = lpage_info_slot(gfn, slot, i);
810 linfo->write_count -= 1;
811 WARN_ON(linfo->write_count < 0);
813 kvm->arch.indirect_shadow_pages--;
816 static int has_wrprotected_page(struct kvm *kvm,
820 struct kvm_memory_slot *slot;
821 struct kvm_lpage_info *linfo;
823 slot = gfn_to_memslot(kvm, gfn);
825 linfo = lpage_info_slot(gfn, slot, level);
826 return linfo->write_count;
832 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
834 unsigned long page_size;
837 page_size = kvm_host_page_size(kvm, gfn);
839 for (i = PT_PAGE_TABLE_LEVEL;
840 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
841 if (page_size >= KVM_HPAGE_SIZE(i))
850 static struct kvm_memory_slot *
851 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
854 struct kvm_memory_slot *slot;
856 slot = gfn_to_memslot(vcpu->kvm, gfn);
857 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
858 (no_dirty_log && slot->dirty_bitmap))
864 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
866 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
869 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
871 int host_level, level, max_level;
873 host_level = host_mapping_level(vcpu->kvm, large_gfn);
875 if (host_level == PT_PAGE_TABLE_LEVEL)
878 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
880 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
881 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
888 * Pte mapping structures:
890 * If pte_list bit zero is zero, then pte_list point to the spte.
892 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
893 * pte_list_desc containing more mappings.
895 * Returns the number of pte entries before the spte was added or zero if
896 * the spte was not added.
899 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
900 unsigned long *pte_list)
902 struct pte_list_desc *desc;
906 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
907 *pte_list = (unsigned long)spte;
908 } else if (!(*pte_list & 1)) {
909 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
910 desc = mmu_alloc_pte_list_desc(vcpu);
911 desc->sptes[0] = (u64 *)*pte_list;
912 desc->sptes[1] = spte;
913 *pte_list = (unsigned long)desc | 1;
916 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
917 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
918 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
920 count += PTE_LIST_EXT;
922 if (desc->sptes[PTE_LIST_EXT-1]) {
923 desc->more = mmu_alloc_pte_list_desc(vcpu);
926 for (i = 0; desc->sptes[i]; ++i)
928 desc->sptes[i] = spte;
934 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
935 int i, struct pte_list_desc *prev_desc)
939 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
941 desc->sptes[i] = desc->sptes[j];
942 desc->sptes[j] = NULL;
945 if (!prev_desc && !desc->more)
946 *pte_list = (unsigned long)desc->sptes[0];
949 prev_desc->more = desc->more;
951 *pte_list = (unsigned long)desc->more | 1;
952 mmu_free_pte_list_desc(desc);
955 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
957 struct pte_list_desc *desc;
958 struct pte_list_desc *prev_desc;
962 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
964 } else if (!(*pte_list & 1)) {
965 rmap_printk("pte_list_remove: %p 1->0\n", spte);
966 if ((u64 *)*pte_list != spte) {
967 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
972 rmap_printk("pte_list_remove: %p many->many\n", spte);
973 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
976 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
977 if (desc->sptes[i] == spte) {
978 pte_list_desc_remove_entry(pte_list,
986 pr_err("pte_list_remove: %p many->many\n", spte);
991 typedef void (*pte_list_walk_fn) (u64 *spte);
992 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
994 struct pte_list_desc *desc;
1000 if (!(*pte_list & 1))
1001 return fn((u64 *)*pte_list);
1003 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1005 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1011 static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1012 struct kvm_memory_slot *slot)
1016 idx = gfn_to_index(gfn, slot->base_gfn, level);
1017 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1021 * Take gfn and return the reverse mapping to it.
1023 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1025 struct kvm_memory_slot *slot;
1027 slot = gfn_to_memslot(kvm, gfn);
1028 return __gfn_to_rmap(gfn, level, slot);
1031 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1033 struct kvm_mmu_memory_cache *cache;
1035 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1036 return mmu_memory_cache_free_objects(cache);
1039 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1041 struct kvm_mmu_page *sp;
1042 unsigned long *rmapp;
1044 sp = page_header(__pa(spte));
1045 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1046 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1047 return pte_list_add(vcpu, spte, rmapp);
1050 static void rmap_remove(struct kvm *kvm, u64 *spte)
1052 struct kvm_mmu_page *sp;
1054 unsigned long *rmapp;
1056 sp = page_header(__pa(spte));
1057 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1058 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1059 pte_list_remove(spte, rmapp);
1063 * Used by the following functions to iterate through the sptes linked by a
1064 * rmap. All fields are private and not assumed to be used outside.
1066 struct rmap_iterator {
1067 /* private fields */
1068 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1069 int pos; /* index of the sptep */
1073 * Iteration must be started by this function. This should also be used after
1074 * removing/dropping sptes from the rmap link because in such cases the
1075 * information in the itererator may not be valid.
1077 * Returns sptep if found, NULL otherwise.
1079 static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1089 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1091 return iter->desc->sptes[iter->pos];
1095 * Must be used with a valid iterator: e.g. after rmap_get_first().
1097 * Returns sptep if found, NULL otherwise.
1099 static u64 *rmap_get_next(struct rmap_iterator *iter)
1102 if (iter->pos < PTE_LIST_EXT - 1) {
1106 sptep = iter->desc->sptes[iter->pos];
1111 iter->desc = iter->desc->more;
1115 /* desc->sptes[0] cannot be NULL */
1116 return iter->desc->sptes[iter->pos];
1123 static void drop_spte(struct kvm *kvm, u64 *sptep)
1125 if (mmu_spte_clear_track_bits(sptep))
1126 rmap_remove(kvm, sptep);
1130 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1132 if (is_large_pte(*sptep)) {
1133 WARN_ON(page_header(__pa(sptep))->role.level ==
1134 PT_PAGE_TABLE_LEVEL);
1135 drop_spte(kvm, sptep);
1143 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1145 if (__drop_large_spte(vcpu->kvm, sptep))
1146 kvm_flush_remote_tlbs(vcpu->kvm);
1150 * Write-protect on the specified @sptep, @pt_protect indicates whether
1151 * spte writ-protection is caused by protecting shadow page table.
1152 * @flush indicates whether tlb need be flushed.
1154 * Note: write protection is difference between drity logging and spte
1156 * - for dirty logging, the spte can be set to writable at anytime if
1157 * its dirty bitmap is properly set.
1158 * - for spte protection, the spte can be writable only after unsync-ing
1161 * Return true if the spte is dropped.
1164 spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1168 if (!is_writable_pte(spte) &&
1169 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1172 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1174 if (__drop_large_spte(kvm, sptep)) {
1180 spte &= ~SPTE_MMU_WRITEABLE;
1181 spte = spte & ~PT_WRITABLE_MASK;
1183 *flush |= mmu_spte_update(sptep, spte);
1187 static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1191 struct rmap_iterator iter;
1194 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1195 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1196 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1197 sptep = rmap_get_first(*rmapp, &iter);
1201 sptep = rmap_get_next(&iter);
1208 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1209 * @kvm: kvm instance
1210 * @slot: slot to protect
1211 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1212 * @mask: indicates which pages we should protect
1214 * Used when we do not need to care about huge page mappings: e.g. during dirty
1215 * logging we do not have any such mappings.
1217 void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1218 struct kvm_memory_slot *slot,
1219 gfn_t gfn_offset, unsigned long mask)
1221 unsigned long *rmapp;
1224 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1225 PT_PAGE_TABLE_LEVEL, slot);
1226 __rmap_write_protect(kvm, rmapp, false);
1228 /* clear the first set bit */
1233 static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1235 struct kvm_memory_slot *slot;
1236 unsigned long *rmapp;
1238 bool write_protected = false;
1240 slot = gfn_to_memslot(kvm, gfn);
1242 for (i = PT_PAGE_TABLE_LEVEL;
1243 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1244 rmapp = __gfn_to_rmap(gfn, i, slot);
1245 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1248 return write_protected;
1251 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1252 struct kvm_memory_slot *slot, unsigned long data)
1255 struct rmap_iterator iter;
1256 int need_tlb_flush = 0;
1258 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1259 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1260 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1262 drop_spte(kvm, sptep);
1266 return need_tlb_flush;
1269 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1270 struct kvm_memory_slot *slot, unsigned long data)
1273 struct rmap_iterator iter;
1276 pte_t *ptep = (pte_t *)data;
1279 WARN_ON(pte_huge(*ptep));
1280 new_pfn = pte_pfn(*ptep);
1282 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1283 BUG_ON(!is_shadow_present_pte(*sptep));
1284 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1288 if (pte_write(*ptep)) {
1289 drop_spte(kvm, sptep);
1290 sptep = rmap_get_first(*rmapp, &iter);
1292 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1293 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1295 new_spte &= ~PT_WRITABLE_MASK;
1296 new_spte &= ~SPTE_HOST_WRITEABLE;
1297 new_spte &= ~shadow_accessed_mask;
1299 mmu_spte_clear_track_bits(sptep);
1300 mmu_spte_set(sptep, new_spte);
1301 sptep = rmap_get_next(&iter);
1306 kvm_flush_remote_tlbs(kvm);
1311 static int kvm_handle_hva_range(struct kvm *kvm,
1312 unsigned long start,
1315 int (*handler)(struct kvm *kvm,
1316 unsigned long *rmapp,
1317 struct kvm_memory_slot *slot,
1318 unsigned long data))
1322 struct kvm_memslots *slots;
1323 struct kvm_memory_slot *memslot;
1325 slots = kvm_memslots(kvm);
1327 kvm_for_each_memslot(memslot, slots) {
1328 unsigned long hva_start, hva_end;
1329 gfn_t gfn_start, gfn_end;
1331 hva_start = max(start, memslot->userspace_addr);
1332 hva_end = min(end, memslot->userspace_addr +
1333 (memslot->npages << PAGE_SHIFT));
1334 if (hva_start >= hva_end)
1337 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1338 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1340 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1341 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1343 for (j = PT_PAGE_TABLE_LEVEL;
1344 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1345 unsigned long idx, idx_end;
1346 unsigned long *rmapp;
1349 * {idx(page_j) | page_j intersects with
1350 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1352 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1353 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1355 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1357 for (; idx <= idx_end; ++idx)
1358 ret |= handler(kvm, rmapp++, memslot, data);
1365 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1367 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1368 struct kvm_memory_slot *slot,
1369 unsigned long data))
1371 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1374 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1376 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1379 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1381 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1384 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1386 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1389 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1390 struct kvm_memory_slot *slot, unsigned long data)
1393 struct rmap_iterator uninitialized_var(iter);
1397 * In case of absence of EPT Access and Dirty Bits supports,
1398 * emulate the accessed bit for EPT, by checking if this page has
1399 * an EPT mapping, and clearing it if it does. On the next access,
1400 * a new EPT mapping will be established.
1401 * This has some overhead, but not as much as the cost of swapping
1402 * out actively used pages or breaking up actively used hugepages.
1404 if (!shadow_accessed_mask) {
1405 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1409 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1410 sptep = rmap_get_next(&iter)) {
1411 BUG_ON(!is_shadow_present_pte(*sptep));
1413 if (*sptep & shadow_accessed_mask) {
1415 clear_bit((ffs(shadow_accessed_mask) - 1),
1416 (unsigned long *)sptep);
1420 /* @data has hva passed to kvm_age_hva(). */
1421 trace_kvm_age_page(data, slot, young);
1425 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1426 struct kvm_memory_slot *slot, unsigned long data)
1429 struct rmap_iterator iter;
1433 * If there's no access bit in the secondary pte set by the
1434 * hardware it's up to gup-fast/gup to set the access bit in
1435 * the primary pte or in the page structure.
1437 if (!shadow_accessed_mask)
1440 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1441 sptep = rmap_get_next(&iter)) {
1442 BUG_ON(!is_shadow_present_pte(*sptep));
1444 if (*sptep & shadow_accessed_mask) {
1453 #define RMAP_RECYCLE_THRESHOLD 1000
1455 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1457 unsigned long *rmapp;
1458 struct kvm_mmu_page *sp;
1460 sp = page_header(__pa(spte));
1462 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1464 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1465 kvm_flush_remote_tlbs(vcpu->kvm);
1468 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1470 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1473 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1475 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1479 static int is_empty_shadow_page(u64 *spt)
1484 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1485 if (is_shadow_present_pte(*pos)) {
1486 printk(KERN_ERR "%s: %p %llx\n", __func__,
1495 * This value is the sum of all of the kvm instances's
1496 * kvm->arch.n_used_mmu_pages values. We need a global,
1497 * aggregate version in order to make the slab shrinker
1500 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1502 kvm->arch.n_used_mmu_pages += nr;
1503 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1506 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1508 ASSERT(is_empty_shadow_page(sp->spt));
1509 hlist_del(&sp->hash_link);
1510 list_del(&sp->link);
1511 free_page((unsigned long)sp->spt);
1512 if (!sp->role.direct)
1513 free_page((unsigned long)sp->gfns);
1514 kmem_cache_free(mmu_page_header_cache, sp);
1517 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1519 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1522 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1523 struct kvm_mmu_page *sp, u64 *parent_pte)
1528 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1531 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1534 pte_list_remove(parent_pte, &sp->parent_ptes);
1537 static void drop_parent_pte(struct kvm_mmu_page *sp,
1540 mmu_page_remove_parent_pte(sp, parent_pte);
1541 mmu_spte_clear_no_track(parent_pte);
1544 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1545 u64 *parent_pte, int direct)
1547 struct kvm_mmu_page *sp;
1549 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1550 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1552 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1553 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1556 * The active_mmu_pages list is the FIFO list, do not move the
1557 * page until it is zapped. kvm_zap_obsolete_pages depends on
1558 * this feature. See the comments in kvm_zap_obsolete_pages().
1560 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1561 sp->parent_ptes = 0;
1562 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1563 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1567 static void mark_unsync(u64 *spte);
1568 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1570 pte_list_walk(&sp->parent_ptes, mark_unsync);
1573 static void mark_unsync(u64 *spte)
1575 struct kvm_mmu_page *sp;
1578 sp = page_header(__pa(spte));
1579 index = spte - sp->spt;
1580 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1582 if (sp->unsync_children++)
1584 kvm_mmu_mark_parents_unsync(sp);
1587 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1588 struct kvm_mmu_page *sp)
1593 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1597 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1598 struct kvm_mmu_page *sp, u64 *spte,
1604 #define KVM_PAGE_ARRAY_NR 16
1606 struct kvm_mmu_pages {
1607 struct mmu_page_and_offset {
1608 struct kvm_mmu_page *sp;
1610 } page[KVM_PAGE_ARRAY_NR];
1614 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1620 for (i=0; i < pvec->nr; i++)
1621 if (pvec->page[i].sp == sp)
1624 pvec->page[pvec->nr].sp = sp;
1625 pvec->page[pvec->nr].idx = idx;
1627 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1630 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1631 struct kvm_mmu_pages *pvec)
1633 int i, ret, nr_unsync_leaf = 0;
1635 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1636 struct kvm_mmu_page *child;
1637 u64 ent = sp->spt[i];
1639 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1640 goto clear_child_bitmap;
1642 child = page_header(ent & PT64_BASE_ADDR_MASK);
1644 if (child->unsync_children) {
1645 if (mmu_pages_add(pvec, child, i))
1648 ret = __mmu_unsync_walk(child, pvec);
1650 goto clear_child_bitmap;
1652 nr_unsync_leaf += ret;
1655 } else if (child->unsync) {
1657 if (mmu_pages_add(pvec, child, i))
1660 goto clear_child_bitmap;
1665 __clear_bit(i, sp->unsync_child_bitmap);
1666 sp->unsync_children--;
1667 WARN_ON((int)sp->unsync_children < 0);
1671 return nr_unsync_leaf;
1674 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1675 struct kvm_mmu_pages *pvec)
1677 if (!sp->unsync_children)
1680 mmu_pages_add(pvec, sp, 0);
1681 return __mmu_unsync_walk(sp, pvec);
1684 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1686 WARN_ON(!sp->unsync);
1687 trace_kvm_mmu_sync_page(sp);
1689 --kvm->stat.mmu_unsync;
1692 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1693 struct list_head *invalid_list);
1694 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1695 struct list_head *invalid_list);
1698 * NOTE: we should pay more attention on the zapped-obsolete page
1699 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1700 * since it has been deleted from active_mmu_pages but still can be found
1703 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1704 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1705 * all the obsolete pages.
1707 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1708 hlist_for_each_entry(_sp, \
1709 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1710 if ((_sp)->gfn != (_gfn)) {} else
1712 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1713 for_each_gfn_sp(_kvm, _sp, _gfn) \
1714 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1716 /* @sp->gfn should be write-protected at the call site */
1717 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1718 struct list_head *invalid_list, bool clear_unsync)
1720 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1721 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1726 kvm_unlink_unsync_page(vcpu->kvm, sp);
1728 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1729 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1733 kvm_mmu_flush_tlb(vcpu);
1737 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1738 struct kvm_mmu_page *sp)
1740 LIST_HEAD(invalid_list);
1743 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1745 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1750 #ifdef CONFIG_KVM_MMU_AUDIT
1751 #include "mmu_audit.c"
1753 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1754 static void mmu_audit_disable(void) { }
1757 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1758 struct list_head *invalid_list)
1760 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1763 /* @gfn should be write-protected at the call site */
1764 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1766 struct kvm_mmu_page *s;
1767 LIST_HEAD(invalid_list);
1770 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1774 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1775 kvm_unlink_unsync_page(vcpu->kvm, s);
1776 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1777 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1778 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1784 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1786 kvm_mmu_flush_tlb(vcpu);
1789 struct mmu_page_path {
1790 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1791 unsigned int idx[PT64_ROOT_LEVEL-1];
1794 #define for_each_sp(pvec, sp, parents, i) \
1795 for (i = mmu_pages_next(&pvec, &parents, -1), \
1796 sp = pvec.page[i].sp; \
1797 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1798 i = mmu_pages_next(&pvec, &parents, i))
1800 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1801 struct mmu_page_path *parents,
1806 for (n = i+1; n < pvec->nr; n++) {
1807 struct kvm_mmu_page *sp = pvec->page[n].sp;
1809 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1810 parents->idx[0] = pvec->page[n].idx;
1814 parents->parent[sp->role.level-2] = sp;
1815 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1821 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1823 struct kvm_mmu_page *sp;
1824 unsigned int level = 0;
1827 unsigned int idx = parents->idx[level];
1829 sp = parents->parent[level];
1833 --sp->unsync_children;
1834 WARN_ON((int)sp->unsync_children < 0);
1835 __clear_bit(idx, sp->unsync_child_bitmap);
1837 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1840 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1841 struct mmu_page_path *parents,
1842 struct kvm_mmu_pages *pvec)
1844 parents->parent[parent->role.level-1] = NULL;
1848 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1849 struct kvm_mmu_page *parent)
1852 struct kvm_mmu_page *sp;
1853 struct mmu_page_path parents;
1854 struct kvm_mmu_pages pages;
1855 LIST_HEAD(invalid_list);
1857 kvm_mmu_pages_init(parent, &parents, &pages);
1858 while (mmu_unsync_walk(parent, &pages)) {
1859 bool protected = false;
1861 for_each_sp(pages, sp, parents, i)
1862 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1865 kvm_flush_remote_tlbs(vcpu->kvm);
1867 for_each_sp(pages, sp, parents, i) {
1868 kvm_sync_page(vcpu, sp, &invalid_list);
1869 mmu_pages_clear_parents(&parents);
1871 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1872 cond_resched_lock(&vcpu->kvm->mmu_lock);
1873 kvm_mmu_pages_init(parent, &parents, &pages);
1877 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1881 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1885 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1887 sp->write_flooding_count = 0;
1890 static void clear_sp_write_flooding_count(u64 *spte)
1892 struct kvm_mmu_page *sp = page_header(__pa(spte));
1894 __clear_sp_write_flooding_count(sp);
1897 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1899 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1902 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1910 union kvm_mmu_page_role role;
1912 struct kvm_mmu_page *sp;
1913 bool need_sync = false;
1915 role = vcpu->arch.mmu.base_role;
1917 role.direct = direct;
1920 role.access = access;
1921 if (!vcpu->arch.mmu.direct_map
1922 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1923 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1924 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1925 role.quadrant = quadrant;
1927 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1928 if (is_obsolete_sp(vcpu->kvm, sp))
1931 if (!need_sync && sp->unsync)
1934 if (sp->role.word != role.word)
1937 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1940 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1941 if (sp->unsync_children) {
1942 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1943 kvm_mmu_mark_parents_unsync(sp);
1944 } else if (sp->unsync)
1945 kvm_mmu_mark_parents_unsync(sp);
1947 __clear_sp_write_flooding_count(sp);
1948 trace_kvm_mmu_get_page(sp, false);
1951 ++vcpu->kvm->stat.mmu_cache_miss;
1952 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1957 hlist_add_head(&sp->hash_link,
1958 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1960 if (rmap_write_protect(vcpu->kvm, gfn))
1961 kvm_flush_remote_tlbs(vcpu->kvm);
1962 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1963 kvm_sync_pages(vcpu, gfn);
1965 account_shadowed(vcpu->kvm, gfn);
1967 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1968 init_shadow_page_table(sp);
1969 trace_kvm_mmu_get_page(sp, true);
1973 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1974 struct kvm_vcpu *vcpu, u64 addr)
1976 iterator->addr = addr;
1977 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1978 iterator->level = vcpu->arch.mmu.shadow_root_level;
1980 if (iterator->level == PT64_ROOT_LEVEL &&
1981 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1982 !vcpu->arch.mmu.direct_map)
1985 if (iterator->level == PT32E_ROOT_LEVEL) {
1986 iterator->shadow_addr
1987 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1988 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1990 if (!iterator->shadow_addr)
1991 iterator->level = 0;
1995 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1997 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2000 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2001 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2005 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2008 if (is_last_spte(spte, iterator->level)) {
2009 iterator->level = 0;
2013 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2017 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2019 return __shadow_walk_next(iterator, *iterator->sptep);
2022 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
2026 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2027 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2029 mmu_spte_set(sptep, spte);
2032 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2033 unsigned direct_access)
2035 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2036 struct kvm_mmu_page *child;
2039 * For the direct sp, if the guest pte's dirty bit
2040 * changed form clean to dirty, it will corrupt the
2041 * sp's access: allow writable in the read-only sp,
2042 * so we should update the spte at this point to get
2043 * a new sp with the correct access.
2045 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2046 if (child->role.access == direct_access)
2049 drop_parent_pte(child, sptep);
2050 kvm_flush_remote_tlbs(vcpu->kvm);
2054 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2058 struct kvm_mmu_page *child;
2061 if (is_shadow_present_pte(pte)) {
2062 if (is_last_spte(pte, sp->role.level)) {
2063 drop_spte(kvm, spte);
2064 if (is_large_pte(pte))
2067 child = page_header(pte & PT64_BASE_ADDR_MASK);
2068 drop_parent_pte(child, spte);
2073 if (is_mmio_spte(pte))
2074 mmu_spte_clear_no_track(spte);
2079 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2080 struct kvm_mmu_page *sp)
2084 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2085 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2088 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2090 mmu_page_remove_parent_pte(sp, parent_pte);
2093 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2096 struct rmap_iterator iter;
2098 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2099 drop_parent_pte(sp, sptep);
2102 static int mmu_zap_unsync_children(struct kvm *kvm,
2103 struct kvm_mmu_page *parent,
2104 struct list_head *invalid_list)
2107 struct mmu_page_path parents;
2108 struct kvm_mmu_pages pages;
2110 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2113 kvm_mmu_pages_init(parent, &parents, &pages);
2114 while (mmu_unsync_walk(parent, &pages)) {
2115 struct kvm_mmu_page *sp;
2117 for_each_sp(pages, sp, parents, i) {
2118 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2119 mmu_pages_clear_parents(&parents);
2122 kvm_mmu_pages_init(parent, &parents, &pages);
2128 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2129 struct list_head *invalid_list)
2133 trace_kvm_mmu_prepare_zap_page(sp);
2134 ++kvm->stat.mmu_shadow_zapped;
2135 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2136 kvm_mmu_page_unlink_children(kvm, sp);
2137 kvm_mmu_unlink_parents(kvm, sp);
2139 if (!sp->role.invalid && !sp->role.direct)
2140 unaccount_shadowed(kvm, sp->gfn);
2143 kvm_unlink_unsync_page(kvm, sp);
2144 if (!sp->root_count) {
2147 list_move(&sp->link, invalid_list);
2148 kvm_mod_used_mmu_pages(kvm, -1);
2150 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2153 * The obsolete pages can not be used on any vcpus.
2154 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2156 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2157 kvm_reload_remote_mmus(kvm);
2160 sp->role.invalid = 1;
2164 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2165 struct list_head *invalid_list)
2167 struct kvm_mmu_page *sp, *nsp;
2169 if (list_empty(invalid_list))
2173 * wmb: make sure everyone sees our modifications to the page tables
2174 * rmb: make sure we see changes to vcpu->mode
2179 * Wait for all vcpus to exit guest mode and/or lockless shadow
2182 kvm_flush_remote_tlbs(kvm);
2184 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2185 WARN_ON(!sp->role.invalid || sp->root_count);
2186 kvm_mmu_free_page(sp);
2190 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2191 struct list_head *invalid_list)
2193 struct kvm_mmu_page *sp;
2195 if (list_empty(&kvm->arch.active_mmu_pages))
2198 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2199 struct kvm_mmu_page, link);
2200 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2206 * Changing the number of mmu pages allocated to the vm
2207 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2209 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2211 LIST_HEAD(invalid_list);
2213 spin_lock(&kvm->mmu_lock);
2215 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2216 /* Need to free some mmu pages to achieve the goal. */
2217 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2218 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2221 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2222 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2225 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2227 spin_unlock(&kvm->mmu_lock);
2230 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2232 struct kvm_mmu_page *sp;
2233 LIST_HEAD(invalid_list);
2236 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2238 spin_lock(&kvm->mmu_lock);
2239 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2240 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2243 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2245 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2246 spin_unlock(&kvm->mmu_lock);
2250 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2253 * The function is based on mtrr_type_lookup() in
2254 * arch/x86/kernel/cpu/mtrr/generic.c
2256 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2261 u8 prev_match, curr_match;
2262 int num_var_ranges = KVM_NR_VAR_MTRR;
2264 if (!mtrr_state->enabled)
2267 /* Make end inclusive end, instead of exclusive */
2270 /* Look in fixed ranges. Just return the type as per start */
2271 if (mtrr_state->have_fixed && (start < 0x100000)) {
2274 if (start < 0x80000) {
2276 idx += (start >> 16);
2277 return mtrr_state->fixed_ranges[idx];
2278 } else if (start < 0xC0000) {
2280 idx += ((start - 0x80000) >> 14);
2281 return mtrr_state->fixed_ranges[idx];
2282 } else if (start < 0x1000000) {
2284 idx += ((start - 0xC0000) >> 12);
2285 return mtrr_state->fixed_ranges[idx];
2290 * Look in variable ranges
2291 * Look of multiple ranges matching this address and pick type
2292 * as per MTRR precedence
2294 if (!(mtrr_state->enabled & 2))
2295 return mtrr_state->def_type;
2298 for (i = 0; i < num_var_ranges; ++i) {
2299 unsigned short start_state, end_state;
2301 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2304 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2305 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2306 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2307 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2309 start_state = ((start & mask) == (base & mask));
2310 end_state = ((end & mask) == (base & mask));
2311 if (start_state != end_state)
2314 if ((start & mask) != (base & mask))
2317 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2318 if (prev_match == 0xFF) {
2319 prev_match = curr_match;
2323 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2324 curr_match == MTRR_TYPE_UNCACHABLE)
2325 return MTRR_TYPE_UNCACHABLE;
2327 if ((prev_match == MTRR_TYPE_WRBACK &&
2328 curr_match == MTRR_TYPE_WRTHROUGH) ||
2329 (prev_match == MTRR_TYPE_WRTHROUGH &&
2330 curr_match == MTRR_TYPE_WRBACK)) {
2331 prev_match = MTRR_TYPE_WRTHROUGH;
2332 curr_match = MTRR_TYPE_WRTHROUGH;
2335 if (prev_match != curr_match)
2336 return MTRR_TYPE_UNCACHABLE;
2339 if (prev_match != 0xFF)
2342 return mtrr_state->def_type;
2345 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2349 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2350 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2351 if (mtrr == 0xfe || mtrr == 0xff)
2352 mtrr = MTRR_TYPE_WRBACK;
2355 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2357 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2359 trace_kvm_mmu_unsync_page(sp);
2360 ++vcpu->kvm->stat.mmu_unsync;
2363 kvm_mmu_mark_parents_unsync(sp);
2366 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2368 struct kvm_mmu_page *s;
2370 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2373 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2374 __kvm_unsync_page(vcpu, s);
2378 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2381 struct kvm_mmu_page *s;
2382 bool need_unsync = false;
2384 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2388 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2395 kvm_unsync_pages(vcpu, gfn);
2399 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2400 unsigned pte_access, int level,
2401 gfn_t gfn, pfn_t pfn, bool speculative,
2402 bool can_unsync, bool host_writable)
2407 if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2410 spte = PT_PRESENT_MASK;
2412 spte |= shadow_accessed_mask;
2414 if (pte_access & ACC_EXEC_MASK)
2415 spte |= shadow_x_mask;
2417 spte |= shadow_nx_mask;
2419 if (pte_access & ACC_USER_MASK)
2420 spte |= shadow_user_mask;
2422 if (level > PT_PAGE_TABLE_LEVEL)
2423 spte |= PT_PAGE_SIZE_MASK;
2425 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2426 kvm_is_mmio_pfn(pfn));
2429 spte |= SPTE_HOST_WRITEABLE;
2431 pte_access &= ~ACC_WRITE_MASK;
2433 spte |= (u64)pfn << PAGE_SHIFT;
2435 if (pte_access & ACC_WRITE_MASK) {
2438 * Other vcpu creates new sp in the window between
2439 * mapping_level() and acquiring mmu-lock. We can
2440 * allow guest to retry the access, the mapping can
2441 * be fixed if guest refault.
2443 if (level > PT_PAGE_TABLE_LEVEL &&
2444 has_wrprotected_page(vcpu->kvm, gfn, level))
2447 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2450 * Optimization: for pte sync, if spte was writable the hash
2451 * lookup is unnecessary (and expensive). Write protection
2452 * is responsibility of mmu_get_page / kvm_sync_page.
2453 * Same reasoning can be applied to dirty page accounting.
2455 if (!can_unsync && is_writable_pte(*sptep))
2458 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2459 pgprintk("%s: found shadow page for %llx, marking ro\n",
2462 pte_access &= ~ACC_WRITE_MASK;
2463 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2467 if (pte_access & ACC_WRITE_MASK)
2468 mark_page_dirty(vcpu->kvm, gfn);
2471 if (mmu_spte_update(sptep, spte))
2472 kvm_flush_remote_tlbs(vcpu->kvm);
2477 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2478 unsigned pte_access, int write_fault, int *emulate,
2479 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2482 int was_rmapped = 0;
2485 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2486 *sptep, write_fault, gfn);
2488 if (is_rmap_spte(*sptep)) {
2490 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2491 * the parent of the now unreachable PTE.
2493 if (level > PT_PAGE_TABLE_LEVEL &&
2494 !is_large_pte(*sptep)) {
2495 struct kvm_mmu_page *child;
2498 child = page_header(pte & PT64_BASE_ADDR_MASK);
2499 drop_parent_pte(child, sptep);
2500 kvm_flush_remote_tlbs(vcpu->kvm);
2501 } else if (pfn != spte_to_pfn(*sptep)) {
2502 pgprintk("hfn old %llx new %llx\n",
2503 spte_to_pfn(*sptep), pfn);
2504 drop_spte(vcpu->kvm, sptep);
2505 kvm_flush_remote_tlbs(vcpu->kvm);
2510 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2511 true, host_writable)) {
2514 kvm_mmu_flush_tlb(vcpu);
2517 if (unlikely(is_mmio_spte(*sptep) && emulate))
2520 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2521 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2522 is_large_pte(*sptep)? "2MB" : "4kB",
2523 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2525 if (!was_rmapped && is_large_pte(*sptep))
2526 ++vcpu->kvm->stat.lpages;
2528 if (is_shadow_present_pte(*sptep)) {
2530 rmap_count = rmap_add(vcpu, sptep, gfn);
2531 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2532 rmap_recycle(vcpu, sptep, gfn);
2536 kvm_release_pfn_clean(pfn);
2539 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2541 mmu_free_roots(vcpu);
2544 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2548 bit7 = (gpte >> 7) & 1;
2549 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2552 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2555 struct kvm_memory_slot *slot;
2557 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2559 return KVM_PFN_ERR_FAULT;
2561 return gfn_to_pfn_memslot_atomic(slot, gfn);
2564 static bool prefetch_invalid_gpte(struct kvm_vcpu *vcpu,
2565 struct kvm_mmu_page *sp, u64 *spte,
2568 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
2571 if (!is_present_gpte(gpte))
2574 if (!(gpte & PT_ACCESSED_MASK))
2580 drop_spte(vcpu->kvm, spte);
2584 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2585 struct kvm_mmu_page *sp,
2586 u64 *start, u64 *end)
2588 struct page *pages[PTE_PREFETCH_NUM];
2589 unsigned access = sp->role.access;
2593 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2594 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2597 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2601 for (i = 0; i < ret; i++, gfn++, start++)
2602 mmu_set_spte(vcpu, start, access, 0, NULL,
2603 sp->role.level, gfn, page_to_pfn(pages[i]),
2609 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2610 struct kvm_mmu_page *sp, u64 *sptep)
2612 u64 *spte, *start = NULL;
2615 WARN_ON(!sp->role.direct);
2617 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2620 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2621 if (is_shadow_present_pte(*spte) || spte == sptep) {
2624 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2632 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2634 struct kvm_mmu_page *sp;
2637 * Since it's no accessed bit on EPT, it's no way to
2638 * distinguish between actually accessed translations
2639 * and prefetched, so disable pte prefetch if EPT is
2642 if (!shadow_accessed_mask)
2645 sp = page_header(__pa(sptep));
2646 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2649 __direct_pte_prefetch(vcpu, sp, sptep);
2652 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2653 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2656 struct kvm_shadow_walk_iterator iterator;
2657 struct kvm_mmu_page *sp;
2661 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2662 if (iterator.level == level) {
2663 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2664 write, &emulate, level, gfn, pfn,
2665 prefault, map_writable);
2666 direct_pte_prefetch(vcpu, iterator.sptep);
2667 ++vcpu->stat.pf_fixed;
2671 if (!is_shadow_present_pte(*iterator.sptep)) {
2672 u64 base_addr = iterator.addr;
2674 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2675 pseudo_gfn = base_addr >> PAGE_SHIFT;
2676 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2678 1, ACC_ALL, iterator.sptep);
2680 link_shadow_page(iterator.sptep, sp);
2686 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2690 info.si_signo = SIGBUS;
2692 info.si_code = BUS_MCEERR_AR;
2693 info.si_addr = (void __user *)address;
2694 info.si_addr_lsb = PAGE_SHIFT;
2696 send_sig_info(SIGBUS, &info, tsk);
2699 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2702 * Do not cache the mmio info caused by writing the readonly gfn
2703 * into the spte otherwise read access on readonly gfn also can
2704 * caused mmio page fault and treat it as mmio access.
2705 * Return 1 to tell kvm to emulate it.
2707 if (pfn == KVM_PFN_ERR_RO_FAULT)
2710 if (pfn == KVM_PFN_ERR_HWPOISON) {
2711 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2718 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2719 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2723 int level = *levelp;
2726 * Check if it's a transparent hugepage. If this would be an
2727 * hugetlbfs page, level wouldn't be set to
2728 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2731 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2732 level == PT_PAGE_TABLE_LEVEL &&
2733 PageTransCompound(pfn_to_page(pfn)) &&
2734 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2737 * mmu_notifier_retry was successful and we hold the
2738 * mmu_lock here, so the pmd can't become splitting
2739 * from under us, and in turn
2740 * __split_huge_page_refcount() can't run from under
2741 * us and we can safely transfer the refcount from
2742 * PG_tail to PG_head as we switch the pfn to tail to
2745 *levelp = level = PT_DIRECTORY_LEVEL;
2746 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2747 VM_BUG_ON((gfn & mask) != (pfn & mask));
2751 kvm_release_pfn_clean(pfn);
2759 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2760 pfn_t pfn, unsigned access, int *ret_val)
2764 /* The pfn is invalid, report the error! */
2765 if (unlikely(is_error_pfn(pfn))) {
2766 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2770 if (unlikely(is_noslot_pfn(pfn)))
2771 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2778 static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
2781 * #PF can be fast only if the shadow page table is present and it
2782 * is caused by write-protect, that means we just need change the
2783 * W bit of the spte which can be done out of mmu-lock.
2785 if (!(error_code & PFERR_PRESENT_MASK) ||
2786 !(error_code & PFERR_WRITE_MASK))
2793 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2795 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2798 WARN_ON(!sp->role.direct);
2801 * The gfn of direct spte is stable since it is calculated
2804 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2806 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2807 mark_page_dirty(vcpu->kvm, gfn);
2814 * - true: let the vcpu to access on the same address again.
2815 * - false: let the real page fault path to fix it.
2817 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2820 struct kvm_shadow_walk_iterator iterator;
2824 if (!page_fault_can_be_fast(vcpu, error_code))
2827 walk_shadow_page_lockless_begin(vcpu);
2828 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2829 if (!is_shadow_present_pte(spte) || iterator.level < level)
2833 * If the mapping has been changed, let the vcpu fault on the
2834 * same address again.
2836 if (!is_rmap_spte(spte)) {
2841 if (!is_last_spte(spte, level))
2845 * Check if it is a spurious fault caused by TLB lazily flushed.
2847 * Need not check the access of upper level table entries since
2848 * they are always ACC_ALL.
2850 if (is_writable_pte(spte)) {
2856 * Currently, to simplify the code, only the spte write-protected
2857 * by dirty-log can be fast fixed.
2859 if (!spte_is_locklessly_modifiable(spte))
2863 * Currently, fast page fault only works for direct mapping since
2864 * the gfn is not stable for indirect shadow page.
2865 * See Documentation/virtual/kvm/locking.txt to get more detail.
2867 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2869 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2871 walk_shadow_page_lockless_end(vcpu);
2876 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2877 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2878 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2880 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2881 gfn_t gfn, bool prefault)
2887 unsigned long mmu_seq;
2888 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2890 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2891 if (likely(!force_pt_level)) {
2892 level = mapping_level(vcpu, gfn);
2894 * This path builds a PAE pagetable - so we can map
2895 * 2mb pages at maximum. Therefore check if the level
2896 * is larger than that.
2898 if (level > PT_DIRECTORY_LEVEL)
2899 level = PT_DIRECTORY_LEVEL;
2901 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2903 level = PT_PAGE_TABLE_LEVEL;
2905 if (fast_page_fault(vcpu, v, level, error_code))
2908 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2911 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2914 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2917 spin_lock(&vcpu->kvm->mmu_lock);
2918 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2920 make_mmu_pages_available(vcpu);
2921 if (likely(!force_pt_level))
2922 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2923 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2925 spin_unlock(&vcpu->kvm->mmu_lock);
2931 spin_unlock(&vcpu->kvm->mmu_lock);
2932 kvm_release_pfn_clean(pfn);
2937 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2940 struct kvm_mmu_page *sp;
2941 LIST_HEAD(invalid_list);
2943 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2946 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2947 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2948 vcpu->arch.mmu.direct_map)) {
2949 hpa_t root = vcpu->arch.mmu.root_hpa;
2951 spin_lock(&vcpu->kvm->mmu_lock);
2952 sp = page_header(root);
2954 if (!sp->root_count && sp->role.invalid) {
2955 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2956 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2958 spin_unlock(&vcpu->kvm->mmu_lock);
2959 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2963 spin_lock(&vcpu->kvm->mmu_lock);
2964 for (i = 0; i < 4; ++i) {
2965 hpa_t root = vcpu->arch.mmu.pae_root[i];
2968 root &= PT64_BASE_ADDR_MASK;
2969 sp = page_header(root);
2971 if (!sp->root_count && sp->role.invalid)
2972 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2975 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2977 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2978 spin_unlock(&vcpu->kvm->mmu_lock);
2979 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2982 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2986 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2987 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2994 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2996 struct kvm_mmu_page *sp;
2999 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3000 spin_lock(&vcpu->kvm->mmu_lock);
3001 make_mmu_pages_available(vcpu);
3002 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3005 spin_unlock(&vcpu->kvm->mmu_lock);
3006 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3007 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3008 for (i = 0; i < 4; ++i) {
3009 hpa_t root = vcpu->arch.mmu.pae_root[i];
3011 ASSERT(!VALID_PAGE(root));
3012 spin_lock(&vcpu->kvm->mmu_lock);
3013 make_mmu_pages_available(vcpu);
3014 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3016 PT32_ROOT_LEVEL, 1, ACC_ALL,
3018 root = __pa(sp->spt);
3020 spin_unlock(&vcpu->kvm->mmu_lock);
3021 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3023 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3030 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3032 struct kvm_mmu_page *sp;
3037 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3039 if (mmu_check_root(vcpu, root_gfn))
3043 * Do we shadow a long mode page table? If so we need to
3044 * write-protect the guests page table root.
3046 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3047 hpa_t root = vcpu->arch.mmu.root_hpa;
3049 ASSERT(!VALID_PAGE(root));
3051 spin_lock(&vcpu->kvm->mmu_lock);
3052 make_mmu_pages_available(vcpu);
3053 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3055 root = __pa(sp->spt);
3057 spin_unlock(&vcpu->kvm->mmu_lock);
3058 vcpu->arch.mmu.root_hpa = root;
3063 * We shadow a 32 bit page table. This may be a legacy 2-level
3064 * or a PAE 3-level page table. In either case we need to be aware that
3065 * the shadow page table may be a PAE or a long mode page table.
3067 pm_mask = PT_PRESENT_MASK;
3068 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3069 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3071 for (i = 0; i < 4; ++i) {
3072 hpa_t root = vcpu->arch.mmu.pae_root[i];
3074 ASSERT(!VALID_PAGE(root));
3075 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3076 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3077 if (!is_present_gpte(pdptr)) {
3078 vcpu->arch.mmu.pae_root[i] = 0;
3081 root_gfn = pdptr >> PAGE_SHIFT;
3082 if (mmu_check_root(vcpu, root_gfn))
3085 spin_lock(&vcpu->kvm->mmu_lock);
3086 make_mmu_pages_available(vcpu);
3087 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3090 root = __pa(sp->spt);
3092 spin_unlock(&vcpu->kvm->mmu_lock);
3094 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3096 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3099 * If we shadow a 32 bit page table with a long mode page
3100 * table we enter this path.
3102 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3103 if (vcpu->arch.mmu.lm_root == NULL) {
3105 * The additional page necessary for this is only
3106 * allocated on demand.
3111 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3112 if (lm_root == NULL)
3115 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3117 vcpu->arch.mmu.lm_root = lm_root;
3120 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3126 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3128 if (vcpu->arch.mmu.direct_map)
3129 return mmu_alloc_direct_roots(vcpu);
3131 return mmu_alloc_shadow_roots(vcpu);
3134 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3137 struct kvm_mmu_page *sp;
3139 if (vcpu->arch.mmu.direct_map)
3142 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3145 vcpu_clear_mmio_info(vcpu, ~0ul);
3146 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3147 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3148 hpa_t root = vcpu->arch.mmu.root_hpa;
3149 sp = page_header(root);
3150 mmu_sync_children(vcpu, sp);
3151 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3154 for (i = 0; i < 4; ++i) {
3155 hpa_t root = vcpu->arch.mmu.pae_root[i];
3157 if (root && VALID_PAGE(root)) {
3158 root &= PT64_BASE_ADDR_MASK;
3159 sp = page_header(root);
3160 mmu_sync_children(vcpu, sp);
3163 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3166 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3168 spin_lock(&vcpu->kvm->mmu_lock);
3169 mmu_sync_roots(vcpu);
3170 spin_unlock(&vcpu->kvm->mmu_lock);
3173 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3174 u32 access, struct x86_exception *exception)
3177 exception->error_code = 0;
3181 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3183 struct x86_exception *exception)
3186 exception->error_code = 0;
3187 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3190 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3193 return vcpu_match_mmio_gpa(vcpu, addr);
3195 return vcpu_match_mmio_gva(vcpu, addr);
3200 * On direct hosts, the last spte is only allows two states
3201 * for mmio page fault:
3202 * - It is the mmio spte
3203 * - It is zapped or it is being zapped.
3205 * This function completely checks the spte when the last spte
3206 * is not the mmio spte.
3208 static bool check_direct_spte_mmio_pf(u64 spte)
3210 return __check_direct_spte_mmio_pf(spte);
3213 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3215 struct kvm_shadow_walk_iterator iterator;
3218 walk_shadow_page_lockless_begin(vcpu);
3219 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3220 if (!is_shadow_present_pte(spte))
3222 walk_shadow_page_lockless_end(vcpu);
3228 * If it is a real mmio page fault, return 1 and emulat the instruction
3229 * directly, return 0 to let CPU fault again on the address, -1 is
3230 * returned if bug is detected.
3232 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3236 if (quickly_check_mmio_pf(vcpu, addr, direct))
3239 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3241 if (is_mmio_spte(spte)) {
3242 gfn_t gfn = get_mmio_spte_gfn(spte);
3243 unsigned access = get_mmio_spte_access(spte);
3248 trace_handle_mmio_page_fault(addr, gfn, access);
3249 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3254 * It's ok if the gva is remapped by other cpus on shadow guest,
3255 * it's a BUG if the gfn is not a mmio page.
3257 if (direct && !check_direct_spte_mmio_pf(spte))
3261 * If the page table is zapped by other cpus, let CPU fault again on
3266 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3268 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3269 u32 error_code, bool direct)
3273 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3278 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3279 u32 error_code, bool prefault)
3284 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3286 if (unlikely(error_code & PFERR_RSVD_MASK))
3287 return handle_mmio_page_fault(vcpu, gva, error_code, true);
3289 r = mmu_topup_memory_caches(vcpu);
3294 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3296 gfn = gva >> PAGE_SHIFT;
3298 return nonpaging_map(vcpu, gva & PAGE_MASK,
3299 error_code, gfn, prefault);
3302 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3304 struct kvm_arch_async_pf arch;
3306 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3308 arch.direct_map = vcpu->arch.mmu.direct_map;
3309 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3311 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3314 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3316 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3317 kvm_event_needs_reinjection(vcpu)))
3320 return kvm_x86_ops->interrupt_allowed(vcpu);
3323 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3324 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3328 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3331 return false; /* *pfn has correct page already */
3333 if (!prefault && can_do_async_pf(vcpu)) {
3334 trace_kvm_try_async_get_page(gva, gfn);
3335 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3336 trace_kvm_async_pf_doublefault(gva, gfn);
3337 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3339 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3343 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3348 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3355 gfn_t gfn = gpa >> PAGE_SHIFT;
3356 unsigned long mmu_seq;
3357 int write = error_code & PFERR_WRITE_MASK;
3361 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3363 if (unlikely(error_code & PFERR_RSVD_MASK))
3364 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3366 r = mmu_topup_memory_caches(vcpu);
3370 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3371 if (likely(!force_pt_level)) {
3372 level = mapping_level(vcpu, gfn);
3373 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3375 level = PT_PAGE_TABLE_LEVEL;
3377 if (fast_page_fault(vcpu, gpa, level, error_code))
3380 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3383 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3386 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3389 spin_lock(&vcpu->kvm->mmu_lock);
3390 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3392 make_mmu_pages_available(vcpu);
3393 if (likely(!force_pt_level))
3394 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3395 r = __direct_map(vcpu, gpa, write, map_writable,
3396 level, gfn, pfn, prefault);
3397 spin_unlock(&vcpu->kvm->mmu_lock);
3402 spin_unlock(&vcpu->kvm->mmu_lock);
3403 kvm_release_pfn_clean(pfn);
3407 static void nonpaging_free(struct kvm_vcpu *vcpu)
3409 mmu_free_roots(vcpu);
3412 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3413 struct kvm_mmu *context)
3415 context->new_cr3 = nonpaging_new_cr3;
3416 context->page_fault = nonpaging_page_fault;
3417 context->gva_to_gpa = nonpaging_gva_to_gpa;
3418 context->free = nonpaging_free;
3419 context->sync_page = nonpaging_sync_page;
3420 context->invlpg = nonpaging_invlpg;
3421 context->update_pte = nonpaging_update_pte;
3422 context->root_level = 0;
3423 context->shadow_root_level = PT32E_ROOT_LEVEL;
3424 context->root_hpa = INVALID_PAGE;
3425 context->direct_map = true;
3426 context->nx = false;
3430 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3432 ++vcpu->stat.tlb_flush;
3433 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3436 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3438 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3439 mmu_free_roots(vcpu);
3442 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3444 return kvm_read_cr3(vcpu);
3447 static void inject_page_fault(struct kvm_vcpu *vcpu,
3448 struct x86_exception *fault)
3450 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3453 static void paging_free(struct kvm_vcpu *vcpu)
3455 nonpaging_free(vcpu);
3458 static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
3462 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
3464 mask = (unsigned)~ACC_WRITE_MASK;
3465 /* Allow write access to dirty gptes */
3466 mask |= (gpte >> (PT_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) & PT_WRITABLE_MASK;
3470 static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3471 unsigned access, int *nr_present)
3473 if (unlikely(is_mmio_spte(*sptep))) {
3474 if (gfn != get_mmio_spte_gfn(*sptep)) {
3475 mmu_spte_clear_no_track(sptep);
3480 mark_mmio_spte(kvm, sptep, gfn, access);
3487 static inline unsigned gpte_access(struct kvm_vcpu *vcpu, u64 gpte)
3491 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
3492 access &= ~(gpte >> PT64_NX_SHIFT);
3497 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3502 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3503 return mmu->last_pte_bitmap & (1 << index);
3507 #include "paging_tmpl.h"
3511 #include "paging_tmpl.h"
3514 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3515 struct kvm_mmu *context)
3517 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3518 u64 exb_bit_rsvd = 0;
3521 exb_bit_rsvd = rsvd_bits(63, 63);
3522 switch (context->root_level) {
3523 case PT32_ROOT_LEVEL:
3524 /* no rsvd bits for 2 level 4K page table entries */
3525 context->rsvd_bits_mask[0][1] = 0;
3526 context->rsvd_bits_mask[0][0] = 0;
3527 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3529 if (!is_pse(vcpu)) {
3530 context->rsvd_bits_mask[1][1] = 0;
3534 if (is_cpuid_PSE36())
3535 /* 36bits PSE 4MB page */
3536 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3538 /* 32 bits PSE 4MB page */
3539 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3541 case PT32E_ROOT_LEVEL:
3542 context->rsvd_bits_mask[0][2] =
3543 rsvd_bits(maxphyaddr, 63) |
3544 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3545 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3546 rsvd_bits(maxphyaddr, 62); /* PDE */
3547 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3548 rsvd_bits(maxphyaddr, 62); /* PTE */
3549 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3550 rsvd_bits(maxphyaddr, 62) |
3551 rsvd_bits(13, 20); /* large page */
3552 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3554 case PT64_ROOT_LEVEL:
3555 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3556 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3557 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3558 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3559 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3560 rsvd_bits(maxphyaddr, 51);
3561 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3562 rsvd_bits(maxphyaddr, 51);
3563 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3564 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3565 rsvd_bits(maxphyaddr, 51) |
3567 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3568 rsvd_bits(maxphyaddr, 51) |
3569 rsvd_bits(13, 20); /* large page */
3570 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3575 static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3577 unsigned bit, byte, pfec;
3579 bool fault, x, w, u, wf, uf, ff, smep;
3581 smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3582 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3585 wf = pfec & PFERR_WRITE_MASK;
3586 uf = pfec & PFERR_USER_MASK;
3587 ff = pfec & PFERR_FETCH_MASK;
3588 for (bit = 0; bit < 8; ++bit) {
3589 x = bit & ACC_EXEC_MASK;
3590 w = bit & ACC_WRITE_MASK;
3591 u = bit & ACC_USER_MASK;
3593 /* Not really needed: !nx will cause pte.nx to fault */
3595 /* Allow supervisor writes if !cr0.wp */
3596 w |= !is_write_protection(vcpu) && !uf;
3597 /* Disallow supervisor fetches of user code if cr4.smep */
3598 x &= !(smep && u && !uf);
3600 fault = (ff && !x) || (uf && !u) || (wf && !w);
3601 map |= fault << bit;
3603 mmu->permissions[byte] = map;
3607 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3610 unsigned level, root_level = mmu->root_level;
3611 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3613 if (root_level == PT32E_ROOT_LEVEL)
3615 /* PT_PAGE_TABLE_LEVEL always terminates */
3616 map = 1 | (1 << ps_set_index);
3617 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3618 if (level <= PT_PDPE_LEVEL
3619 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3620 map |= 1 << (ps_set_index | (level - 1));
3622 mmu->last_pte_bitmap = map;
3625 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3626 struct kvm_mmu *context,
3629 context->nx = is_nx(vcpu);
3630 context->root_level = level;
3632 reset_rsvds_bits_mask(vcpu, context);
3633 update_permission_bitmask(vcpu, context);
3634 update_last_pte_bitmap(vcpu, context);
3636 ASSERT(is_pae(vcpu));
3637 context->new_cr3 = paging_new_cr3;
3638 context->page_fault = paging64_page_fault;
3639 context->gva_to_gpa = paging64_gva_to_gpa;
3640 context->sync_page = paging64_sync_page;
3641 context->invlpg = paging64_invlpg;
3642 context->update_pte = paging64_update_pte;
3643 context->free = paging_free;
3644 context->shadow_root_level = level;
3645 context->root_hpa = INVALID_PAGE;
3646 context->direct_map = false;
3650 static int paging64_init_context(struct kvm_vcpu *vcpu,
3651 struct kvm_mmu *context)
3653 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3656 static int paging32_init_context(struct kvm_vcpu *vcpu,
3657 struct kvm_mmu *context)
3659 context->nx = false;
3660 context->root_level = PT32_ROOT_LEVEL;
3662 reset_rsvds_bits_mask(vcpu, context);
3663 update_permission_bitmask(vcpu, context);
3664 update_last_pte_bitmap(vcpu, context);
3666 context->new_cr3 = paging_new_cr3;
3667 context->page_fault = paging32_page_fault;
3668 context->gva_to_gpa = paging32_gva_to_gpa;
3669 context->free = paging_free;
3670 context->sync_page = paging32_sync_page;
3671 context->invlpg = paging32_invlpg;
3672 context->update_pte = paging32_update_pte;
3673 context->shadow_root_level = PT32E_ROOT_LEVEL;
3674 context->root_hpa = INVALID_PAGE;
3675 context->direct_map = false;
3679 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3680 struct kvm_mmu *context)
3682 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3685 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3687 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3689 context->base_role.word = 0;
3690 context->new_cr3 = nonpaging_new_cr3;
3691 context->page_fault = tdp_page_fault;
3692 context->free = nonpaging_free;
3693 context->sync_page = nonpaging_sync_page;
3694 context->invlpg = nonpaging_invlpg;
3695 context->update_pte = nonpaging_update_pte;
3696 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3697 context->root_hpa = INVALID_PAGE;
3698 context->direct_map = true;
3699 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3700 context->get_cr3 = get_cr3;
3701 context->get_pdptr = kvm_pdptr_read;
3702 context->inject_page_fault = kvm_inject_page_fault;
3704 if (!is_paging(vcpu)) {
3705 context->nx = false;
3706 context->gva_to_gpa = nonpaging_gva_to_gpa;
3707 context->root_level = 0;
3708 } else if (is_long_mode(vcpu)) {
3709 context->nx = is_nx(vcpu);
3710 context->root_level = PT64_ROOT_LEVEL;
3711 reset_rsvds_bits_mask(vcpu, context);
3712 context->gva_to_gpa = paging64_gva_to_gpa;
3713 } else if (is_pae(vcpu)) {
3714 context->nx = is_nx(vcpu);
3715 context->root_level = PT32E_ROOT_LEVEL;
3716 reset_rsvds_bits_mask(vcpu, context);
3717 context->gva_to_gpa = paging64_gva_to_gpa;
3719 context->nx = false;
3720 context->root_level = PT32_ROOT_LEVEL;
3721 reset_rsvds_bits_mask(vcpu, context);
3722 context->gva_to_gpa = paging32_gva_to_gpa;
3725 update_permission_bitmask(vcpu, context);
3726 update_last_pte_bitmap(vcpu, context);
3731 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3734 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3736 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3738 if (!is_paging(vcpu))
3739 r = nonpaging_init_context(vcpu, context);
3740 else if (is_long_mode(vcpu))
3741 r = paging64_init_context(vcpu, context);
3742 else if (is_pae(vcpu))
3743 r = paging32E_init_context(vcpu, context);
3745 r = paging32_init_context(vcpu, context);
3747 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3748 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3749 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3750 vcpu->arch.mmu.base_role.smep_andnot_wp
3751 = smep && !is_write_protection(vcpu);
3755 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3757 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3759 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3761 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3762 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3763 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3764 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3769 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3771 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3773 g_context->get_cr3 = get_cr3;
3774 g_context->get_pdptr = kvm_pdptr_read;
3775 g_context->inject_page_fault = kvm_inject_page_fault;
3778 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3779 * translation of l2_gpa to l1_gpa addresses is done using the
3780 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3781 * functions between mmu and nested_mmu are swapped.
3783 if (!is_paging(vcpu)) {
3784 g_context->nx = false;
3785 g_context->root_level = 0;
3786 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3787 } else if (is_long_mode(vcpu)) {
3788 g_context->nx = is_nx(vcpu);
3789 g_context->root_level = PT64_ROOT_LEVEL;
3790 reset_rsvds_bits_mask(vcpu, g_context);
3791 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3792 } else if (is_pae(vcpu)) {
3793 g_context->nx = is_nx(vcpu);
3794 g_context->root_level = PT32E_ROOT_LEVEL;
3795 reset_rsvds_bits_mask(vcpu, g_context);
3796 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3798 g_context->nx = false;
3799 g_context->root_level = PT32_ROOT_LEVEL;
3800 reset_rsvds_bits_mask(vcpu, g_context);
3801 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3804 update_permission_bitmask(vcpu, g_context);
3805 update_last_pte_bitmap(vcpu, g_context);
3810 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3812 if (mmu_is_nested(vcpu))
3813 return init_kvm_nested_mmu(vcpu);
3814 else if (tdp_enabled)
3815 return init_kvm_tdp_mmu(vcpu);
3817 return init_kvm_softmmu(vcpu);
3820 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3823 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3824 /* mmu.free() should set root_hpa = INVALID_PAGE */
3825 vcpu->arch.mmu.free(vcpu);
3828 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3830 destroy_kvm_mmu(vcpu);
3831 return init_kvm_mmu(vcpu);
3833 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3835 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3839 r = mmu_topup_memory_caches(vcpu);
3842 r = mmu_alloc_roots(vcpu);
3843 kvm_mmu_sync_roots(vcpu);
3846 /* set_cr3() should ensure TLB has been flushed */
3847 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3851 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3853 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3855 mmu_free_roots(vcpu);
3857 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3859 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3860 struct kvm_mmu_page *sp, u64 *spte,
3863 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3864 ++vcpu->kvm->stat.mmu_pde_zapped;
3868 ++vcpu->kvm->stat.mmu_pte_updated;
3869 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3872 static bool need_remote_flush(u64 old, u64 new)
3874 if (!is_shadow_present_pte(old))
3876 if (!is_shadow_present_pte(new))
3878 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3880 old ^= PT64_NX_MASK;
3881 new ^= PT64_NX_MASK;
3882 return (old & ~new & PT64_PERM_MASK) != 0;
3885 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3886 bool remote_flush, bool local_flush)
3892 kvm_flush_remote_tlbs(vcpu->kvm);
3893 else if (local_flush)
3894 kvm_mmu_flush_tlb(vcpu);
3897 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3898 const u8 *new, int *bytes)
3904 * Assume that the pte write on a page table of the same type
3905 * as the current vcpu paging mode since we update the sptes only
3906 * when they have the same mode.
3908 if (is_pae(vcpu) && *bytes == 4) {
3909 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3912 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3915 new = (const u8 *)&gentry;
3920 gentry = *(const u32 *)new;
3923 gentry = *(const u64 *)new;
3934 * If we're seeing too many writes to a page, it may no longer be a page table,
3935 * or we may be forking, in which case it is better to unmap the page.
3937 static bool detect_write_flooding(struct kvm_mmu_page *sp)
3940 * Skip write-flooding detected for the sp whose level is 1, because
3941 * it can become unsync, then the guest page is not write-protected.
3943 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
3946 return ++sp->write_flooding_count >= 3;
3950 * Misaligned accesses are too much trouble to fix up; also, they usually
3951 * indicate a page is not used as a page table.
3953 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3956 unsigned offset, pte_size, misaligned;
3958 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3959 gpa, bytes, sp->role.word);
3961 offset = offset_in_page(gpa);
3962 pte_size = sp->role.cr4_pae ? 8 : 4;
3965 * Sometimes, the OS only writes the last one bytes to update status
3966 * bits, for example, in linux, andb instruction is used in clear_bit().
3968 if (!(offset & (pte_size - 1)) && bytes == 1)
3971 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3972 misaligned |= bytes < 4;
3977 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3979 unsigned page_offset, quadrant;
3983 page_offset = offset_in_page(gpa);
3984 level = sp->role.level;
3986 if (!sp->role.cr4_pae) {
3987 page_offset <<= 1; /* 32->64 */
3989 * A 32-bit pde maps 4MB while the shadow pdes map
3990 * only 2MB. So we need to double the offset again
3991 * and zap two pdes instead of one.
3993 if (level == PT32_ROOT_LEVEL) {
3994 page_offset &= ~7; /* kill rounding error */
3998 quadrant = page_offset >> PAGE_SHIFT;
3999 page_offset &= ~PAGE_MASK;
4000 if (quadrant != sp->role.quadrant)
4004 spte = &sp->spt[page_offset / sizeof(*spte)];
4008 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4009 const u8 *new, int bytes)
4011 gfn_t gfn = gpa >> PAGE_SHIFT;
4012 union kvm_mmu_page_role mask = { .word = 0 };
4013 struct kvm_mmu_page *sp;
4014 LIST_HEAD(invalid_list);
4015 u64 entry, gentry, *spte;
4017 bool remote_flush, local_flush, zap_page;
4020 * If we don't have indirect shadow pages, it means no page is
4021 * write-protected, so we can exit simply.
4023 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4026 zap_page = remote_flush = local_flush = false;
4028 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4030 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4033 * No need to care whether allocation memory is successful
4034 * or not since pte prefetch is skiped if it does not have
4035 * enough objects in the cache.
4037 mmu_topup_memory_caches(vcpu);
4039 spin_lock(&vcpu->kvm->mmu_lock);
4040 ++vcpu->kvm->stat.mmu_pte_write;
4041 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4043 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
4044 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4045 if (detect_write_misaligned(sp, gpa, bytes) ||
4046 detect_write_flooding(sp)) {
4047 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4049 ++vcpu->kvm->stat.mmu_flooded;
4053 spte = get_written_sptes(sp, gpa, &npte);
4060 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4062 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4063 & mask.word) && rmap_can_add(vcpu))
4064 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4065 if (need_remote_flush(entry, *spte))
4066 remote_flush = true;
4070 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4071 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4072 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4073 spin_unlock(&vcpu->kvm->mmu_lock);
4076 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4081 if (vcpu->arch.mmu.direct_map)
4084 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4086 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4090 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4092 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4094 LIST_HEAD(invalid_list);
4096 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4099 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4100 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4103 ++vcpu->kvm->stat.mmu_recycled;
4105 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4108 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4110 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4111 return vcpu_match_mmio_gpa(vcpu, addr);
4113 return vcpu_match_mmio_gva(vcpu, addr);
4116 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4117 void *insn, int insn_len)
4119 int r, emulation_type = EMULTYPE_RETRY;
4120 enum emulation_result er;
4122 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4131 if (is_mmio_page_fault(vcpu, cr2))
4134 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4139 case EMULATE_DO_MMIO:
4140 ++vcpu->stat.mmio_exits;
4150 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4152 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4154 vcpu->arch.mmu.invlpg(vcpu, gva);
4155 kvm_mmu_flush_tlb(vcpu);
4156 ++vcpu->stat.invlpg;
4158 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4160 void kvm_enable_tdp(void)
4164 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4166 void kvm_disable_tdp(void)
4168 tdp_enabled = false;
4170 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4172 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4174 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4175 if (vcpu->arch.mmu.lm_root != NULL)
4176 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4179 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4187 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4188 * Therefore we need to allocate shadow page tables in the first
4189 * 4GB of memory, which happens to fit the DMA32 zone.
4191 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4195 vcpu->arch.mmu.pae_root = page_address(page);
4196 for (i = 0; i < 4; ++i)
4197 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4202 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4206 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4207 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4208 vcpu->arch.mmu.translate_gpa = translate_gpa;
4209 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4211 return alloc_mmu_pages(vcpu);
4214 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
4217 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4219 return init_kvm_mmu(vcpu);
4222 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4224 struct kvm_memory_slot *memslot;
4228 memslot = id_to_memslot(kvm->memslots, slot);
4229 last_gfn = memslot->base_gfn + memslot->npages - 1;
4231 spin_lock(&kvm->mmu_lock);
4233 for (i = PT_PAGE_TABLE_LEVEL;
4234 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4235 unsigned long *rmapp;
4236 unsigned long last_index, index;
4238 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4239 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4241 for (index = 0; index <= last_index; ++index, ++rmapp) {
4243 __rmap_write_protect(kvm, rmapp, false);
4245 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4246 kvm_flush_remote_tlbs(kvm);
4247 cond_resched_lock(&kvm->mmu_lock);
4252 kvm_flush_remote_tlbs(kvm);
4253 spin_unlock(&kvm->mmu_lock);
4256 #define BATCH_ZAP_PAGES 10
4257 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4259 struct kvm_mmu_page *sp, *node;
4263 list_for_each_entry_safe_reverse(sp, node,
4264 &kvm->arch.active_mmu_pages, link) {
4268 * No obsolete page exists before new created page since
4269 * active_mmu_pages is the FIFO list.
4271 if (!is_obsolete_sp(kvm, sp))
4275 * Since we are reversely walking the list and the invalid
4276 * list will be moved to the head, skip the invalid page
4277 * can help us to avoid the infinity list walking.
4279 if (sp->role.invalid)
4283 * Need not flush tlb since we only zap the sp with invalid
4284 * generation number.
4286 if (batch >= BATCH_ZAP_PAGES &&
4287 cond_resched_lock(&kvm->mmu_lock)) {
4292 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4293 &kvm->arch.zapped_obsolete_pages);
4301 * Should flush tlb before free page tables since lockless-walking
4302 * may use the pages.
4304 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4308 * Fast invalidate all shadow pages and use lock-break technique
4309 * to zap obsolete pages.
4311 * It's required when memslot is being deleted or VM is being
4312 * destroyed, in these cases, we should ensure that KVM MMU does
4313 * not use any resource of the being-deleted slot or all slots
4314 * after calling the function.
4316 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4318 spin_lock(&kvm->mmu_lock);
4319 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4320 kvm->arch.mmu_valid_gen++;
4323 * Notify all vcpus to reload its shadow page table
4324 * and flush TLB. Then all vcpus will switch to new
4325 * shadow page table with the new mmu_valid_gen.
4327 * Note: we should do this under the protection of
4328 * mmu-lock, otherwise, vcpu would purge shadow page
4329 * but miss tlb flush.
4331 kvm_reload_remote_mmus(kvm);
4333 kvm_zap_obsolete_pages(kvm);
4334 spin_unlock(&kvm->mmu_lock);
4337 void kvm_mmu_zap_mmio_sptes(struct kvm *kvm)
4339 struct kvm_mmu_page *sp, *node;
4340 LIST_HEAD(invalid_list);
4342 spin_lock(&kvm->mmu_lock);
4344 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
4345 if (!sp->mmio_cached)
4347 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
4351 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4352 spin_unlock(&kvm->mmu_lock);
4355 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4357 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4360 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
4363 int nr_to_scan = sc->nr_to_scan;
4365 if (nr_to_scan == 0)
4368 raw_spin_lock(&kvm_lock);
4370 list_for_each_entry(kvm, &vm_list, vm_list) {
4372 LIST_HEAD(invalid_list);
4375 * Never scan more than sc->nr_to_scan VM instances.
4376 * Will not hit this condition practically since we do not try
4377 * to shrink more than one VM and it is very unlikely to see
4378 * !n_used_mmu_pages so many times.
4383 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4384 * here. We may skip a VM instance errorneosly, but we do not
4385 * want to shrink a VM that only started to populate its MMU
4388 if (!kvm->arch.n_used_mmu_pages &&
4389 !kvm_has_zapped_obsolete_pages(kvm))
4392 idx = srcu_read_lock(&kvm->srcu);
4393 spin_lock(&kvm->mmu_lock);
4395 if (kvm_has_zapped_obsolete_pages(kvm)) {
4396 kvm_mmu_commit_zap_page(kvm,
4397 &kvm->arch.zapped_obsolete_pages);
4401 prepare_zap_oldest_mmu_page(kvm, &invalid_list);
4402 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4405 spin_unlock(&kvm->mmu_lock);
4406 srcu_read_unlock(&kvm->srcu, idx);
4408 list_move_tail(&kvm->vm_list, &vm_list);
4412 raw_spin_unlock(&kvm_lock);
4415 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4418 static struct shrinker mmu_shrinker = {
4419 .shrink = mmu_shrink,
4420 .seeks = DEFAULT_SEEKS * 10,
4423 static void mmu_destroy_caches(void)
4425 if (pte_list_desc_cache)
4426 kmem_cache_destroy(pte_list_desc_cache);
4427 if (mmu_page_header_cache)
4428 kmem_cache_destroy(mmu_page_header_cache);
4431 int kvm_mmu_module_init(void)
4433 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4434 sizeof(struct pte_list_desc),
4436 if (!pte_list_desc_cache)
4439 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4440 sizeof(struct kvm_mmu_page),
4442 if (!mmu_page_header_cache)
4445 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4448 register_shrinker(&mmu_shrinker);
4453 mmu_destroy_caches();
4458 * Caculate mmu pages needed for kvm.
4460 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4462 unsigned int nr_mmu_pages;
4463 unsigned int nr_pages = 0;
4464 struct kvm_memslots *slots;
4465 struct kvm_memory_slot *memslot;
4467 slots = kvm_memslots(kvm);
4469 kvm_for_each_memslot(memslot, slots)
4470 nr_pages += memslot->npages;
4472 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4473 nr_mmu_pages = max(nr_mmu_pages,
4474 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4476 return nr_mmu_pages;
4479 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4481 struct kvm_shadow_walk_iterator iterator;
4485 walk_shadow_page_lockless_begin(vcpu);
4486 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4487 sptes[iterator.level-1] = spte;
4489 if (!is_shadow_present_pte(spte))
4492 walk_shadow_page_lockless_end(vcpu);
4496 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4498 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4502 destroy_kvm_mmu(vcpu);
4503 free_mmu_pages(vcpu);
4504 mmu_free_memory_caches(vcpu);
4507 void kvm_mmu_module_exit(void)
4509 mmu_destroy_caches();
4510 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4511 unregister_shrinker(&mmu_shrinker);
4512 mmu_audit_disable();