arch/x86/kvm/mmu.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * MMU support
   8  *
   9  * Copyright (C) 2006 Qumranet, Inc.
  10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  11  *
  12  * Authors:
  13  *   Yaniv Kamay  <yaniv@qumranet.com>
  14  *   Avi Kivity   <avi@qumranet.com>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.  See
  17  * the COPYING file in the top-level directory.
  18  *
  19  */
  20
  21 #include "irq.h"
  22 #include "mmu.h"
  23 #include "x86.h"
  24 #include "kvm_cache_regs.h"
  25
  26 #include <linux/kvm_host.h>
  27 #include <linux/types.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/highmem.h>
  31 #include <linux/module.h>
  32 #include <linux/swap.h>
  33 #include <linux/hugetlb.h>
  34 #include <linux/compiler.h>
  35 #include <linux/srcu.h>
  36 #include <linux/slab.h>
  37 #include <linux/uaccess.h>
  38
  39 #include <asm/page.h>
  40 #include <asm/cmpxchg.h>
  41 #include <asm/io.h>
  42 #include <asm/vmx.h>
  43
  44 /*
  45  * When setting this variable to true it enables Two-Dimensional-Paging
  46  * where the hardware walks 2 page tables:
  47  * 1. the guest-virtual to guest-physical
  48  * 2. while doing 1. it walks guest-physical to host-physical
  49  * If the hardware supports that we don't need to do shadow paging.
  50  */
  51 bool tdp_enabled = false;
  52
  53 enum {
  54         AUDIT_PRE_PAGE_FAULT,
  55         AUDIT_POST_PAGE_FAULT,
  56         AUDIT_PRE_PTE_WRITE,
  57         AUDIT_POST_PTE_WRITE,
  58         AUDIT_PRE_SYNC,
  59         AUDIT_POST_SYNC
  60 };
  61
  62 char *audit_point_name[] = {
  63         "pre page fault",
  64         "post page fault",
  65         "pre pte write",
  66         "post pte write",
  67         "pre sync",
  68         "post sync"
  69 };
  70
  71 #undef MMU_DEBUG
  72
  73 #ifdef MMU_DEBUG
  74
  75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
  76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
  77
  78 #else
  79
  80 #define pgprintk(x...) do { } while (0)
  81 #define rmap_printk(x...) do { } while (0)
  82
  83 #endif
  84
  85 #ifdef MMU_DEBUG
  86 static int dbg = 0;
  87 module_param(dbg, bool, 0644);
  88 #endif
  89
  90 static int oos_shadow = 1;
  91 module_param(oos_shadow, bool, 0644);
  92
  93 #ifndef MMU_DEBUG
  94 #define ASSERT(x) do { } while (0)
  95 #else
  96 #define ASSERT(x)                                                       \
  97         if (!(x)) {                                                     \
  98                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
  99                        __FILE__, __LINE__, #x);                         \
 100         }
 101 #endif
 102
 103 #define PTE_PREFETCH_NUM                8
 104
 105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
 106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 107
 108 #define PT64_LEVEL_BITS 9
 109
 110 #define PT64_LEVEL_SHIFT(level) \
 111                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
 112
 113 #define PT64_INDEX(address, level)\
 114         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
 115
 116
 117 #define PT32_LEVEL_BITS 10
 118
 119 #define PT32_LEVEL_SHIFT(level) \
 120                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
 121
 122 #define PT32_LVL_OFFSET_MASK(level) \
 123         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
 124                                                 * PT32_LEVEL_BITS))) - 1))
 125
 126 #define PT32_INDEX(address, level)\
 127         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
 128
 129
 130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
 131 #define PT64_DIR_BASE_ADDR_MASK \
 132         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
 133 #define PT64_LVL_ADDR_MASK(level) \
 134         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
 135                                                 * PT64_LEVEL_BITS))) - 1))
 136 #define PT64_LVL_OFFSET_MASK(level) \
 137         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
 138                                                 * PT64_LEVEL_BITS))) - 1))
 139
 140 #define PT32_BASE_ADDR_MASK PAGE_MASK
 141 #define PT32_DIR_BASE_ADDR_MASK \
 142         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
 143 #define PT32_LVL_ADDR_MASK(level) \
 144         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
 145                                             * PT32_LEVEL_BITS))) - 1))
 146
 147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
 148                         | PT64_NX_MASK)
 149
 150 #define PTE_LIST_EXT 4
 151
 152 #define ACC_EXEC_MASK    1
 153 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
 154 #define ACC_USER_MASK    PT_USER_MASK
 155 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
 156
 157 #include <trace/events/kvm.h>
 158
 159 #define CREATE_TRACE_POINTS
 160 #include "mmutrace.h"
 161
 162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
 163
 164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
 165
 166 struct pte_list_desc {
 167         u64 *sptes[PTE_LIST_EXT];
 168         struct pte_list_desc *more;
 169 };
 170
 171 struct kvm_shadow_walk_iterator {
 172         u64 addr;
 173         hpa_t shadow_addr;
 174         u64 *sptep;
 175         int level;
 176         unsigned index;
 177 };
 178
 179 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
 180         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
 181              shadow_walk_okay(&(_walker));                      \
 182              shadow_walk_next(&(_walker)))
 183
 184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
 185         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
 186              shadow_walk_okay(&(_walker)) &&                            \
 187                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
 188              __shadow_walk_next(&(_walker), spte))
 189
 190 static struct kmem_cache *pte_list_desc_cache;
 191 static struct kmem_cache *mmu_page_header_cache;
 192 static struct percpu_counter kvm_total_used_mmu_pages;
 193
 194 static u64 __read_mostly shadow_nx_mask;
 195 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
 196 static u64 __read_mostly shadow_user_mask;
 197 static u64 __read_mostly shadow_accessed_mask;
 198 static u64 __read_mostly shadow_dirty_mask;
 199 static u64 __read_mostly shadow_mmio_mask;
 200
 201 static void mmu_spte_set(u64 *sptep, u64 spte);
 202
 203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
 204 {
 205         shadow_mmio_mask = mmio_mask;
 206 }
 207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
 208
 209 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
 210 {
 211         access &= ACC_WRITE_MASK | ACC_USER_MASK;
 212
 213         trace_mark_mmio_spte(sptep, gfn, access);
 214         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
 215 }
 216
 217 static bool is_mmio_spte(u64 spte)
 218 {
 219         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
 220 }
 221
 222 static gfn_t get_mmio_spte_gfn(u64 spte)
 223 {
 224         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
 225 }
 226
 227 static unsigned get_mmio_spte_access(u64 spte)
 228 {
 229         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
 230 }
 231
 232 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
 233 {
 234         if (unlikely(is_noslot_pfn(pfn))) {
 235                 mark_mmio_spte(sptep, gfn, access);
 236                 return true;
 237         }
 238
 239         return false;
 240 }
 241
 242 static inline u64 rsvd_bits(int s, int e)
 243 {
 244         return ((1ULL << (e - s + 1)) - 1) << s;
 245 }
 246
 247 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
 248                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
 249 {
 250         shadow_user_mask = user_mask;
 251         shadow_accessed_mask = accessed_mask;
 252         shadow_dirty_mask = dirty_mask;
 253         shadow_nx_mask = nx_mask;
 254         shadow_x_mask = x_mask;
 255 }
 256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
 257
 258 static int is_cpuid_PSE36(void)
 259 {
 260         return 1;
 261 }
 262
 263 static int is_nx(struct kvm_vcpu *vcpu)
 264 {
 265         return vcpu->arch.efer & EFER_NX;
 266 }
 267
 268 static int is_shadow_present_pte(u64 pte)
 269 {
 270         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
 271 }
 272
 273 static int is_large_pte(u64 pte)
 274 {
 275         return pte & PT_PAGE_SIZE_MASK;
 276 }
 277
 278 static int is_dirty_gpte(unsigned long pte)
 279 {
 280         return pte & PT_DIRTY_MASK;
 281 }
 282
 283 static int is_rmap_spte(u64 pte)
 284 {
 285         return is_shadow_present_pte(pte);
 286 }
 287
 288 static int is_last_spte(u64 pte, int level)
 289 {
 290         if (level == PT_PAGE_TABLE_LEVEL)
 291                 return 1;
 292         if (is_large_pte(pte))
 293                 return 1;
 294         return 0;
 295 }
 296
 297 static pfn_t spte_to_pfn(u64 pte)
 298 {
 299         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
 300 }
 301
 302 static gfn_t pse36_gfn_delta(u32 gpte)
 303 {
 304         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
 305
 306         return (gpte & PT32_DIR_PSE36_MASK) << shift;
 307 }
 308
 309 #ifdef CONFIG_X86_64
 310 static void __set_spte(u64 *sptep, u64 spte)
 311 {
 312         *sptep = spte;
 313 }
 314
 315 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
 316 {
 317         *sptep = spte;
 318 }
 319
 320 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 321 {
 322         return xchg(sptep, spte);
 323 }
 324
 325 static u64 __get_spte_lockless(u64 *sptep)
 326 {
 327         return ACCESS_ONCE(*sptep);
 328 }
 329
 330 static bool __check_direct_spte_mmio_pf(u64 spte)
 331 {
 332         /* It is valid if the spte is zapped. */
 333         return spte == 0ull;
 334 }
 335 #else
 336 union split_spte {
 337         struct {
 338                 u32 spte_low;
 339                 u32 spte_high;
 340         };
 341         u64 spte;
 342 };
 343
 344 static void count_spte_clear(u64 *sptep, u64 spte)
 345 {
 346         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
 347
 348         if (is_shadow_present_pte(spte))
 349                 return;
 350
 351         /* Ensure the spte is completely set before we increase the count */
 352         smp_wmb();
 353         sp->clear_spte_count++;
 354 }
 355
 356 static void __set_spte(u64 *sptep, u64 spte)
 357 {
 358         union split_spte *ssptep, sspte;
 359
 360         ssptep = (union split_spte *)sptep;
 361         sspte = (union split_spte)spte;
 362
 363         ssptep->spte_high = sspte.spte_high;
 364
 365         /*
 366          * If we map the spte from nonpresent to present, We should store
 367          * the high bits firstly, then set present bit, so cpu can not
 368          * fetch this spte while we are setting the spte.
 369          */
 370         smp_wmb();
 371
 372         ssptep->spte_low = sspte.spte_low;
 373 }
 374
 375 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
 376 {
 377         union split_spte *ssptep, sspte;
 378
 379         ssptep = (union split_spte *)sptep;
 380         sspte = (union split_spte)spte;
 381
 382         ssptep->spte_low = sspte.spte_low;
 383
 384         /*
 385          * If we map the spte from present to nonpresent, we should clear
 386          * present bit firstly to avoid vcpu fetch the old high bits.
 387          */
 388         smp_wmb();
 389
 390         ssptep->spte_high = sspte.spte_high;
 391         count_spte_clear(sptep, spte);
 392 }
 393
 394 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 395 {
 396         union split_spte *ssptep, sspte, orig;
 397
 398         ssptep = (union split_spte *)sptep;
 399         sspte = (union split_spte)spte;
 400
 401         /* xchg acts as a barrier before the setting of the high bits */
 402         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
 403         orig.spte_high = ssptep->spte_high;
 404         ssptep->spte_high = sspte.spte_high;
 405         count_spte_clear(sptep, spte);
 406
 407         return orig.spte;
 408 }
 409
 410 /*
 411  * The idea using the light way get the spte on x86_32 guest is from
 412  * gup_get_pte(arch/x86/mm/gup.c).
 413  * The difference is we can not catch the spte tlb flush if we leave
 414  * guest mode, so we emulate it by increase clear_spte_count when spte
 415  * is cleared.
 416  */
 417 static u64 __get_spte_lockless(u64 *sptep)
 418 {
 419         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
 420         union split_spte spte, *orig = (union split_spte *)sptep;
 421         int count;
 422
 423 retry:
 424         count = sp->clear_spte_count;
 425         smp_rmb();
 426
 427         spte.spte_low = orig->spte_low;
 428         smp_rmb();
 429
 430         spte.spte_high = orig->spte_high;
 431         smp_rmb();
 432
 433         if (unlikely(spte.spte_low != orig->spte_low ||
 434               count != sp->clear_spte_count))
 435                 goto retry;
 436
 437         return spte.spte;
 438 }
 439
 440 static bool __check_direct_spte_mmio_pf(u64 spte)
 441 {
 442         union split_spte sspte = (union split_spte)spte;
 443         u32 high_mmio_mask = shadow_mmio_mask >> 32;
 444
 445         /* It is valid if the spte is zapped. */
 446         if (spte == 0ull)
 447                 return true;
 448
 449         /* It is valid if the spte is being zapped. */
 450         if (sspte.spte_low == 0ull &&
 451             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
 452                 return true;
 453
 454         return false;
 455 }
 456 #endif
 457
 458 static bool spte_has_volatile_bits(u64 spte)
 459 {
 460         if (!shadow_accessed_mask)
 461                 return false;
 462
 463         if (!is_shadow_present_pte(spte))
 464                 return false;
 465
 466         if ((spte & shadow_accessed_mask) &&
 467               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
 468                 return false;
 469
 470         return true;
 471 }
 472
 473 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
 474 {
 475         return (old_spte & bit_mask) && !(new_spte & bit_mask);
 476 }
 477
 478 /* Rules for using mmu_spte_set:
 479  * Set the sptep from nonpresent to present.
 480  * Note: the sptep being assigned *must* be either not present
 481  * or in a state where the hardware will not attempt to update
 482  * the spte.
 483  */
 484 static void mmu_spte_set(u64 *sptep, u64 new_spte)
 485 {
 486         WARN_ON(is_shadow_present_pte(*sptep));
 487         __set_spte(sptep, new_spte);
 488 }
 489
 490 /* Rules for using mmu_spte_update:
 491  * Update the state bits, it means the mapped pfn is not changged.
 492  */
 493 static void mmu_spte_update(u64 *sptep, u64 new_spte)
 494 {
 495         u64 mask, old_spte = *sptep;
 496
 497         WARN_ON(!is_rmap_spte(new_spte));
 498
 499         if (!is_shadow_present_pte(old_spte))
 500                 return mmu_spte_set(sptep, new_spte);
 501
 502         new_spte |= old_spte & shadow_dirty_mask;
 503
 504         mask = shadow_accessed_mask;
 505         if (is_writable_pte(old_spte))
 506                 mask |= shadow_dirty_mask;
 507
 508         if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
 509                 __update_clear_spte_fast(sptep, new_spte);
 510         else
 511                 old_spte = __update_clear_spte_slow(sptep, new_spte);
 512
 513         if (!shadow_accessed_mask)
 514                 return;
 515
 516         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
 517                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
 518         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
 519                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
 520 }
 521
 522 /*
 523  * Rules for using mmu_spte_clear_track_bits:
 524  * It sets the sptep from present to nonpresent, and track the
 525  * state bits, it is used to clear the last level sptep.
 526  */
 527 static int mmu_spte_clear_track_bits(u64 *sptep)
 528 {
 529         pfn_t pfn;
 530         u64 old_spte = *sptep;
 531
 532         if (!spte_has_volatile_bits(old_spte))
 533                 __update_clear_spte_fast(sptep, 0ull);
 534         else
 535                 old_spte = __update_clear_spte_slow(sptep, 0ull);
 536
 537         if (!is_rmap_spte(old_spte))
 538                 return 0;
 539
 540         pfn = spte_to_pfn(old_spte);
 541         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
 542                 kvm_set_pfn_accessed(pfn);
 543         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
 544                 kvm_set_pfn_dirty(pfn);
 545         return 1;
 546 }
 547
 548 /*
 549  * Rules for using mmu_spte_clear_no_track:
 550  * Directly clear spte without caring the state bits of sptep,
 551  * it is used to set the upper level spte.
 552  */
 553 static void mmu_spte_clear_no_track(u64 *sptep)
 554 {
 555         __update_clear_spte_fast(sptep, 0ull);
 556 }
 557
 558 static u64 mmu_spte_get_lockless(u64 *sptep)
 559 {
 560         return __get_spte_lockless(sptep);
 561 }
 562
 563 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
 564 {
 565         rcu_read_lock();
 566         atomic_inc(&vcpu->kvm->arch.reader_counter);
 567
 568         /* Increase the counter before walking shadow page table */
 569         smp_mb__after_atomic_inc();
 570 }
 571
 572 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
 573 {
 574         /* Decrease the counter after walking shadow page table finished */
 575         smp_mb__before_atomic_dec();
 576         atomic_dec(&vcpu->kvm->arch.reader_counter);
 577         rcu_read_unlock();
 578 }
 579
 580 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
 581                                   struct kmem_cache *base_cache, int min)
 582 {
 583         void *obj;
 584
 585         if (cache->nobjs >= min)
 586                 return 0;
 587         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
 588                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
 589                 if (!obj)
 590                         return -ENOMEM;
 591                 cache->objects[cache->nobjs++] = obj;
 592         }
 593         return 0;
 594 }
 595
 596 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
 597 {
 598         return cache->nobjs;
 599 }
 600
 601 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
 602                                   struct kmem_cache *cache)
 603 {
 604         while (mc->nobjs)
 605                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
 606 }
 607
 608 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
 609                                        int min)
 610 {
 611         void *page;
 612
 613         if (cache->nobjs >= min)
 614                 return 0;
 615         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
 616                 page = (void *)__get_free_page(GFP_KERNEL);
 617                 if (!page)
 618                         return -ENOMEM;
 619                 cache->objects[cache->nobjs++] = page;
 620         }
 621         return 0;
 622 }
 623
 624 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
 625 {
 626         while (mc->nobjs)
 627                 free_page((unsigned long)mc->objects[--mc->nobjs]);
 628 }
 629
 630 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
 631 {
 632         int r;
 633
 634         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
 635                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
 636         if (r)
 637                 goto out;
 638         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
 639         if (r)
 640                 goto out;
 641         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
 642                                    mmu_page_header_cache, 4);
 643 out:
 644         return r;
 645 }
 646
 647 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
 648 {
 649         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
 650                                 pte_list_desc_cache);
 651         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
 652         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
 653                                 mmu_page_header_cache);
 654 }
 655
 656 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
 657                                     size_t size)
 658 {
 659         void *p;
 660
 661         BUG_ON(!mc->nobjs);
 662         p = mc->objects[--mc->nobjs];
 663         return p;
 664 }
 665
 666 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
 667 {
 668         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
 669                                       sizeof(struct pte_list_desc));
 670 }
 671
 672 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
 673 {
 674         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
 675 }
 676
 677 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
 678 {
 679         if (!sp->role.direct)
 680                 return sp->gfns[index];
 681
 682         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
 683 }
 684
 685 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
 686 {
 687         if (sp->role.direct)
 688                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
 689         else
 690                 sp->gfns[index] = gfn;
 691 }
 692
 693 /*
 694  * Return the pointer to the large page information for a given gfn,
 695  * handling slots that are not large page aligned.
 696  */
 697 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
 698                                               struct kvm_memory_slot *slot,
 699                                               int level)
 700 {
 701         unsigned long idx;
 702
 703         idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
 704               (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
 705         return &slot->lpage_info[level - 2][idx];
 706 }
 707
 708 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
 709 {
 710         struct kvm_memory_slot *slot;
 711         struct kvm_lpage_info *linfo;
 712         int i;
 713
 714         slot = gfn_to_memslot(kvm, gfn);
 715         for (i = PT_DIRECTORY_LEVEL;
 716              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
 717                 linfo = lpage_info_slot(gfn, slot, i);
 718                 linfo->write_count += 1;
 719         }
 720         kvm->arch.indirect_shadow_pages++;
 721 }
 722
 723 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
 724 {
 725         struct kvm_memory_slot *slot;
 726         struct kvm_lpage_info *linfo;
 727         int i;
 728
 729         slot = gfn_to_memslot(kvm, gfn);
 730         for (i = PT_DIRECTORY_LEVEL;
 731              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
 732                 linfo = lpage_info_slot(gfn, slot, i);
 733                 linfo->write_count -= 1;
 734                 WARN_ON(linfo->write_count < 0);
 735         }
 736         kvm->arch.indirect_shadow_pages--;
 737 }
 738
 739 static int has_wrprotected_page(struct kvm *kvm,
 740                                 gfn_t gfn,
 741                                 int level)
 742 {
 743         struct kvm_memory_slot *slot;
 744         struct kvm_lpage_info *linfo;
 745
 746         slot = gfn_to_memslot(kvm, gfn);
 747         if (slot) {
 748                 linfo = lpage_info_slot(gfn, slot, level);
 749                 return linfo->write_count;
 750         }
 751
 752         return 1;
 753 }
 754
 755 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
 756 {
 757         unsigned long page_size;
 758         int i, ret = 0;
 759
 760         page_size = kvm_host_page_size(kvm, gfn);
 761
 762         for (i = PT_PAGE_TABLE_LEVEL;
 763              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
 764                 if (page_size >= KVM_HPAGE_SIZE(i))
 765                         ret = i;
 766                 else
 767                         break;
 768         }
 769
 770         return ret;
 771 }
 772
 773 static struct kvm_memory_slot *
 774 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
 775                             bool no_dirty_log)
 776 {
 777         struct kvm_memory_slot *slot;
 778
 779         slot = gfn_to_memslot(vcpu->kvm, gfn);
 780         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
 781               (no_dirty_log && slot->dirty_bitmap))
 782                 slot = NULL;
 783
 784         return slot;
 785 }
 786
 787 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 788 {
 789         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
 790 }
 791
 792 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 793 {
 794         int host_level, level, max_level;
 795
 796         host_level = host_mapping_level(vcpu->kvm, large_gfn);
 797
 798         if (host_level == PT_PAGE_TABLE_LEVEL)
 799                 return host_level;
 800
 801         max_level = kvm_x86_ops->get_lpage_level() < host_level ?
 802                 kvm_x86_ops->get_lpage_level() : host_level;
 803
 804         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
 805                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
 806                         break;
 807
 808         return level - 1;
 809 }
 810
 811 /*
 812  * Pte mapping structures:
 813  *
 814  * If pte_list bit zero is zero, then pte_list point to the spte.
 815  *
 816  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
 817  * pte_list_desc containing more mappings.
 818  *
 819  * Returns the number of pte entries before the spte was added or zero if
 820  * the spte was not added.
 821  *
 822  */
 823 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
 824                         unsigned long *pte_list)
 825 {
 826         struct pte_list_desc *desc;
 827         int i, count = 0;
 828
 829         if (!*pte_list) {
 830                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
 831                 *pte_list = (unsigned long)spte;
 832         } else if (!(*pte_list & 1)) {
 833                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
 834                 desc = mmu_alloc_pte_list_desc(vcpu);
 835                 desc->sptes[0] = (u64 *)*pte_list;
 836                 desc->sptes[1] = spte;
 837                 *pte_list = (unsigned long)desc | 1;
 838                 ++count;
 839         } else {
 840                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
 841                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 842                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
 843                         desc = desc->more;
 844                         count += PTE_LIST_EXT;
 845                 }
 846                 if (desc->sptes[PTE_LIST_EXT-1]) {
 847                         desc->more = mmu_alloc_pte_list_desc(vcpu);
 848                         desc = desc->more;
 849                 }
 850                 for (i = 0; desc->sptes[i]; ++i)
 851                         ++count;
 852                 desc->sptes[i] = spte;
 853         }
 854         return count;
 855 }
 856
 857 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
 858 {
 859         struct pte_list_desc *desc;
 860         u64 *prev_spte;
 861         int i;
 862
 863         if (!*pte_list)
 864                 return NULL;
 865         else if (!(*pte_list & 1)) {
 866                 if (!spte)
 867                         return (u64 *)*pte_list;
 868                 return NULL;
 869         }
 870         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 871         prev_spte = NULL;
 872         while (desc) {
 873                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
 874                         if (prev_spte == spte)
 875                                 return desc->sptes[i];
 876                         prev_spte = desc->sptes[i];
 877                 }
 878                 desc = desc->more;
 879         }
 880         return NULL;
 881 }
 882
 883 static void
 884 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
 885                            int i, struct pte_list_desc *prev_desc)
 886 {
 887         int j;
 888
 889         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
 890                 ;
 891         desc->sptes[i] = desc->sptes[j];
 892         desc->sptes[j] = NULL;
 893         if (j != 0)
 894                 return;
 895         if (!prev_desc && !desc->more)
 896                 *pte_list = (unsigned long)desc->sptes[0];
 897         else
 898                 if (prev_desc)
 899                         prev_desc->more = desc->more;
 900                 else
 901                         *pte_list = (unsigned long)desc->more | 1;
 902         mmu_free_pte_list_desc(desc);
 903 }
 904
 905 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
 906 {
 907         struct pte_list_desc *desc;
 908         struct pte_list_desc *prev_desc;
 909         int i;
 910
 911         if (!*pte_list) {
 912                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
 913                 BUG();
 914         } else if (!(*pte_list & 1)) {
 915                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
 916                 if ((u64 *)*pte_list != spte) {
 917                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
 918                         BUG();
 919                 }
 920                 *pte_list = 0;
 921         } else {
 922                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
 923                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 924                 prev_desc = NULL;
 925                 while (desc) {
 926                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
 927                                 if (desc->sptes[i] == spte) {
 928                                         pte_list_desc_remove_entry(pte_list,
 929                                                                desc, i,
 930                                                                prev_desc);
 931                                         return;
 932                                 }
 933                         prev_desc = desc;
 934                         desc = desc->more;
 935                 }
 936                 pr_err("pte_list_remove: %p many->many\n", spte);
 937                 BUG();
 938         }
 939 }
 940
 941 typedef void (*pte_list_walk_fn) (u64 *spte);
 942 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
 943 {
 944         struct pte_list_desc *desc;
 945         int i;
 946
 947         if (!*pte_list)
 948                 return;
 949
 950         if (!(*pte_list & 1))
 951                 return fn((u64 *)*pte_list);
 952
 953         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
 954         while (desc) {
 955                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
 956                         fn(desc->sptes[i]);
 957                 desc = desc->more;
 958         }
 959 }
 960
 961 /*
 962  * Take gfn and return the reverse mapping to it.
 963  */
 964 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
 965 {
 966         struct kvm_memory_slot *slot;
 967         struct kvm_lpage_info *linfo;
 968
 969         slot = gfn_to_memslot(kvm, gfn);
 970         if (likely(level == PT_PAGE_TABLE_LEVEL))
 971                 return &slot->rmap[gfn - slot->base_gfn];
 972
 973         linfo = lpage_info_slot(gfn, slot, level);
 974
 975         return &linfo->rmap_pde;
 976 }
 977
 978 static bool rmap_can_add(struct kvm_vcpu *vcpu)
 979 {
 980         struct kvm_mmu_memory_cache *cache;
 981
 982         cache = &vcpu->arch.mmu_pte_list_desc_cache;
 983         return mmu_memory_cache_free_objects(cache);
 984 }
 985
 986 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 987 {
 988         struct kvm_mmu_page *sp;
 989         unsigned long *rmapp;
 990
 991         sp = page_header(__pa(spte));
 992         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
 993         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
 994         return pte_list_add(vcpu, spte, rmapp);
 995 }
 996
 997 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
 998 {
 999         return pte_list_next(rmapp, spte);
1000 }
1001
1002 static void rmap_remove(struct kvm *kvm, u64 *spte)
1003 {
1004         struct kvm_mmu_page *sp;
1005         gfn_t gfn;
1006         unsigned long *rmapp;
1007
1008         sp = page_header(__pa(spte));
1009         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1010         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1011         pte_list_remove(spte, rmapp);
1012 }
1013
1014 static void drop_spte(struct kvm *kvm, u64 *sptep)
1015 {
1016         if (mmu_spte_clear_track_bits(sptep))
1017                 rmap_remove(kvm, sptep);
1018 }
1019
1020 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1021 {
1022         unsigned long *rmapp;
1023         u64 *spte;
1024         int i, write_protected = 0;
1025
1026         rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
1027
1028         spte = rmap_next(kvm, rmapp, NULL);
1029         while (spte) {
1030                 BUG_ON(!spte);
1031                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1032                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1033                 if (is_writable_pte(*spte)) {
1034                         mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1035                         write_protected = 1;
1036                 }
1037                 spte = rmap_next(kvm, rmapp, spte);
1038         }
1039
1040         /* check for huge page mappings */
1041         for (i = PT_DIRECTORY_LEVEL;
1042              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1043                 rmapp = gfn_to_rmap(kvm, gfn, i);
1044                 spte = rmap_next(kvm, rmapp, NULL);
1045                 while (spte) {
1046                         BUG_ON(!spte);
1047                         BUG_ON(!(*spte & PT_PRESENT_MASK));
1048                         BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
1049                         pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1050                         if (is_writable_pte(*spte)) {
1051                                 drop_spte(kvm, spte);
1052                                 --kvm->stat.lpages;
1053                                 spte = NULL;
1054                                 write_protected = 1;
1055                         }
1056                         spte = rmap_next(kvm, rmapp, spte);
1057                 }
1058         }
1059
1060         return write_protected;
1061 }
1062
1063 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1064                            unsigned long data)
1065 {
1066         u64 *spte;
1067         int need_tlb_flush = 0;
1068
1069         while ((spte = rmap_next(kvm, rmapp, NULL))) {
1070                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1071                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1072                 drop_spte(kvm, spte);
1073                 need_tlb_flush = 1;
1074         }
1075         return need_tlb_flush;
1076 }
1077
1078 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1079                              unsigned long data)
1080 {
1081         int need_flush = 0;
1082         u64 *spte, new_spte;
1083         pte_t *ptep = (pte_t *)data;
1084         pfn_t new_pfn;
1085
1086         WARN_ON(pte_huge(*ptep));
1087         new_pfn = pte_pfn(*ptep);
1088         spte = rmap_next(kvm, rmapp, NULL);
1089         while (spte) {
1090                 BUG_ON(!is_shadow_present_pte(*spte));
1091                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1092                 need_flush = 1;
1093                 if (pte_write(*ptep)) {
1094                         drop_spte(kvm, spte);
1095                         spte = rmap_next(kvm, rmapp, NULL);
1096                 } else {
1097                         new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1098                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1099
1100                         new_spte &= ~PT_WRITABLE_MASK;
1101                         new_spte &= ~SPTE_HOST_WRITEABLE;
1102                         new_spte &= ~shadow_accessed_mask;
1103                         mmu_spte_clear_track_bits(spte);
1104                         mmu_spte_set(spte, new_spte);
1105                         spte = rmap_next(kvm, rmapp, spte);
1106                 }
1107         }
1108         if (need_flush)
1109                 kvm_flush_remote_tlbs(kvm);
1110
1111         return 0;
1112 }
1113
1114 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1115                           unsigned long data,
1116                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1117                                          unsigned long data))
1118 {
1119         int i, j;
1120         int ret;
1121         int retval = 0;
1122         struct kvm_memslots *slots;
1123
1124         slots = kvm_memslots(kvm);
1125
1126         for (i = 0; i < slots->nmemslots; i++) {
1127                 struct kvm_memory_slot *memslot = &slots->memslots[i];
1128                 unsigned long start = memslot->userspace_addr;
1129                 unsigned long end;
1130
1131                 end = start + (memslot->npages << PAGE_SHIFT);
1132                 if (hva >= start && hva < end) {
1133                         gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1134                         gfn_t gfn = memslot->base_gfn + gfn_offset;
1135
1136                         ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1137
1138                         for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1139                                 struct kvm_lpage_info *linfo;
1140
1141                                 linfo = lpage_info_slot(gfn, memslot,
1142                                                         PT_DIRECTORY_LEVEL + j);
1143                                 ret |= handler(kvm, &linfo->rmap_pde, data);
1144                         }
1145                         trace_kvm_age_page(hva, memslot, ret);
1146                         retval |= ret;
1147                 }
1148         }
1149
1150         return retval;
1151 }
1152
1153 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1154 {
1155         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1156 }
1157
1158 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1159 {
1160         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1161 }
1162
1163 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1164                          unsigned long data)
1165 {
1166         u64 *spte;
1167         int young = 0;
1168
1169         /*
1170          * Emulate the accessed bit for EPT, by checking if this page has
1171          * an EPT mapping, and clearing it if it does. On the next access,
1172          * a new EPT mapping will be established.
1173          * This has some overhead, but not as much as the cost of swapping
1174          * out actively used pages or breaking up actively used hugepages.
1175          */
1176         if (!shadow_accessed_mask)
1177                 return kvm_unmap_rmapp(kvm, rmapp, data);
1178
1179         spte = rmap_next(kvm, rmapp, NULL);
1180         while (spte) {
1181                 int _young;
1182                 u64 _spte = *spte;
1183                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1184                 _young = _spte & PT_ACCESSED_MASK;
1185                 if (_young) {
1186                         young = 1;
1187                         clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1188                 }
1189                 spte = rmap_next(kvm, rmapp, spte);
1190         }
1191         return young;
1192 }
1193
1194 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1195                               unsigned long data)
1196 {
1197         u64 *spte;
1198         int young = 0;
1199
1200         /*
1201          * If there's no access bit in the secondary pte set by the
1202          * hardware it's up to gup-fast/gup to set the access bit in
1203          * the primary pte or in the page structure.
1204          */
1205         if (!shadow_accessed_mask)
1206                 goto out;
1207
1208         spte = rmap_next(kvm, rmapp, NULL);
1209         while (spte) {
1210                 u64 _spte = *spte;
1211                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1212                 young = _spte & PT_ACCESSED_MASK;
1213                 if (young) {
1214                         young = 1;
1215                         break;
1216                 }
1217                 spte = rmap_next(kvm, rmapp, spte);
1218         }
1219 out:
1220         return young;
1221 }
1222
1223 #define RMAP_RECYCLE_THRESHOLD 1000
1224
1225 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1226 {
1227         unsigned long *rmapp;
1228         struct kvm_mmu_page *sp;
1229
1230         sp = page_header(__pa(spte));
1231
1232         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1233
1234         kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1235         kvm_flush_remote_tlbs(vcpu->kvm);
1236 }
1237
1238 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1239 {
1240         return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1241 }
1242
1243 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1244 {
1245         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1246 }
1247
1248 #ifdef MMU_DEBUG
1249 static int is_empty_shadow_page(u64 *spt)
1250 {
1251         u64 *pos;
1252         u64 *end;
1253
1254         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1255                 if (is_shadow_present_pte(*pos)) {
1256                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1257                                pos, *pos);
1258                         return 0;
1259                 }
1260         return 1;
1261 }
1262 #endif
1263
1264 /*
1265  * This value is the sum of all of the kvm instances's
1266  * kvm->arch.n_used_mmu_pages values.  We need a global,
1267  * aggregate version in order to make the slab shrinker
1268  * faster
1269  */
1270 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1271 {
1272         kvm->arch.n_used_mmu_pages += nr;
1273         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1274 }
1275
1276 /*
1277  * Remove the sp from shadow page cache, after call it,
1278  * we can not find this sp from the cache, and the shadow
1279  * page table is still valid.
1280  * It should be under the protection of mmu lock.
1281  */
1282 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1283 {
1284         ASSERT(is_empty_shadow_page(sp->spt));
1285         hlist_del(&sp->hash_link);
1286         if (!sp->role.direct)
1287                 free_page((unsigned long)sp->gfns);
1288 }
1289
1290 /*
1291  * Free the shadow page table and the sp, we can do it
1292  * out of the protection of mmu lock.
1293  */
1294 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1295 {
1296         list_del(&sp->link);
1297         free_page((unsigned long)sp->spt);
1298         kmem_cache_free(mmu_page_header_cache, sp);
1299 }
1300
1301 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1302 {
1303         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1304 }
1305
1306 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1307                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1308 {
1309         if (!parent_pte)
1310                 return;
1311
1312         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1313 }
1314
1315 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1316                                        u64 *parent_pte)
1317 {
1318         pte_list_remove(parent_pte, &sp->parent_ptes);
1319 }
1320
1321 static void drop_parent_pte(struct kvm_mmu_page *sp,
1322                             u64 *parent_pte)
1323 {
1324         mmu_page_remove_parent_pte(sp, parent_pte);
1325         mmu_spte_clear_no_track(parent_pte);
1326 }
1327
1328 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1329                                                u64 *parent_pte, int direct)
1330 {
1331         struct kvm_mmu_page *sp;
1332         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1333                                         sizeof *sp);
1334         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1335         if (!direct)
1336                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1337                                                   PAGE_SIZE);
1338         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1339         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1340         bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1341         sp->parent_ptes = 0;
1342         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1343         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1344         return sp;
1345 }
1346
1347 static void mark_unsync(u64 *spte);
1348 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1349 {
1350         pte_list_walk(&sp->parent_ptes, mark_unsync);
1351 }
1352
1353 static void mark_unsync(u64 *spte)
1354 {
1355         struct kvm_mmu_page *sp;
1356         unsigned int index;
1357
1358         sp = page_header(__pa(spte));
1359         index = spte - sp->spt;
1360         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1361                 return;
1362         if (sp->unsync_children++)
1363                 return;
1364         kvm_mmu_mark_parents_unsync(sp);
1365 }
1366
1367 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1368                                struct kvm_mmu_page *sp)
1369 {
1370         return 1;
1371 }
1372
1373 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1374 {
1375 }
1376
1377 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1378                                  struct kvm_mmu_page *sp, u64 *spte,
1379                                  const void *pte)
1380 {
1381         WARN_ON(1);
1382 }
1383
1384 #define KVM_PAGE_ARRAY_NR 16
1385
1386 struct kvm_mmu_pages {
1387         struct mmu_page_and_offset {
1388                 struct kvm_mmu_page *sp;
1389                 unsigned int idx;
1390         } page[KVM_PAGE_ARRAY_NR];
1391         unsigned int nr;
1392 };
1393
1394 #define for_each_unsync_children(bitmap, idx)           \
1395         for (idx = find_first_bit(bitmap, 512);         \
1396              idx < 512;                                 \
1397              idx = find_next_bit(bitmap, 512, idx+1))
1398
1399 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1400                          int idx)
1401 {
1402         int i;
1403
1404         if (sp->unsync)
1405                 for (i=0; i < pvec->nr; i++)
1406                         if (pvec->page[i].sp == sp)
1407                                 return 0;
1408
1409         pvec->page[pvec->nr].sp = sp;
1410         pvec->page[pvec->nr].idx = idx;
1411         pvec->nr++;
1412         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1413 }
1414
1415 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1416                            struct kvm_mmu_pages *pvec)
1417 {
1418         int i, ret, nr_unsync_leaf = 0;
1419
1420         for_each_unsync_children(sp->unsync_child_bitmap, i) {
1421                 struct kvm_mmu_page *child;
1422                 u64 ent = sp->spt[i];
1423
1424                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1425                         goto clear_child_bitmap;
1426
1427                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1428
1429                 if (child->unsync_children) {
1430                         if (mmu_pages_add(pvec, child, i))
1431                                 return -ENOSPC;
1432
1433                         ret = __mmu_unsync_walk(child, pvec);
1434                         if (!ret)
1435                                 goto clear_child_bitmap;
1436                         else if (ret > 0)
1437                                 nr_unsync_leaf += ret;
1438                         else
1439                                 return ret;
1440                 } else if (child->unsync) {
1441                         nr_unsync_leaf++;
1442                         if (mmu_pages_add(pvec, child, i))
1443                                 return -ENOSPC;
1444                 } else
1445                          goto clear_child_bitmap;
1446
1447                 continue;
1448
1449 clear_child_bitmap:
1450                 __clear_bit(i, sp->unsync_child_bitmap);
1451                 sp->unsync_children--;
1452                 WARN_ON((int)sp->unsync_children < 0);
1453         }
1454
1455
1456         return nr_unsync_leaf;
1457 }
1458
1459 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1460                            struct kvm_mmu_pages *pvec)
1461 {
1462         if (!sp->unsync_children)
1463                 return 0;
1464
1465         mmu_pages_add(pvec, sp, 0);
1466         return __mmu_unsync_walk(sp, pvec);
1467 }
1468
1469 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1470 {
1471         WARN_ON(!sp->unsync);
1472         trace_kvm_mmu_sync_page(sp);
1473         sp->unsync = 0;
1474         --kvm->stat.mmu_unsync;
1475 }
1476
1477 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1478                                     struct list_head *invalid_list);
1479 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1480                                     struct list_head *invalid_list);
1481
1482 #define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
1483   hlist_for_each_entry(sp, pos,                                         \
1484    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1485         if ((sp)->gfn != (gfn)) {} else
1486
1487 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
1488   hlist_for_each_entry(sp, pos,                                         \
1489    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1490                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1491                         (sp)->role.invalid) {} else
1492
1493 /* @sp->gfn should be write-protected at the call site */
1494 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1495                            struct list_head *invalid_list, bool clear_unsync)
1496 {
1497         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1498                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1499                 return 1;
1500         }
1501
1502         if (clear_unsync)
1503                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1504
1505         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1506                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1507                 return 1;
1508         }
1509
1510         kvm_mmu_flush_tlb(vcpu);
1511         return 0;
1512 }
1513
1514 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1515                                    struct kvm_mmu_page *sp)
1516 {
1517         LIST_HEAD(invalid_list);
1518         int ret;
1519
1520         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1521         if (ret)
1522                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1523
1524         return ret;
1525 }
1526
1527 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1528                          struct list_head *invalid_list)
1529 {
1530         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1531 }
1532
1533 /* @gfn should be write-protected at the call site */
1534 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1535 {
1536         struct kvm_mmu_page *s;
1537         struct hlist_node *node;
1538         LIST_HEAD(invalid_list);
1539         bool flush = false;
1540
1541         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1542                 if (!s->unsync)
1543                         continue;
1544
1545                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1546                 kvm_unlink_unsync_page(vcpu->kvm, s);
1547                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1548                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1549                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1550                         continue;
1551                 }
1552                 flush = true;
1553         }
1554
1555         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1556         if (flush)
1557                 kvm_mmu_flush_tlb(vcpu);
1558 }
1559
1560 struct mmu_page_path {
1561         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1562         unsigned int idx[PT64_ROOT_LEVEL-1];
1563 };
1564
1565 #define for_each_sp(pvec, sp, parents, i)                       \
1566                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1567                         sp = pvec.page[i].sp;                   \
1568                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1569                         i = mmu_pages_next(&pvec, &parents, i))
1570
1571 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1572                           struct mmu_page_path *parents,
1573                           int i)
1574 {
1575         int n;
1576
1577         for (n = i+1; n < pvec->nr; n++) {
1578                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1579
1580                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1581                         parents->idx[0] = pvec->page[n].idx;
1582                         return n;
1583                 }
1584
1585                 parents->parent[sp->role.level-2] = sp;
1586                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1587         }
1588
1589         return n;
1590 }
1591
1592 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1593 {
1594         struct kvm_mmu_page *sp;
1595         unsigned int level = 0;
1596
1597         do {
1598                 unsigned int idx = parents->idx[level];
1599
1600                 sp = parents->parent[level];
1601                 if (!sp)
1602                         return;
1603
1604                 --sp->unsync_children;
1605                 WARN_ON((int)sp->unsync_children < 0);
1606                 __clear_bit(idx, sp->unsync_child_bitmap);
1607                 level++;
1608         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1609 }
1610
1611 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1612                                struct mmu_page_path *parents,
1613                                struct kvm_mmu_pages *pvec)
1614 {
1615         parents->parent[parent->role.level-1] = NULL;
1616         pvec->nr = 0;
1617 }
1618
1619 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1620                               struct kvm_mmu_page *parent)
1621 {
1622         int i;
1623         struct kvm_mmu_page *sp;
1624         struct mmu_page_path parents;
1625         struct kvm_mmu_pages pages;
1626         LIST_HEAD(invalid_list);
1627
1628         kvm_mmu_pages_init(parent, &parents, &pages);
1629         while (mmu_unsync_walk(parent, &pages)) {
1630                 int protected = 0;
1631
1632                 for_each_sp(pages, sp, parents, i)
1633                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1634
1635                 if (protected)
1636                         kvm_flush_remote_tlbs(vcpu->kvm);
1637
1638                 for_each_sp(pages, sp, parents, i) {
1639                         kvm_sync_page(vcpu, sp, &invalid_list);
1640                         mmu_pages_clear_parents(&parents);
1641                 }
1642                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1643                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1644                 kvm_mmu_pages_init(parent, &parents, &pages);
1645         }
1646 }
1647
1648 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1649 {
1650         int i;
1651
1652         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1653                 sp->spt[i] = 0ull;
1654 }
1655
1656 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1657                                              gfn_t gfn,
1658                                              gva_t gaddr,
1659                                              unsigned level,
1660                                              int direct,
1661                                              unsigned access,
1662                                              u64 *parent_pte)
1663 {
1664         union kvm_mmu_page_role role;
1665         unsigned quadrant;
1666         struct kvm_mmu_page *sp;
1667         struct hlist_node *node;
1668         bool need_sync = false;
1669
1670         role = vcpu->arch.mmu.base_role;
1671         role.level = level;
1672         role.direct = direct;
1673         if (role.direct)
1674                 role.cr4_pae = 0;
1675         role.access = access;
1676         if (!vcpu->arch.mmu.direct_map
1677             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1678                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1679                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1680                 role.quadrant = quadrant;
1681         }
1682         for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1683                 if (!need_sync && sp->unsync)
1684                         need_sync = true;
1685
1686                 if (sp->role.word != role.word)
1687                         continue;
1688
1689                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1690                         break;
1691
1692                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1693                 if (sp->unsync_children) {
1694                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1695                         kvm_mmu_mark_parents_unsync(sp);
1696                 } else if (sp->unsync)
1697                         kvm_mmu_mark_parents_unsync(sp);
1698
1699                 trace_kvm_mmu_get_page(sp, false);
1700                 return sp;
1701         }
1702         ++vcpu->kvm->stat.mmu_cache_miss;
1703         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1704         if (!sp)
1705                 return sp;
1706         sp->gfn = gfn;
1707         sp->role = role;
1708         hlist_add_head(&sp->hash_link,
1709                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1710         if (!direct) {
1711                 if (rmap_write_protect(vcpu->kvm, gfn))
1712                         kvm_flush_remote_tlbs(vcpu->kvm);
1713                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1714                         kvm_sync_pages(vcpu, gfn);
1715
1716                 account_shadowed(vcpu->kvm, gfn);
1717         }
1718         init_shadow_page_table(sp);
1719         trace_kvm_mmu_get_page(sp, true);
1720         return sp;
1721 }
1722
1723 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1724                              struct kvm_vcpu *vcpu, u64 addr)
1725 {
1726         iterator->addr = addr;
1727         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1728         iterator->level = vcpu->arch.mmu.shadow_root_level;
1729
1730         if (iterator->level == PT64_ROOT_LEVEL &&
1731             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1732             !vcpu->arch.mmu.direct_map)
1733                 --iterator->level;
1734
1735         if (iterator->level == PT32E_ROOT_LEVEL) {
1736                 iterator->shadow_addr
1737                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1738                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1739                 --iterator->level;
1740                 if (!iterator->shadow_addr)
1741                         iterator->level = 0;
1742         }
1743 }
1744
1745 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1746 {
1747         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1748                 return false;
1749
1750         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1751         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1752         return true;
1753 }
1754
1755 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1756                                u64 spte)
1757 {
1758         if (is_last_spte(spte, iterator->level)) {
1759                 iterator->level = 0;
1760                 return;
1761         }
1762
1763         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1764         --iterator->level;
1765 }
1766
1767 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1768 {
1769         return __shadow_walk_next(iterator, *iterator->sptep);
1770 }
1771
1772 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1773 {
1774         u64 spte;
1775
1776         spte = __pa(sp->spt)
1777                 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1778                 | PT_WRITABLE_MASK | PT_USER_MASK;
1779         mmu_spte_set(sptep, spte);
1780 }
1781
1782 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1783 {
1784         if (is_large_pte(*sptep)) {
1785                 drop_spte(vcpu->kvm, sptep);
1786                 kvm_flush_remote_tlbs(vcpu->kvm);
1787         }
1788 }
1789
1790 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1791                                    unsigned direct_access)
1792 {
1793         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1794                 struct kvm_mmu_page *child;
1795
1796                 /*
1797                  * For the direct sp, if the guest pte's dirty bit
1798                  * changed form clean to dirty, it will corrupt the
1799                  * sp's access: allow writable in the read-only sp,
1800                  * so we should update the spte at this point to get
1801                  * a new sp with the correct access.
1802                  */
1803                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1804                 if (child->role.access == direct_access)
1805                         return;
1806
1807                 drop_parent_pte(child, sptep);
1808                 kvm_flush_remote_tlbs(vcpu->kvm);
1809         }
1810 }
1811
1812 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1813                              u64 *spte)
1814 {
1815         u64 pte;
1816         struct kvm_mmu_page *child;
1817
1818         pte = *spte;
1819         if (is_shadow_present_pte(pte)) {
1820                 if (is_last_spte(pte, sp->role.level)) {
1821                         drop_spte(kvm, spte);
1822                         if (is_large_pte(pte))
1823                                 --kvm->stat.lpages;
1824                 } else {
1825                         child = page_header(pte & PT64_BASE_ADDR_MASK);
1826                         drop_parent_pte(child, spte);
1827                 }
1828                 return true;
1829         }
1830
1831         if (is_mmio_spte(pte))
1832                 mmu_spte_clear_no_track(spte);
1833
1834         return false;
1835 }
1836
1837 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1838                                          struct kvm_mmu_page *sp)
1839 {
1840         unsigned i;
1841
1842         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1843                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1844 }
1845
1846 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1847 {
1848         mmu_page_remove_parent_pte(sp, parent_pte);
1849 }
1850
1851 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1852 {
1853         int i;
1854         struct kvm_vcpu *vcpu;
1855
1856         kvm_for_each_vcpu(i, vcpu, kvm)
1857                 vcpu->arch.last_pte_updated = NULL;
1858 }
1859
1860 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1861 {
1862         u64 *parent_pte;
1863
1864         while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1865                 drop_parent_pte(sp, parent_pte);
1866 }
1867
1868 static int mmu_zap_unsync_children(struct kvm *kvm,
1869                                    struct kvm_mmu_page *parent,
1870                                    struct list_head *invalid_list)
1871 {
1872         int i, zapped = 0;
1873         struct mmu_page_path parents;
1874         struct kvm_mmu_pages pages;
1875
1876         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1877                 return 0;
1878
1879         kvm_mmu_pages_init(parent, &parents, &pages);
1880         while (mmu_unsync_walk(parent, &pages)) {
1881                 struct kvm_mmu_page *sp;
1882
1883                 for_each_sp(pages, sp, parents, i) {
1884                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1885                         mmu_pages_clear_parents(&parents);
1886                         zapped++;
1887                 }
1888                 kvm_mmu_pages_init(parent, &parents, &pages);
1889         }
1890
1891         return zapped;
1892 }
1893
1894 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1895                                     struct list_head *invalid_list)
1896 {
1897         int ret;
1898
1899         trace_kvm_mmu_prepare_zap_page(sp);
1900         ++kvm->stat.mmu_shadow_zapped;
1901         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1902         kvm_mmu_page_unlink_children(kvm, sp);
1903         kvm_mmu_unlink_parents(kvm, sp);
1904         if (!sp->role.invalid && !sp->role.direct)
1905                 unaccount_shadowed(kvm, sp->gfn);
1906         if (sp->unsync)
1907                 kvm_unlink_unsync_page(kvm, sp);
1908         if (!sp->root_count) {
1909                 /* Count self */
1910                 ret++;
1911                 list_move(&sp->link, invalid_list);
1912                 kvm_mod_used_mmu_pages(kvm, -1);
1913         } else {
1914                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1915                 kvm_reload_remote_mmus(kvm);
1916         }
1917
1918         sp->role.invalid = 1;
1919         kvm_mmu_reset_last_pte_updated(kvm);
1920         return ret;
1921 }
1922
1923 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1924 {
1925         struct kvm_mmu_page *sp;
1926
1927         list_for_each_entry(sp, invalid_list, link)
1928                 kvm_mmu_isolate_page(sp);
1929 }
1930
1931 static void free_pages_rcu(struct rcu_head *head)
1932 {
1933         struct kvm_mmu_page *next, *sp;
1934
1935         sp = container_of(head, struct kvm_mmu_page, rcu);
1936         while (sp) {
1937                 if (!list_empty(&sp->link))
1938                         next = list_first_entry(&sp->link,
1939                                       struct kvm_mmu_page, link);
1940                 else
1941                         next = NULL;
1942                 kvm_mmu_free_page(sp);
1943                 sp = next;
1944         }
1945 }
1946
1947 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1948                                     struct list_head *invalid_list)
1949 {
1950         struct kvm_mmu_page *sp;
1951
1952         if (list_empty(invalid_list))
1953                 return;
1954
1955         kvm_flush_remote_tlbs(kvm);
1956
1957         if (atomic_read(&kvm->arch.reader_counter)) {
1958                 kvm_mmu_isolate_pages(invalid_list);
1959                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1960                 list_del_init(invalid_list);
1961
1962                 trace_kvm_mmu_delay_free_pages(sp);
1963                 call_rcu(&sp->rcu, free_pages_rcu);
1964                 return;
1965         }
1966
1967         do {
1968                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1969                 WARN_ON(!sp->role.invalid || sp->root_count);
1970                 kvm_mmu_isolate_page(sp);
1971                 kvm_mmu_free_page(sp);
1972         } while (!list_empty(invalid_list));
1973
1974 }
1975
1976 /*
1977  * Changing the number of mmu pages allocated to the vm
1978  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1979  */
1980 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1981 {
1982         LIST_HEAD(invalid_list);
1983         /*
1984          * If we set the number of mmu pages to be smaller be than the
1985          * number of actived pages , we must to free some mmu pages before we
1986          * change the value
1987          */
1988
1989         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1990                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1991                         !list_empty(&kvm->arch.active_mmu_pages)) {
1992                         struct kvm_mmu_page *page;
1993
1994                         page = container_of(kvm->arch.active_mmu_pages.prev,
1995                                             struct kvm_mmu_page, link);
1996                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1997                 }
1998                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1999                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2000         }
2001
2002         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2003 }
2004
2005 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2006 {
2007         struct kvm_mmu_page *sp;
2008         struct hlist_node *node;
2009         LIST_HEAD(invalid_list);
2010         int r;
2011
2012         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2013         r = 0;
2014         spin_lock(&kvm->mmu_lock);
2015         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2016                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2017                          sp->role.word);
2018                 r = 1;
2019                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2020         }
2021         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2022         spin_unlock(&kvm->mmu_lock);
2023
2024         return r;
2025 }
2026 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2027
2028 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
2029 {
2030         struct kvm_mmu_page *sp;
2031         struct hlist_node *node;
2032         LIST_HEAD(invalid_list);
2033
2034         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2035                 pgprintk("%s: zap %llx %x\n",
2036                          __func__, gfn, sp->role.word);
2037                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2038         }
2039         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2040 }
2041
2042 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2043 {
2044         int slot = memslot_id(kvm, gfn);
2045         struct kvm_mmu_page *sp = page_header(__pa(pte));
2046
2047         __set_bit(slot, sp->slot_bitmap);
2048 }
2049
2050 /*
2051  * The function is based on mtrr_type_lookup() in
2052  * arch/x86/kernel/cpu/mtrr/generic.c
2053  */
2054 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2055                          u64 start, u64 end)
2056 {
2057         int i;
2058         u64 base, mask;
2059         u8 prev_match, curr_match;
2060         int num_var_ranges = KVM_NR_VAR_MTRR;
2061
2062         if (!mtrr_state->enabled)
2063                 return 0xFF;
2064
2065         /* Make end inclusive end, instead of exclusive */
2066         end--;
2067
2068         /* Look in fixed ranges. Just return the type as per start */
2069         if (mtrr_state->have_fixed && (start < 0x100000)) {
2070                 int idx;
2071
2072                 if (start < 0x80000) {
2073                         idx = 0;
2074                         idx += (start >> 16);
2075                         return mtrr_state->fixed_ranges[idx];
2076                 } else if (start < 0xC0000) {
2077                         idx = 1 * 8;
2078                         idx += ((start - 0x80000) >> 14);
2079                         return mtrr_state->fixed_ranges[idx];
2080                 } else if (start < 0x1000000) {
2081                         idx = 3 * 8;
2082                         idx += ((start - 0xC0000) >> 12);
2083                         return mtrr_state->fixed_ranges[idx];
2084                 }
2085         }
2086
2087         /*
2088          * Look in variable ranges
2089          * Look of multiple ranges matching this address and pick type
2090          * as per MTRR precedence
2091          */
2092         if (!(mtrr_state->enabled & 2))
2093                 return mtrr_state->def_type;
2094
2095         prev_match = 0xFF;
2096         for (i = 0; i < num_var_ranges; ++i) {
2097                 unsigned short start_state, end_state;
2098
2099                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2100                         continue;
2101
2102                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2103                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2104                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2105                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2106
2107                 start_state = ((start & mask) == (base & mask));
2108                 end_state = ((end & mask) == (base & mask));
2109                 if (start_state != end_state)
2110                         return 0xFE;
2111
2112                 if ((start & mask) != (base & mask))
2113                         continue;
2114
2115                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2116                 if (prev_match == 0xFF) {
2117                         prev_match = curr_match;
2118                         continue;
2119                 }
2120
2121                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2122                     curr_match == MTRR_TYPE_UNCACHABLE)
2123                         return MTRR_TYPE_UNCACHABLE;
2124
2125                 if ((prev_match == MTRR_TYPE_WRBACK &&
2126                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2127                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2128                      curr_match == MTRR_TYPE_WRBACK)) {
2129                         prev_match = MTRR_TYPE_WRTHROUGH;
2130                         curr_match = MTRR_TYPE_WRTHROUGH;
2131                 }
2132
2133                 if (prev_match != curr_match)
2134                         return MTRR_TYPE_UNCACHABLE;
2135         }
2136
2137         if (prev_match != 0xFF)
2138                 return prev_match;
2139
2140         return mtrr_state->def_type;
2141 }
2142
2143 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2144 {
2145         u8 mtrr;
2146
2147         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2148                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2149         if (mtrr == 0xfe || mtrr == 0xff)
2150                 mtrr = MTRR_TYPE_WRBACK;
2151         return mtrr;
2152 }
2153 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2154
2155 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2156 {
2157         trace_kvm_mmu_unsync_page(sp);
2158         ++vcpu->kvm->stat.mmu_unsync;
2159         sp->unsync = 1;
2160
2161         kvm_mmu_mark_parents_unsync(sp);
2162 }
2163
2164 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2165 {
2166         struct kvm_mmu_page *s;
2167         struct hlist_node *node;
2168
2169         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2170                 if (s->unsync)
2171                         continue;
2172                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2173                 __kvm_unsync_page(vcpu, s);
2174         }
2175 }
2176
2177 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2178                                   bool can_unsync)
2179 {
2180         struct kvm_mmu_page *s;
2181         struct hlist_node *node;
2182         bool need_unsync = false;
2183
2184         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2185                 if (!can_unsync)
2186                         return 1;
2187
2188                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2189                         return 1;
2190
2191                 if (!need_unsync && !s->unsync) {
2192                         if (!oos_shadow)
2193                                 return 1;
2194                         need_unsync = true;
2195                 }
2196         }
2197         if (need_unsync)
2198                 kvm_unsync_pages(vcpu, gfn);
2199         return 0;
2200 }
2201
2202 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2203                     unsigned pte_access, int user_fault,
2204                     int write_fault, int level,
2205                     gfn_t gfn, pfn_t pfn, bool speculative,
2206                     bool can_unsync, bool host_writable)
2207 {
2208         u64 spte, entry = *sptep;
2209         int ret = 0;
2210
2211         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2212                 return 0;
2213
2214         spte = PT_PRESENT_MASK;
2215         if (!speculative)
2216                 spte |= shadow_accessed_mask;
2217
2218         if (pte_access & ACC_EXEC_MASK)
2219                 spte |= shadow_x_mask;
2220         else
2221                 spte |= shadow_nx_mask;
2222         if (pte_access & ACC_USER_MASK)
2223                 spte |= shadow_user_mask;
2224         if (level > PT_PAGE_TABLE_LEVEL)
2225                 spte |= PT_PAGE_SIZE_MASK;
2226         if (tdp_enabled)
2227                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2228                         kvm_is_mmio_pfn(pfn));
2229
2230         if (host_writable)
2231                 spte |= SPTE_HOST_WRITEABLE;
2232         else
2233                 pte_access &= ~ACC_WRITE_MASK;
2234
2235         spte |= (u64)pfn << PAGE_SHIFT;
2236
2237         if ((pte_access & ACC_WRITE_MASK)
2238             || (!vcpu->arch.mmu.direct_map && write_fault
2239                 && !is_write_protection(vcpu) && !user_fault)) {
2240
2241                 if (level > PT_PAGE_TABLE_LEVEL &&
2242                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
2243                         ret = 1;
2244                         drop_spte(vcpu->kvm, sptep);
2245                         goto done;
2246                 }
2247
2248                 spte |= PT_WRITABLE_MASK;
2249
2250                 if (!vcpu->arch.mmu.direct_map
2251                     && !(pte_access & ACC_WRITE_MASK)) {
2252                         spte &= ~PT_USER_MASK;
2253                         /*
2254                          * If we converted a user page to a kernel page,
2255                          * so that the kernel can write to it when cr0.wp=0,
2256                          * then we should prevent the kernel from executing it
2257                          * if SMEP is enabled.
2258                          */
2259                         if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2260                                 spte |= PT64_NX_MASK;
2261                 }
2262
2263                 /*
2264                  * Optimization: for pte sync, if spte was writable the hash
2265                  * lookup is unnecessary (and expensive). Write protection
2266                  * is responsibility of mmu_get_page / kvm_sync_page.
2267                  * Same reasoning can be applied to dirty page accounting.
2268                  */
2269                 if (!can_unsync && is_writable_pte(*sptep))
2270                         goto set_pte;
2271
2272                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2273                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2274                                  __func__, gfn);
2275                         ret = 1;
2276                         pte_access &= ~ACC_WRITE_MASK;
2277                         if (is_writable_pte(spte))
2278                                 spte &= ~PT_WRITABLE_MASK;
2279                 }
2280         }
2281
2282         if (pte_access & ACC_WRITE_MASK)
2283                 mark_page_dirty(vcpu->kvm, gfn);
2284
2285 set_pte:
2286         mmu_spte_update(sptep, spte);
2287         /*
2288          * If we overwrite a writable spte with a read-only one we
2289          * should flush remote TLBs. Otherwise rmap_write_protect
2290          * will find a read-only spte, even though the writable spte
2291          * might be cached on a CPU's TLB.
2292          */
2293         if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2294                 kvm_flush_remote_tlbs(vcpu->kvm);
2295 done:
2296         return ret;
2297 }
2298
2299 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2300                          unsigned pt_access, unsigned pte_access,
2301                          int user_fault, int write_fault,
2302                          int *emulate, int level, gfn_t gfn,
2303                          pfn_t pfn, bool speculative,
2304                          bool host_writable)
2305 {
2306         int was_rmapped = 0;
2307         int rmap_count;
2308
2309         pgprintk("%s: spte %llx access %x write_fault %d"
2310                  " user_fault %d gfn %llx\n",
2311                  __func__, *sptep, pt_access,
2312                  write_fault, user_fault, gfn);
2313
2314         if (is_rmap_spte(*sptep)) {
2315                 /*
2316                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2317                  * the parent of the now unreachable PTE.
2318                  */
2319                 if (level > PT_PAGE_TABLE_LEVEL &&
2320                     !is_large_pte(*sptep)) {
2321                         struct kvm_mmu_page *child;
2322                         u64 pte = *sptep;
2323
2324                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2325                         drop_parent_pte(child, sptep);
2326                         kvm_flush_remote_tlbs(vcpu->kvm);
2327                 } else if (pfn != spte_to_pfn(*sptep)) {
2328                         pgprintk("hfn old %llx new %llx\n",
2329                                  spte_to_pfn(*sptep), pfn);
2330                         drop_spte(vcpu->kvm, sptep);
2331                         kvm_flush_remote_tlbs(vcpu->kvm);
2332                 } else
2333                         was_rmapped = 1;
2334         }
2335
2336         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2337                       level, gfn, pfn, speculative, true,
2338                       host_writable)) {
2339                 if (write_fault)
2340                         *emulate = 1;
2341                 kvm_mmu_flush_tlb(vcpu);
2342         }
2343
2344         if (unlikely(is_mmio_spte(*sptep) && emulate))
2345                 *emulate = 1;
2346
2347         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2348         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2349                  is_large_pte(*sptep)? "2MB" : "4kB",
2350                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2351                  *sptep, sptep);
2352         if (!was_rmapped && is_large_pte(*sptep))
2353                 ++vcpu->kvm->stat.lpages;
2354
2355         if (is_shadow_present_pte(*sptep)) {
2356                 page_header_update_slot(vcpu->kvm, sptep, gfn);
2357                 if (!was_rmapped) {
2358                         rmap_count = rmap_add(vcpu, sptep, gfn);
2359                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2360                                 rmap_recycle(vcpu, sptep, gfn);
2361                 }
2362         }
2363         kvm_release_pfn_clean(pfn);
2364         if (speculative)
2365                 vcpu->arch.last_pte_updated = sptep;
2366 }
2367
2368 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2369 {
2370 }
2371
2372 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2373                                      bool no_dirty_log)
2374 {
2375         struct kvm_memory_slot *slot;
2376         unsigned long hva;
2377
2378         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2379         if (!slot) {
2380                 get_page(fault_page);
2381                 return page_to_pfn(fault_page);
2382         }
2383
2384         hva = gfn_to_hva_memslot(slot, gfn);
2385
2386         return hva_to_pfn_atomic(vcpu->kvm, hva);
2387 }
2388
2389 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2390                                     struct kvm_mmu_page *sp,
2391                                     u64 *start, u64 *end)
2392 {
2393         struct page *pages[PTE_PREFETCH_NUM];
2394         unsigned access = sp->role.access;
2395         int i, ret;
2396         gfn_t gfn;
2397
2398         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2399         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2400                 return -1;
2401
2402         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2403         if (ret <= 0)
2404                 return -1;
2405
2406         for (i = 0; i < ret; i++, gfn++, start++)
2407                 mmu_set_spte(vcpu, start, ACC_ALL,
2408                              access, 0, 0, NULL,
2409                              sp->role.level, gfn,
2410                              page_to_pfn(pages[i]), true, true);
2411
2412         return 0;
2413 }
2414
2415 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2416                                   struct kvm_mmu_page *sp, u64 *sptep)
2417 {
2418         u64 *spte, *start = NULL;
2419         int i;
2420
2421         WARN_ON(!sp->role.direct);
2422
2423         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2424         spte = sp->spt + i;
2425
2426         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2427                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2428                         if (!start)
2429                                 continue;
2430                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2431                                 break;
2432                         start = NULL;
2433                 } else if (!start)
2434                         start = spte;
2435         }
2436 }
2437
2438 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2439 {
2440         struct kvm_mmu_page *sp;
2441
2442         /*
2443          * Since it's no accessed bit on EPT, it's no way to
2444          * distinguish between actually accessed translations
2445          * and prefetched, so disable pte prefetch if EPT is
2446          * enabled.
2447          */
2448         if (!shadow_accessed_mask)
2449                 return;
2450
2451         sp = page_header(__pa(sptep));
2452         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2453                 return;
2454
2455         __direct_pte_prefetch(vcpu, sp, sptep);
2456 }
2457
2458 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2459                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2460                         bool prefault)
2461 {
2462         struct kvm_shadow_walk_iterator iterator;
2463         struct kvm_mmu_page *sp;
2464         int emulate = 0;
2465         gfn_t pseudo_gfn;
2466
2467         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2468                 if (iterator.level == level) {
2469                         unsigned pte_access = ACC_ALL;
2470
2471                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2472                                      0, write, &emulate,
2473                                      level, gfn, pfn, prefault, map_writable);
2474                         direct_pte_prefetch(vcpu, iterator.sptep);
2475                         ++vcpu->stat.pf_fixed;
2476                         break;
2477                 }
2478
2479                 if (!is_shadow_present_pte(*iterator.sptep)) {
2480                         u64 base_addr = iterator.addr;
2481
2482                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2483                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2484                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2485                                               iterator.level - 1,
2486                                               1, ACC_ALL, iterator.sptep);
2487                         if (!sp) {
2488                                 pgprintk("nonpaging_map: ENOMEM\n");
2489                                 kvm_release_pfn_clean(pfn);
2490                                 return -ENOMEM;
2491                         }
2492
2493                         mmu_spte_set(iterator.sptep,
2494                                      __pa(sp->spt)
2495                                      | PT_PRESENT_MASK | PT_WRITABLE_MASK
2496                                      | shadow_user_mask | shadow_x_mask
2497                                      | shadow_accessed_mask);
2498                 }
2499         }
2500         return emulate;
2501 }
2502
2503 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2504 {
2505         siginfo_t info;
2506
2507         info.si_signo   = SIGBUS;
2508         info.si_errno   = 0;
2509         info.si_code    = BUS_MCEERR_AR;
2510         info.si_addr    = (void __user *)address;
2511         info.si_addr_lsb = PAGE_SHIFT;
2512
2513         send_sig_info(SIGBUS, &info, tsk);
2514 }
2515
2516 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2517 {
2518         kvm_release_pfn_clean(pfn);
2519         if (is_hwpoison_pfn(pfn)) {
2520                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2521                 return 0;
2522         }
2523
2524         return -EFAULT;
2525 }
2526
2527 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2528                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2529 {
2530         pfn_t pfn = *pfnp;
2531         gfn_t gfn = *gfnp;
2532         int level = *levelp;
2533
2534         /*
2535          * Check if it's a transparent hugepage. If this would be an
2536          * hugetlbfs page, level wouldn't be set to
2537          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2538          * here.
2539          */
2540         if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2541             level == PT_PAGE_TABLE_LEVEL &&
2542             PageTransCompound(pfn_to_page(pfn)) &&
2543             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2544                 unsigned long mask;
2545                 /*
2546                  * mmu_notifier_retry was successful and we hold the
2547                  * mmu_lock here, so the pmd can't become splitting
2548                  * from under us, and in turn
2549                  * __split_huge_page_refcount() can't run from under
2550                  * us and we can safely transfer the refcount from
2551                  * PG_tail to PG_head as we switch the pfn to tail to
2552                  * head.
2553                  */
2554                 *levelp = level = PT_DIRECTORY_LEVEL;
2555                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2556                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2557                 if (pfn & mask) {
2558                         gfn &= ~mask;
2559                         *gfnp = gfn;
2560                         kvm_release_pfn_clean(pfn);
2561                         pfn &= ~mask;
2562                         if (!get_page_unless_zero(pfn_to_page(pfn)))
2563                                 BUG();
2564                         *pfnp = pfn;
2565                 }
2566         }
2567 }
2568
2569 static bool mmu_invalid_pfn(pfn_t pfn)
2570 {
2571         return unlikely(is_invalid_pfn(pfn));
2572 }
2573
2574 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2575                                 pfn_t pfn, unsigned access, int *ret_val)
2576 {
2577         bool ret = true;
2578
2579         /* The pfn is invalid, report the error! */
2580         if (unlikely(is_invalid_pfn(pfn))) {
2581                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2582                 goto exit;
2583         }
2584
2585         if (unlikely(is_noslot_pfn(pfn)))
2586                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2587
2588         ret = false;
2589 exit:
2590         return ret;
2591 }
2592
2593 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2594                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2595
2596 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2597                          bool prefault)
2598 {
2599         int r;
2600         int level;
2601         int force_pt_level;
2602         pfn_t pfn;
2603         unsigned long mmu_seq;
2604         bool map_writable;
2605
2606         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2607         if (likely(!force_pt_level)) {
2608                 level = mapping_level(vcpu, gfn);
2609                 /*
2610                  * This path builds a PAE pagetable - so we can map
2611                  * 2mb pages at maximum. Therefore check if the level
2612                  * is larger than that.
2613                  */
2614                 if (level > PT_DIRECTORY_LEVEL)
2615                         level = PT_DIRECTORY_LEVEL;
2616
2617                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2618         } else
2619                 level = PT_PAGE_TABLE_LEVEL;
2620
2621         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2622         smp_rmb();
2623
2624         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2625                 return 0;
2626
2627         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2628                 return r;
2629
2630         spin_lock(&vcpu->kvm->mmu_lock);
2631         if (mmu_notifier_retry(vcpu, mmu_seq))
2632                 goto out_unlock;
2633         kvm_mmu_free_some_pages(vcpu);
2634         if (likely(!force_pt_level))
2635                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2636         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2637                          prefault);
2638         spin_unlock(&vcpu->kvm->mmu_lock);
2639
2640
2641         return r;
2642
2643 out_unlock:
2644         spin_unlock(&vcpu->kvm->mmu_lock);
2645         kvm_release_pfn_clean(pfn);
2646         return 0;
2647 }
2648
2649
2650 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2651 {
2652         int i;
2653         struct kvm_mmu_page *sp;
2654         LIST_HEAD(invalid_list);
2655
2656         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2657                 return;
2658         spin_lock(&vcpu->kvm->mmu_lock);
2659         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2660             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2661              vcpu->arch.mmu.direct_map)) {
2662                 hpa_t root = vcpu->arch.mmu.root_hpa;
2663
2664                 sp = page_header(root);
2665                 --sp->root_count;
2666                 if (!sp->root_count && sp->role.invalid) {
2667                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2668                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2669                 }
2670                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2671                 spin_unlock(&vcpu->kvm->mmu_lock);
2672                 return;
2673         }
2674         for (i = 0; i < 4; ++i) {
2675                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2676
2677                 if (root) {
2678                         root &= PT64_BASE_ADDR_MASK;
2679                         sp = page_header(root);
2680                         --sp->root_count;
2681                         if (!sp->root_count && sp->role.invalid)
2682                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2683                                                          &invalid_list);
2684                 }
2685                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2686         }
2687         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2688         spin_unlock(&vcpu->kvm->mmu_lock);
2689         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2690 }
2691
2692 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2693 {
2694         int ret = 0;
2695
2696         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2697                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2698                 ret = 1;
2699         }
2700
2701         return ret;
2702 }
2703
2704 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2705 {
2706         struct kvm_mmu_page *sp;
2707         unsigned i;
2708
2709         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2710                 spin_lock(&vcpu->kvm->mmu_lock);
2711                 kvm_mmu_free_some_pages(vcpu);
2712                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2713                                       1, ACC_ALL, NULL);
2714                 ++sp->root_count;
2715                 spin_unlock(&vcpu->kvm->mmu_lock);
2716                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2717         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2718                 for (i = 0; i < 4; ++i) {
2719                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2720
2721                         ASSERT(!VALID_PAGE(root));
2722                         spin_lock(&vcpu->kvm->mmu_lock);
2723                         kvm_mmu_free_some_pages(vcpu);
2724                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2725                                               i << 30,
2726                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2727                                               NULL);
2728                         root = __pa(sp->spt);
2729                         ++sp->root_count;
2730                         spin_unlock(&vcpu->kvm->mmu_lock);
2731                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2732                 }
2733                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2734         } else
2735                 BUG();
2736
2737         return 0;
2738 }
2739
2740 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2741 {
2742         struct kvm_mmu_page *sp;
2743         u64 pdptr, pm_mask;
2744         gfn_t root_gfn;
2745         int i;
2746
2747         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2748
2749         if (mmu_check_root(vcpu, root_gfn))
2750                 return 1;
2751
2752         /*
2753          * Do we shadow a long mode page table? If so we need to
2754          * write-protect the guests page table root.
2755          */
2756         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2757                 hpa_t root = vcpu->arch.mmu.root_hpa;
2758
2759                 ASSERT(!VALID_PAGE(root));
2760
2761                 spin_lock(&vcpu->kvm->mmu_lock);
2762                 kvm_mmu_free_some_pages(vcpu);
2763                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2764                                       0, ACC_ALL, NULL);
2765                 root = __pa(sp->spt);
2766                 ++sp->root_count;
2767                 spin_unlock(&vcpu->kvm->mmu_lock);
2768                 vcpu->arch.mmu.root_hpa = root;
2769                 return 0;
2770         }
2771
2772         /*
2773          * We shadow a 32 bit page table. This may be a legacy 2-level
2774          * or a PAE 3-level page table. In either case we need to be aware that
2775          * the shadow page table may be a PAE or a long mode page table.
2776          */
2777         pm_mask = PT_PRESENT_MASK;
2778         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2779                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2780
2781         for (i = 0; i < 4; ++i) {
2782                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2783
2784                 ASSERT(!VALID_PAGE(root));
2785                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2786                         pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
2787                         if (!is_present_gpte(pdptr)) {
2788                                 vcpu->arch.mmu.pae_root[i] = 0;
2789                                 continue;
2790                         }
2791                         root_gfn = pdptr >> PAGE_SHIFT;
2792                         if (mmu_check_root(vcpu, root_gfn))
2793                                 return 1;
2794                 }
2795                 spin_lock(&vcpu->kvm->mmu_lock);
2796                 kvm_mmu_free_some_pages(vcpu);
2797                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2798                                       PT32_ROOT_LEVEL, 0,
2799                                       ACC_ALL, NULL);
2800                 root = __pa(sp->spt);
2801                 ++sp->root_count;
2802                 spin_unlock(&vcpu->kvm->mmu_lock);
2803
2804                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2805         }
2806         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2807
2808         /*
2809          * If we shadow a 32 bit page table with a long mode page
2810          * table we enter this path.
2811          */
2812         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2813                 if (vcpu->arch.mmu.lm_root == NULL) {
2814                         /*
2815                          * The additional page necessary for this is only
2816                          * allocated on demand.
2817                          */
2818
2819                         u64 *lm_root;
2820
2821                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2822                         if (lm_root == NULL)
2823                                 return 1;
2824
2825                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2826
2827                         vcpu->arch.mmu.lm_root = lm_root;
2828                 }
2829
2830                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2831         }
2832
2833         return 0;
2834 }
2835
2836 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2837 {
2838         if (vcpu->arch.mmu.direct_map)
2839                 return mmu_alloc_direct_roots(vcpu);
2840         else
2841                 return mmu_alloc_shadow_roots(vcpu);
2842 }
2843
2844 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2845 {
2846         int i;
2847         struct kvm_mmu_page *sp;
2848
2849         if (vcpu->arch.mmu.direct_map)
2850                 return;
2851
2852         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2853                 return;
2854
2855         vcpu_clear_mmio_info(vcpu, ~0ul);
2856         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2857         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2858                 hpa_t root = vcpu->arch.mmu.root_hpa;
2859                 sp = page_header(root);
2860                 mmu_sync_children(vcpu, sp);
2861                 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2862                 return;
2863         }
2864         for (i = 0; i < 4; ++i) {
2865                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2866
2867                 if (root && VALID_PAGE(root)) {
2868                         root &= PT64_BASE_ADDR_MASK;
2869                         sp = page_header(root);
2870                         mmu_sync_children(vcpu, sp);
2871                 }
2872         }
2873         trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2874 }
2875
2876 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2877 {
2878         spin_lock(&vcpu->kvm->mmu_lock);
2879         mmu_sync_roots(vcpu);
2880         spin_unlock(&vcpu->kvm->mmu_lock);
2881 }
2882
2883 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2884                                   u32 access, struct x86_exception *exception)
2885 {
2886         if (exception)
2887                 exception->error_code = 0;
2888         return vaddr;
2889 }
2890
2891 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2892                                          u32 access,
2893                                          struct x86_exception *exception)
2894 {
2895         if (exception)
2896                 exception->error_code = 0;
2897         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2898 }
2899
2900 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2901 {
2902         if (direct)
2903                 return vcpu_match_mmio_gpa(vcpu, addr);
2904
2905         return vcpu_match_mmio_gva(vcpu, addr);
2906 }
2907
2908
2909 /*
2910  * On direct hosts, the last spte is only allows two states
2911  * for mmio page fault:
2912  *   - It is the mmio spte
2913  *   - It is zapped or it is being zapped.
2914  *
2915  * This function completely checks the spte when the last spte
2916  * is not the mmio spte.
2917  */
2918 static bool check_direct_spte_mmio_pf(u64 spte)
2919 {
2920         return __check_direct_spte_mmio_pf(spte);
2921 }
2922
2923 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2924 {
2925         struct kvm_shadow_walk_iterator iterator;
2926         u64 spte = 0ull;
2927
2928         walk_shadow_page_lockless_begin(vcpu);
2929         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2930                 if (!is_shadow_present_pte(spte))
2931                         break;
2932         walk_shadow_page_lockless_end(vcpu);
2933
2934         return spte;
2935 }
2936
2937 /*
2938  * If it is a real mmio page fault, return 1 and emulat the instruction
2939  * directly, return 0 to let CPU fault again on the address, -1 is
2940  * returned if bug is detected.
2941  */
2942 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2943 {
2944         u64 spte;
2945
2946         if (quickly_check_mmio_pf(vcpu, addr, direct))
2947                 return 1;
2948
2949         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2950
2951         if (is_mmio_spte(spte)) {
2952                 gfn_t gfn = get_mmio_spte_gfn(spte);
2953                 unsigned access = get_mmio_spte_access(spte);
2954
2955                 if (direct)
2956                         addr = 0;
2957
2958                 trace_handle_mmio_page_fault(addr, gfn, access);
2959                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2960                 return 1;
2961         }
2962
2963         /*
2964          * It's ok if the gva is remapped by other cpus on shadow guest,
2965          * it's a BUG if the gfn is not a mmio page.
2966          */
2967         if (direct && !check_direct_spte_mmio_pf(spte))
2968                 return -1;
2969
2970         /*
2971          * If the page table is zapped by other cpus, let CPU fault again on
2972          * the address.
2973          */
2974         return 0;
2975 }
2976 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2977
2978 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2979                                   u32 error_code, bool direct)
2980 {
2981         int ret;
2982
2983         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2984         WARN_ON(ret < 0);
2985         return ret;
2986 }
2987
2988 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2989                                 u32 error_code, bool prefault)
2990 {
2991         gfn_t gfn;
2992         int r;
2993
2994         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2995
2996         if (unlikely(error_code & PFERR_RSVD_MASK))
2997                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2998
2999         r = mmu_topup_memory_caches(vcpu);
3000         if (r)
3001                 return r;
3002
3003         ASSERT(vcpu);
3004         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3005
3006         gfn = gva >> PAGE_SHIFT;
3007
3008         return nonpaging_map(vcpu, gva & PAGE_MASK,
3009                              error_code & PFERR_WRITE_MASK, gfn, prefault);
3010 }
3011
3012 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3013 {
3014         struct kvm_arch_async_pf arch;
3015
3016         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3017         arch.gfn = gfn;
3018         arch.direct_map = vcpu->arch.mmu.direct_map;
3019         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3020
3021         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3022 }
3023
3024 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3025 {
3026         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3027                      kvm_event_needs_reinjection(vcpu)))
3028                 return false;
3029
3030         return kvm_x86_ops->interrupt_allowed(vcpu);
3031 }
3032
3033 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3034                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3035 {
3036         bool async;
3037
3038         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3039
3040         if (!async)
3041                 return false; /* *pfn has correct page already */
3042
3043         put_page(pfn_to_page(*pfn));
3044
3045         if (!prefault && can_do_async_pf(vcpu)) {
3046                 trace_kvm_try_async_get_page(gva, gfn);
3047                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3048                         trace_kvm_async_pf_doublefault(gva, gfn);
3049                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3050                         return true;
3051                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3052                         return true;
3053         }
3054
3055         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3056
3057         return false;
3058 }
3059
3060 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3061                           bool prefault)
3062 {
3063         pfn_t pfn;
3064         int r;
3065         int level;
3066         int force_pt_level;
3067         gfn_t gfn = gpa >> PAGE_SHIFT;
3068         unsigned long mmu_seq;
3069         int write = error_code & PFERR_WRITE_MASK;
3070         bool map_writable;
3071
3072         ASSERT(vcpu);
3073         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3074
3075         if (unlikely(error_code & PFERR_RSVD_MASK))
3076                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3077
3078         r = mmu_topup_memory_caches(vcpu);
3079         if (r)
3080                 return r;
3081
3082         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3083         if (likely(!force_pt_level)) {
3084                 level = mapping_level(vcpu, gfn);
3085                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3086         } else
3087                 level = PT_PAGE_TABLE_LEVEL;
3088
3089         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3090         smp_rmb();
3091
3092         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3093                 return 0;
3094
3095         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3096                 return r;
3097
3098         spin_lock(&vcpu->kvm->mmu_lock);
3099         if (mmu_notifier_retry(vcpu, mmu_seq))
3100                 goto out_unlock;
3101         kvm_mmu_free_some_pages(vcpu);
3102         if (likely(!force_pt_level))
3103                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3104         r = __direct_map(vcpu, gpa, write, map_writable,
3105                          level, gfn, pfn, prefault);
3106         spin_unlock(&vcpu->kvm->mmu_lock);
3107
3108         return r;
3109
3110 out_unlock:
3111         spin_unlock(&vcpu->kvm->mmu_lock);
3112         kvm_release_pfn_clean(pfn);
3113         return 0;
3114 }
3115
3116 static void nonpaging_free(struct kvm_vcpu *vcpu)
3117 {
3118         mmu_free_roots(vcpu);
3119 }
3120
3121 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3122                                   struct kvm_mmu *context)
3123 {
3124         context->new_cr3 = nonpaging_new_cr3;
3125         context->page_fault = nonpaging_page_fault;
3126         context->gva_to_gpa = nonpaging_gva_to_gpa;
3127         context->free = nonpaging_free;
3128         context->sync_page = nonpaging_sync_page;
3129         context->invlpg = nonpaging_invlpg;
3130         context->update_pte = nonpaging_update_pte;
3131         context->root_level = 0;
3132         context->shadow_root_level = PT32E_ROOT_LEVEL;
3133         context->root_hpa = INVALID_PAGE;
3134         context->direct_map = true;
3135         context->nx = false;
3136         return 0;
3137 }
3138
3139 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3140 {
3141         ++vcpu->stat.tlb_flush;
3142         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3143 }
3144
3145 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3146 {
3147         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3148         mmu_free_roots(vcpu);
3149 }
3150
3151 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3152 {
3153         return kvm_read_cr3(vcpu);
3154 }
3155
3156 static void inject_page_fault(struct kvm_vcpu *vcpu,
3157                               struct x86_exception *fault)
3158 {
3159         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3160 }
3161
3162 static void paging_free(struct kvm_vcpu *vcpu)
3163 {
3164         nonpaging_free(vcpu);
3165 }
3166
3167 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3168 {
3169         int bit7;
3170
3171         bit7 = (gpte >> 7) & 1;
3172         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3173 }
3174
3175 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3176                            int *nr_present)
3177 {
3178         if (unlikely(is_mmio_spte(*sptep))) {
3179                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3180                         mmu_spte_clear_no_track(sptep);
3181                         return true;
3182                 }
3183
3184                 (*nr_present)++;
3185                 mark_mmio_spte(sptep, gfn, access);
3186                 return true;
3187         }
3188
3189         return false;
3190 }
3191
3192 #define PTTYPE 64
3193 #include "paging_tmpl.h"
3194 #undef PTTYPE
3195
3196 #define PTTYPE 32
3197 #include "paging_tmpl.h"
3198 #undef PTTYPE
3199
3200 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3201                                   struct kvm_mmu *context,
3202                                   int level)
3203 {
3204         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3205         u64 exb_bit_rsvd = 0;
3206
3207         if (!context->nx)
3208                 exb_bit_rsvd = rsvd_bits(63, 63);
3209         switch (level) {
3210         case PT32_ROOT_LEVEL:
3211                 /* no rsvd bits for 2 level 4K page table entries */
3212                 context->rsvd_bits_mask[0][1] = 0;
3213                 context->rsvd_bits_mask[0][0] = 0;
3214                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3215
3216                 if (!is_pse(vcpu)) {
3217                         context->rsvd_bits_mask[1][1] = 0;
3218                         break;
3219                 }
3220
3221                 if (is_cpuid_PSE36())
3222                         /* 36bits PSE 4MB page */
3223                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3224                 else
3225                         /* 32 bits PSE 4MB page */
3226                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3227                 break;
3228         case PT32E_ROOT_LEVEL:
3229                 context->rsvd_bits_mask[0][2] =
3230                         rsvd_bits(maxphyaddr, 63) |
3231                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3232                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3233                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3234                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3235                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3236                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3237                         rsvd_bits(maxphyaddr, 62) |
3238                         rsvd_bits(13, 20);              /* large page */
3239                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3240                 break;
3241         case PT64_ROOT_LEVEL:
3242                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3243                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3244                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3245                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3246                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3247                         rsvd_bits(maxphyaddr, 51);
3248                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3249                         rsvd_bits(maxphyaddr, 51);
3250                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3251                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3252                         rsvd_bits(maxphyaddr, 51) |
3253                         rsvd_bits(13, 29);
3254                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3255                         rsvd_bits(maxphyaddr, 51) |
3256                         rsvd_bits(13, 20);              /* large page */
3257                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3258                 break;
3259         }
3260 }
3261
3262 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3263                                         struct kvm_mmu *context,
3264                                         int level)
3265 {
3266         context->nx = is_nx(vcpu);
3267
3268         reset_rsvds_bits_mask(vcpu, context, level);
3269
3270         ASSERT(is_pae(vcpu));
3271         context->new_cr3 = paging_new_cr3;
3272         context->page_fault = paging64_page_fault;
3273         context->gva_to_gpa = paging64_gva_to_gpa;
3274         context->sync_page = paging64_sync_page;
3275         context->invlpg = paging64_invlpg;
3276         context->update_pte = paging64_update_pte;
3277         context->free = paging_free;
3278         context->root_level = level;
3279         context->shadow_root_level = level;
3280         context->root_hpa = INVALID_PAGE;
3281         context->direct_map = false;
3282         return 0;
3283 }
3284
3285 static int paging64_init_context(struct kvm_vcpu *vcpu,
3286                                  struct kvm_mmu *context)
3287 {
3288         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3289 }
3290
3291 static int paging32_init_context(struct kvm_vcpu *vcpu,
3292                                  struct kvm_mmu *context)
3293 {
3294         context->nx = false;
3295
3296         reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3297
3298         context->new_cr3 = paging_new_cr3;
3299         context->page_fault = paging32_page_fault;
3300         context->gva_to_gpa = paging32_gva_to_gpa;
3301         context->free = paging_free;
3302         context->sync_page = paging32_sync_page;
3303         context->invlpg = paging32_invlpg;
3304         context->update_pte = paging32_update_pte;
3305         context->root_level = PT32_ROOT_LEVEL;
3306         context->shadow_root_level = PT32E_ROOT_LEVEL;
3307         context->root_hpa = INVALID_PAGE;
3308         context->direct_map = false;
3309         return 0;
3310 }
3311
3312 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3313                                   struct kvm_mmu *context)
3314 {
3315         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3316 }
3317
3318 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3319 {
3320         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3321
3322         context->base_role.word = 0;
3323         context->new_cr3 = nonpaging_new_cr3;
3324         context->page_fault = tdp_page_fault;
3325         context->free = nonpaging_free;
3326         context->sync_page = nonpaging_sync_page;
3327         context->invlpg = nonpaging_invlpg;
3328         context->update_pte = nonpaging_update_pte;
3329         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3330         context->root_hpa = INVALID_PAGE;
3331         context->direct_map = true;
3332         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3333         context->get_cr3 = get_cr3;
3334         context->get_pdptr = kvm_pdptr_read;
3335         context->inject_page_fault = kvm_inject_page_fault;
3336         context->nx = is_nx(vcpu);
3337
3338         if (!is_paging(vcpu)) {
3339                 context->nx = false;
3340                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3341                 context->root_level = 0;
3342         } else if (is_long_mode(vcpu)) {
3343                 context->nx = is_nx(vcpu);
3344                 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3345                 context->gva_to_gpa = paging64_gva_to_gpa;
3346                 context->root_level = PT64_ROOT_LEVEL;
3347         } else if (is_pae(vcpu)) {
3348                 context->nx = is_nx(vcpu);
3349                 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3350                 context->gva_to_gpa = paging64_gva_to_gpa;
3351                 context->root_level = PT32E_ROOT_LEVEL;
3352         } else {
3353                 context->nx = false;
3354                 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3355                 context->gva_to_gpa = paging32_gva_to_gpa;
3356                 context->root_level = PT32_ROOT_LEVEL;
3357         }
3358
3359         return 0;
3360 }
3361
3362 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3363 {
3364         int r;
3365         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3366         ASSERT(vcpu);
3367         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3368
3369         if (!is_paging(vcpu))
3370                 r = nonpaging_init_context(vcpu, context);
3371         else if (is_long_mode(vcpu))
3372                 r = paging64_init_context(vcpu, context);
3373         else if (is_pae(vcpu))
3374                 r = paging32E_init_context(vcpu, context);
3375         else
3376                 r = paging32_init_context(vcpu, context);
3377
3378         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3379         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3380         vcpu->arch.mmu.base_role.smep_andnot_wp
3381                 = smep && !is_write_protection(vcpu);
3382
3383         return r;
3384 }
3385 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3386
3387 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3388 {
3389         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3390
3391         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3392         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3393         vcpu->arch.walk_mmu->get_pdptr         = kvm_pdptr_read;
3394         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3395
3396         return r;
3397 }
3398
3399 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3400 {
3401         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3402
3403         g_context->get_cr3           = get_cr3;
3404         g_context->get_pdptr         = kvm_pdptr_read;
3405         g_context->inject_page_fault = kvm_inject_page_fault;
3406
3407         /*
3408          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3409          * translation of l2_gpa to l1_gpa addresses is done using the
3410          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3411          * functions between mmu and nested_mmu are swapped.
3412          */
3413         if (!is_paging(vcpu)) {
3414                 g_context->nx = false;
3415                 g_context->root_level = 0;
3416                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3417         } else if (is_long_mode(vcpu)) {
3418                 g_context->nx = is_nx(vcpu);
3419                 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3420                 g_context->root_level = PT64_ROOT_LEVEL;
3421                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3422         } else if (is_pae(vcpu)) {
3423                 g_context->nx = is_nx(vcpu);
3424                 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3425                 g_context->root_level = PT32E_ROOT_LEVEL;
3426                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3427         } else {
3428                 g_context->nx = false;
3429                 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3430                 g_context->root_level = PT32_ROOT_LEVEL;
3431                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3432         }
3433
3434         return 0;
3435 }
3436
3437 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3438 {
3439         if (mmu_is_nested(vcpu))
3440                 return init_kvm_nested_mmu(vcpu);
3441         else if (tdp_enabled)
3442                 return init_kvm_tdp_mmu(vcpu);
3443         else
3444                 return init_kvm_softmmu(vcpu);
3445 }
3446
3447 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3448 {
3449         ASSERT(vcpu);
3450         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3451                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3452                 vcpu->arch.mmu.free(vcpu);
3453 }
3454
3455 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3456 {
3457         destroy_kvm_mmu(vcpu);
3458         return init_kvm_mmu(vcpu);
3459 }
3460 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3461
3462 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3463 {
3464         int r;
3465
3466         r = mmu_topup_memory_caches(vcpu);
3467         if (r)
3468                 goto out;
3469         r = mmu_alloc_roots(vcpu);
3470         spin_lock(&vcpu->kvm->mmu_lock);
3471         mmu_sync_roots(vcpu);
3472         spin_unlock(&vcpu->kvm->mmu_lock);
3473         if (r)
3474                 goto out;
3475         /* set_cr3() should ensure TLB has been flushed */
3476         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3477 out:
3478         return r;
3479 }
3480 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3481
3482 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3483 {
3484         mmu_free_roots(vcpu);
3485 }
3486 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3487
3488 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3489                                   struct kvm_mmu_page *sp, u64 *spte,
3490                                   const void *new)
3491 {
3492         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3493                 ++vcpu->kvm->stat.mmu_pde_zapped;
3494                 return;
3495         }
3496
3497         ++vcpu->kvm->stat.mmu_pte_updated;
3498         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3499 }
3500
3501 static bool need_remote_flush(u64 old, u64 new)
3502 {
3503         if (!is_shadow_present_pte(old))
3504                 return false;
3505         if (!is_shadow_present_pte(new))
3506                 return true;
3507         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3508                 return true;
3509         old ^= PT64_NX_MASK;
3510         new ^= PT64_NX_MASK;
3511         return (old & ~new & PT64_PERM_MASK) != 0;
3512 }
3513
3514 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3515                                     bool remote_flush, bool local_flush)
3516 {
3517         if (zap_page)
3518                 return;
3519
3520         if (remote_flush)
3521                 kvm_flush_remote_tlbs(vcpu->kvm);
3522         else if (local_flush)
3523                 kvm_mmu_flush_tlb(vcpu);
3524 }
3525
3526 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3527 {
3528         u64 *spte = vcpu->arch.last_pte_updated;
3529
3530         return !!(spte && (*spte & shadow_accessed_mask));
3531 }
3532
3533 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3534                                     const u8 *new, int *bytes)
3535 {
3536         u64 gentry;
3537         int r;
3538
3539         /*
3540          * Assume that the pte write on a page table of the same type
3541          * as the current vcpu paging mode since we update the sptes only
3542          * when they have the same mode.
3543          */
3544         if (is_pae(vcpu) && *bytes == 4) {
3545                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3546                 *gpa &= ~(gpa_t)7;
3547                 *bytes = 8;
3548                 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, min(*bytes, 8));
3549                 if (r)
3550                         gentry = 0;
3551                 new = (const u8 *)&gentry;
3552         }
3553
3554         switch (*bytes) {
3555         case 4:
3556                 gentry = *(const u32 *)new;
3557                 break;
3558         case 8:
3559                 gentry = *(const u64 *)new;
3560                 break;
3561         default:
3562                 gentry = 0;
3563                 break;
3564         }
3565
3566         return gentry;
3567 }
3568
3569 /*
3570  * If we're seeing too many writes to a page, it may no longer be a page table,
3571  * or we may be forking, in which case it is better to unmap the page.
3572  */
3573 static bool detect_write_flooding(struct kvm_vcpu *vcpu, gfn_t gfn)
3574 {
3575         bool flooded = false;
3576
3577         if (gfn == vcpu->arch.last_pt_write_gfn
3578             && !last_updated_pte_accessed(vcpu)) {
3579                 ++vcpu->arch.last_pt_write_count;
3580                 if (vcpu->arch.last_pt_write_count >= 3)
3581                         flooded = true;
3582         } else {
3583                 vcpu->arch.last_pt_write_gfn = gfn;
3584                 vcpu->arch.last_pt_write_count = 1;
3585                 vcpu->arch.last_pte_updated = NULL;
3586         }
3587
3588         return flooded;
3589 }
3590
3591 /*
3592  * Misaligned accesses are too much trouble to fix up; also, they usually
3593  * indicate a page is not used as a page table.
3594  */
3595 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
3596                                     int bytes)
3597 {
3598         unsigned offset, pte_size, misaligned;
3599
3600         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3601                  gpa, bytes, sp->role.word);
3602
3603         offset = offset_in_page(gpa);
3604         pte_size = sp->role.cr4_pae ? 8 : 4;
3605         misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3606         misaligned |= bytes < 4;
3607
3608         return misaligned;
3609 }
3610
3611 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
3612 {
3613         unsigned page_offset, quadrant;
3614         u64 *spte;
3615         int level;
3616
3617         page_offset = offset_in_page(gpa);
3618         level = sp->role.level;
3619         *nspte = 1;
3620         if (!sp->role.cr4_pae) {
3621                 page_offset <<= 1;      /* 32->64 */
3622                 /*
3623                  * A 32-bit pde maps 4MB while the shadow pdes map
3624                  * only 2MB.  So we need to double the offset again
3625                  * and zap two pdes instead of one.
3626                  */
3627                 if (level == PT32_ROOT_LEVEL) {
3628                         page_offset &= ~7; /* kill rounding error */
3629                         page_offset <<= 1;
3630                         *nspte = 2;
3631                 }
3632                 quadrant = page_offset >> PAGE_SHIFT;
3633                 page_offset &= ~PAGE_MASK;
3634                 if (quadrant != sp->role.quadrant)
3635                         return NULL;
3636         }
3637
3638         spte = &sp->spt[page_offset / sizeof(*spte)];
3639         return spte;
3640 }
3641
3642 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3643                        const u8 *new, int bytes)
3644 {
3645         gfn_t gfn = gpa >> PAGE_SHIFT;
3646         union kvm_mmu_page_role mask = { .word = 0 };
3647         struct kvm_mmu_page *sp;
3648         struct hlist_node *node;
3649         LIST_HEAD(invalid_list);
3650         u64 entry, gentry, *spte;
3651         int npte;
3652         bool remote_flush, local_flush, zap_page, flooded, misaligned;
3653
3654         /*
3655          * If we don't have indirect shadow pages, it means no page is
3656          * write-protected, so we can exit simply.
3657          */
3658         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3659                 return;
3660
3661         zap_page = remote_flush = local_flush = false;
3662
3663         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3664
3665         gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
3666
3667         /*
3668          * No need to care whether allocation memory is successful
3669          * or not since pte prefetch is skiped if it does not have
3670          * enough objects in the cache.
3671          */
3672         mmu_topup_memory_caches(vcpu);
3673
3674         spin_lock(&vcpu->kvm->mmu_lock);
3675         ++vcpu->kvm->stat.mmu_pte_write;
3676         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3677
3678         flooded = detect_write_flooding(vcpu, gfn);
3679         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3680         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3681                 misaligned = detect_write_misaligned(sp, gpa, bytes);
3682
3683                 if (misaligned || flooded) {
3684                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3685                                                      &invalid_list);
3686                         ++vcpu->kvm->stat.mmu_flooded;
3687                         continue;
3688                 }
3689
3690                 spte = get_written_sptes(sp, gpa, &npte);
3691                 if (!spte)
3692                         continue;
3693
3694                 local_flush = true;
3695                 while (npte--) {
3696                         entry = *spte;
3697                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3698                         if (gentry &&
3699                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3700                               & mask.word) && rmap_can_add(vcpu))
3701                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3702                         if (!remote_flush && need_remote_flush(entry, *spte))
3703                                 remote_flush = true;
3704                         ++spte;
3705                 }
3706         }
3707         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3708         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3709         trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3710         spin_unlock(&vcpu->kvm->mmu_lock);
3711 }
3712
3713 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3714 {
3715         gpa_t gpa;
3716         int r;
3717
3718         if (vcpu->arch.mmu.direct_map)
3719                 return 0;
3720
3721         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3722
3723         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3724
3725         return r;
3726 }
3727 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3728
3729 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3730 {
3731         LIST_HEAD(invalid_list);
3732
3733         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3734                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3735                 struct kvm_mmu_page *sp;
3736
3737                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3738                                   struct kvm_mmu_page, link);
3739                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3740                 ++vcpu->kvm->stat.mmu_recycled;
3741         }
3742         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3743 }
3744
3745 static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
3746 {
3747         if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
3748                 return vcpu_match_mmio_gpa(vcpu, addr);
3749
3750         return vcpu_match_mmio_gva(vcpu, addr);
3751 }
3752
3753 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3754                        void *insn, int insn_len)
3755 {
3756         int r, emulation_type = EMULTYPE_RETRY;
3757         enum emulation_result er;
3758
3759         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3760         if (r < 0)
3761                 goto out;
3762
3763         if (!r) {
3764                 r = 1;
3765                 goto out;
3766         }
3767
3768         if (is_mmio_page_fault(vcpu, cr2))
3769                 emulation_type = 0;
3770
3771         er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
3772
3773         switch (er) {
3774         case EMULATE_DONE:
3775                 return 1;
3776         case EMULATE_DO_MMIO:
3777                 ++vcpu->stat.mmio_exits;
3778                 /* fall through */
3779         case EMULATE_FAIL:
3780                 return 0;
3781         default:
3782                 BUG();
3783         }
3784 out:
3785         return r;
3786 }
3787 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3788
3789 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3790 {
3791         vcpu->arch.mmu.invlpg(vcpu, gva);
3792         kvm_mmu_flush_tlb(vcpu);
3793         ++vcpu->stat.invlpg;
3794 }
3795 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3796
3797 void kvm_enable_tdp(void)
3798 {
3799         tdp_enabled = true;
3800 }
3801 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3802
3803 void kvm_disable_tdp(void)
3804 {
3805         tdp_enabled = false;
3806 }
3807 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3808
3809 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3810 {
3811         free_page((unsigned long)vcpu->arch.mmu.pae_root);
3812         if (vcpu->arch.mmu.lm_root != NULL)
3813                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3814 }
3815
3816 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3817 {
3818         struct page *page;
3819         int i;
3820
3821         ASSERT(vcpu);
3822
3823         /*
3824          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3825          * Therefore we need to allocate shadow page tables in the first
3826          * 4GB of memory, which happens to fit the DMA32 zone.
3827          */
3828         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3829         if (!page)
3830                 return -ENOMEM;
3831
3832         vcpu->arch.mmu.pae_root = page_address(page);
3833         for (i = 0; i < 4; ++i)
3834                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3835
3836         return 0;
3837 }
3838
3839 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3840 {
3841         ASSERT(vcpu);
3842         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3843
3844         return alloc_mmu_pages(vcpu);
3845 }
3846
3847 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3848 {
3849         ASSERT(vcpu);
3850         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3851
3852         return init_kvm_mmu(vcpu);
3853 }
3854
3855 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3856 {
3857         struct kvm_mmu_page *sp;
3858
3859         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3860                 int i;
3861                 u64 *pt;
3862
3863                 if (!test_bit(slot, sp->slot_bitmap))
3864                         continue;
3865
3866                 pt = sp->spt;
3867                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3868                         if (!is_shadow_present_pte(pt[i]) ||
3869                               !is_last_spte(pt[i], sp->role.level))
3870                                 continue;
3871
3872                         if (is_large_pte(pt[i])) {
3873                                 drop_spte(kvm, &pt[i]);
3874                                 --kvm->stat.lpages;
3875                                 continue;
3876                         }
3877
3878                         /* avoid RMW */
3879                         if (is_writable_pte(pt[i]))
3880                                 mmu_spte_update(&pt[i],
3881                                                 pt[i] & ~PT_WRITABLE_MASK);
3882                 }
3883         }
3884         kvm_flush_remote_tlbs(kvm);
3885 }
3886
3887 void kvm_mmu_zap_all(struct kvm *kvm)
3888 {
3889         struct kvm_mmu_page *sp, *node;
3890         LIST_HEAD(invalid_list);
3891
3892         spin_lock(&kvm->mmu_lock);
3893 restart:
3894         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3895                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3896                         goto restart;
3897
3898         kvm_mmu_commit_zap_page(kvm, &invalid_list);
3899         spin_unlock(&kvm->mmu_lock);
3900 }
3901
3902 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3903                                                struct list_head *invalid_list)
3904 {
3905         struct kvm_mmu_page *page;
3906
3907         page = container_of(kvm->arch.active_mmu_pages.prev,
3908                             struct kvm_mmu_page, link);
3909         return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3910 }
3911
3912 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3913 {
3914         struct kvm *kvm;
3915         struct kvm *kvm_freed = NULL;
3916         int nr_to_scan = sc->nr_to_scan;
3917
3918         if (nr_to_scan == 0)
3919                 goto out;
3920
3921         raw_spin_lock(&kvm_lock);
3922
3923         list_for_each_entry(kvm, &vm_list, vm_list) {
3924                 int idx, freed_pages;
3925                 LIST_HEAD(invalid_list);
3926
3927                 idx = srcu_read_lock(&kvm->srcu);
3928                 spin_lock(&kvm->mmu_lock);
3929                 if (!kvm_freed && nr_to_scan > 0 &&
3930                     kvm->arch.n_used_mmu_pages > 0) {
3931                         freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3932                                                           &invalid_list);
3933                         kvm_freed = kvm;
3934                 }
3935                 nr_to_scan--;
3936
3937                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3938                 spin_unlock(&kvm->mmu_lock);
3939                 srcu_read_unlock(&kvm->srcu, idx);
3940         }
3941         if (kvm_freed)
3942                 list_move_tail(&kvm_freed->vm_list, &vm_list);
3943
3944         raw_spin_unlock(&kvm_lock);
3945
3946 out:
3947         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3948 }
3949
3950 static struct shrinker mmu_shrinker = {
3951         .shrink = mmu_shrink,
3952         .seeks = DEFAULT_SEEKS * 10,
3953 };
3954
3955 static void mmu_destroy_caches(void)
3956 {
3957         if (pte_list_desc_cache)
3958                 kmem_cache_destroy(pte_list_desc_cache);
3959         if (mmu_page_header_cache)
3960                 kmem_cache_destroy(mmu_page_header_cache);
3961 }
3962
3963 int kvm_mmu_module_init(void)
3964 {
3965         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3966                                             sizeof(struct pte_list_desc),
3967                                             0, 0, NULL);
3968         if (!pte_list_desc_cache)
3969                 goto nomem;
3970
3971         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3972                                                   sizeof(struct kvm_mmu_page),
3973                                                   0, 0, NULL);
3974         if (!mmu_page_header_cache)
3975                 goto nomem;
3976
3977         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3978                 goto nomem;
3979
3980         register_shrinker(&mmu_shrinker);
3981
3982         return 0;
3983
3984 nomem:
3985         mmu_destroy_caches();
3986         return -ENOMEM;
3987 }
3988
3989 /*
3990  * Caculate mmu pages needed for kvm.
3991  */
3992 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3993 {
3994         int i;
3995         unsigned int nr_mmu_pages;
3996         unsigned int  nr_pages = 0;
3997         struct kvm_memslots *slots;
3998
3999         slots = kvm_memslots(kvm);
4000
4001         for (i = 0; i < slots->nmemslots; i++)
4002                 nr_pages += slots->memslots[i].npages;
4003
4004         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4005         nr_mmu_pages = max(nr_mmu_pages,
4006                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4007
4008         return nr_mmu_pages;
4009 }
4010
4011 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
4012                                 unsigned len)
4013 {
4014         if (len > buffer->len)
4015                 return NULL;
4016         return buffer->ptr;
4017 }
4018
4019 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
4020                                 unsigned len)
4021 {
4022         void *ret;
4023
4024         ret = pv_mmu_peek_buffer(buffer, len);
4025         if (!ret)
4026                 return ret;
4027         buffer->ptr += len;
4028         buffer->len -= len;
4029         buffer->processed += len;
4030         return ret;
4031 }
4032
4033 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
4034                              gpa_t addr, gpa_t value)
4035 {
4036         int bytes = 8;
4037         int r;
4038
4039         if (!is_long_mode(vcpu) && !is_pae(vcpu))
4040                 bytes = 4;
4041
4042         r = mmu_topup_memory_caches(vcpu);
4043         if (r)
4044                 return r;
4045
4046         if (!emulator_write_phys(vcpu, addr, &value, bytes))
4047                 return -EFAULT;
4048
4049         return 1;
4050 }
4051
4052 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
4053 {
4054         (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
4055         return 1;
4056 }
4057
4058 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
4059 {
4060         spin_lock(&vcpu->kvm->mmu_lock);
4061         mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
4062         spin_unlock(&vcpu->kvm->mmu_lock);
4063         return 1;
4064 }
4065
4066 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
4067                              struct kvm_pv_mmu_op_buffer *buffer)
4068 {
4069         struct kvm_mmu_op_header *header;
4070
4071         header = pv_mmu_peek_buffer(buffer, sizeof *header);
4072         if (!header)
4073                 return 0;
4074         switch (header->op) {
4075         case KVM_MMU_OP_WRITE_PTE: {
4076                 struct kvm_mmu_op_write_pte *wpte;
4077
4078                 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
4079                 if (!wpte)
4080                         return 0;
4081                 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
4082                                         wpte->pte_val);
4083         }
4084         case KVM_MMU_OP_FLUSH_TLB: {
4085                 struct kvm_mmu_op_flush_tlb *ftlb;
4086
4087                 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
4088                 if (!ftlb)
4089                         return 0;
4090                 return kvm_pv_mmu_flush_tlb(vcpu);
4091         }
4092         case KVM_MMU_OP_RELEASE_PT: {
4093                 struct kvm_mmu_op_release_pt *rpt;
4094
4095                 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
4096                 if (!rpt)
4097                         return 0;
4098                 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
4099         }
4100         default: return 0;
4101         }
4102 }
4103
4104 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
4105                   gpa_t addr, unsigned long *ret)
4106 {
4107         int r;
4108         struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
4109
4110         buffer->ptr = buffer->buf;
4111         buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
4112         buffer->processed = 0;
4113
4114         r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
4115         if (r)
4116                 goto out;
4117
4118         while (buffer->len) {
4119                 r = kvm_pv_mmu_op_one(vcpu, buffer);
4120                 if (r < 0)
4121                         goto out;
4122                 if (r == 0)
4123                         break;
4124         }
4125
4126         r = 1;
4127 out:
4128         *ret = buffer->processed;
4129         return r;
4130 }
4131
4132 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4133 {
4134         struct kvm_shadow_walk_iterator iterator;
4135         u64 spte;
4136         int nr_sptes = 0;
4137
4138         walk_shadow_page_lockless_begin(vcpu);
4139         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4140                 sptes[iterator.level-1] = spte;
4141                 nr_sptes++;
4142                 if (!is_shadow_present_pte(spte))
4143                         break;
4144         }
4145         walk_shadow_page_lockless_end(vcpu);
4146
4147         return nr_sptes;
4148 }
4149 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4150
4151 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4152 {
4153         ASSERT(vcpu);
4154
4155         destroy_kvm_mmu(vcpu);
4156         free_mmu_pages(vcpu);
4157         mmu_free_memory_caches(vcpu);
4158 }
4159
4160 #ifdef CONFIG_KVM_MMU_AUDIT
4161 #include "mmu_audit.c"
4162 #else
4163 static void mmu_audit_disable(void) { }
4164 #endif
4165
4166 void kvm_mmu_module_exit(void)
4167 {
4168         mmu_destroy_caches();
4169         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4170         unregister_shrinker(&mmu_shrinker);
4171         mmu_audit_disable();
4172 }