2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
27 #include <linux/kvm_host.h>
28 #include <linux/types.h>
29 #include <linux/string.h>
31 #include <linux/highmem.h>
32 #include <linux/module.h>
33 #include <linux/swap.h>
34 #include <linux/hugetlb.h>
35 #include <linux/compiler.h>
36 #include <linux/srcu.h>
37 #include <linux/slab.h>
38 #include <linux/uaccess.h>
41 #include <asm/cmpxchg.h>
44 #include <asm/kvm_page_track.h>
47 * When setting this variable to true it enables Two-Dimensional-Paging
48 * where the hardware walks 2 page tables:
49 * 1. the guest-virtual to guest-physical
50 * 2. while doing 1. it walks guest-physical to host-physical
51 * If the hardware supports that we don't need to do shadow paging.
53 bool tdp_enabled = false;
57 AUDIT_POST_PAGE_FAULT,
68 module_param(dbg, bool, 0644);
70 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
71 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
72 #define MMU_WARN_ON(x) WARN_ON(x)
74 #define pgprintk(x...) do { } while (0)
75 #define rmap_printk(x...) do { } while (0)
76 #define MMU_WARN_ON(x) do { } while (0)
79 #define PTE_PREFETCH_NUM 8
81 #define PT_FIRST_AVAIL_BITS_SHIFT 10
82 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
84 #define PT64_LEVEL_BITS 9
86 #define PT64_LEVEL_SHIFT(level) \
87 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
89 #define PT64_INDEX(address, level)\
90 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
93 #define PT32_LEVEL_BITS 10
95 #define PT32_LEVEL_SHIFT(level) \
96 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
98 #define PT32_LVL_OFFSET_MASK(level) \
99 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
100 * PT32_LEVEL_BITS))) - 1))
102 #define PT32_INDEX(address, level)\
103 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
106 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
107 #define PT64_DIR_BASE_ADDR_MASK \
108 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
109 #define PT64_LVL_ADDR_MASK(level) \
110 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
111 * PT64_LEVEL_BITS))) - 1))
112 #define PT64_LVL_OFFSET_MASK(level) \
113 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
114 * PT64_LEVEL_BITS))) - 1))
116 #define PT32_BASE_ADDR_MASK PAGE_MASK
117 #define PT32_DIR_BASE_ADDR_MASK \
118 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
119 #define PT32_LVL_ADDR_MASK(level) \
120 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
121 * PT32_LEVEL_BITS))) - 1))
123 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
124 | shadow_x_mask | shadow_nx_mask)
126 #define ACC_EXEC_MASK 1
127 #define ACC_WRITE_MASK PT_WRITABLE_MASK
128 #define ACC_USER_MASK PT_USER_MASK
129 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
131 #include <trace/events/kvm.h>
133 #define CREATE_TRACE_POINTS
134 #include "mmutrace.h"
136 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
137 #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
139 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
141 /* make pte_list_desc fit well in cache line */
142 #define PTE_LIST_EXT 3
144 struct pte_list_desc {
145 u64 *sptes[PTE_LIST_EXT];
146 struct pte_list_desc *more;
149 struct kvm_shadow_walk_iterator {
157 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
158 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
159 shadow_walk_okay(&(_walker)); \
160 shadow_walk_next(&(_walker)))
162 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
163 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
164 shadow_walk_okay(&(_walker)) && \
165 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
166 __shadow_walk_next(&(_walker), spte))
168 static struct kmem_cache *pte_list_desc_cache;
169 static struct kmem_cache *mmu_page_header_cache;
170 static struct percpu_counter kvm_total_used_mmu_pages;
172 static u64 __read_mostly shadow_nx_mask;
173 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
174 static u64 __read_mostly shadow_user_mask;
175 static u64 __read_mostly shadow_accessed_mask;
176 static u64 __read_mostly shadow_dirty_mask;
177 static u64 __read_mostly shadow_mmio_mask;
179 static void mmu_spte_set(u64 *sptep, u64 spte);
180 static void mmu_free_roots(struct kvm_vcpu *vcpu);
182 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
184 shadow_mmio_mask = mmio_mask;
186 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
189 * the low bit of the generation number is always presumed to be zero.
190 * This disables mmio caching during memslot updates. The concept is
191 * similar to a seqcount but instead of retrying the access we just punt
192 * and ignore the cache.
194 * spte bits 3-11 are used as bits 1-9 of the generation number,
195 * the bits 52-61 are used as bits 10-19 of the generation number.
197 #define MMIO_SPTE_GEN_LOW_SHIFT 2
198 #define MMIO_SPTE_GEN_HIGH_SHIFT 52
200 #define MMIO_GEN_SHIFT 20
201 #define MMIO_GEN_LOW_SHIFT 10
202 #define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 2)
203 #define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
205 static u64 generation_mmio_spte_mask(unsigned int gen)
209 WARN_ON(gen & ~MMIO_GEN_MASK);
211 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
212 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
216 static unsigned int get_mmio_spte_generation(u64 spte)
220 spte &= ~shadow_mmio_mask;
222 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
223 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
227 static unsigned int kvm_current_mmio_generation(struct kvm_vcpu *vcpu)
229 return kvm_vcpu_memslots(vcpu)->generation & MMIO_GEN_MASK;
232 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
235 unsigned int gen = kvm_current_mmio_generation(vcpu);
236 u64 mask = generation_mmio_spte_mask(gen);
238 access &= ACC_WRITE_MASK | ACC_USER_MASK;
239 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
241 trace_mark_mmio_spte(sptep, gfn, access, gen);
242 mmu_spte_set(sptep, mask);
245 static bool is_mmio_spte(u64 spte)
247 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
250 static gfn_t get_mmio_spte_gfn(u64 spte)
252 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
253 return (spte & ~mask) >> PAGE_SHIFT;
256 static unsigned get_mmio_spte_access(u64 spte)
258 u64 mask = generation_mmio_spte_mask(MMIO_GEN_MASK) | shadow_mmio_mask;
259 return (spte & ~mask) & ~PAGE_MASK;
262 static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
263 kvm_pfn_t pfn, unsigned access)
265 if (unlikely(is_noslot_pfn(pfn))) {
266 mark_mmio_spte(vcpu, sptep, gfn, access);
273 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
275 unsigned int kvm_gen, spte_gen;
277 kvm_gen = kvm_current_mmio_generation(vcpu);
278 spte_gen = get_mmio_spte_generation(spte);
280 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
281 return likely(kvm_gen == spte_gen);
284 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
285 u64 dirty_mask, u64 nx_mask, u64 x_mask)
287 shadow_user_mask = user_mask;
288 shadow_accessed_mask = accessed_mask;
289 shadow_dirty_mask = dirty_mask;
290 shadow_nx_mask = nx_mask;
291 shadow_x_mask = x_mask;
293 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
295 static int is_cpuid_PSE36(void)
300 static int is_nx(struct kvm_vcpu *vcpu)
302 return vcpu->arch.efer & EFER_NX;
305 static int is_shadow_present_pte(u64 pte)
307 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
310 static int is_large_pte(u64 pte)
312 return pte & PT_PAGE_SIZE_MASK;
315 static int is_last_spte(u64 pte, int level)
317 if (level == PT_PAGE_TABLE_LEVEL)
319 if (is_large_pte(pte))
324 static kvm_pfn_t spte_to_pfn(u64 pte)
326 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
329 static gfn_t pse36_gfn_delta(u32 gpte)
331 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
333 return (gpte & PT32_DIR_PSE36_MASK) << shift;
337 static void __set_spte(u64 *sptep, u64 spte)
342 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
347 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
349 return xchg(sptep, spte);
352 static u64 __get_spte_lockless(u64 *sptep)
354 return ACCESS_ONCE(*sptep);
365 static void count_spte_clear(u64 *sptep, u64 spte)
367 struct kvm_mmu_page *sp = page_header(__pa(sptep));
369 if (is_shadow_present_pte(spte))
372 /* Ensure the spte is completely set before we increase the count */
374 sp->clear_spte_count++;
377 static void __set_spte(u64 *sptep, u64 spte)
379 union split_spte *ssptep, sspte;
381 ssptep = (union split_spte *)sptep;
382 sspte = (union split_spte)spte;
384 ssptep->spte_high = sspte.spte_high;
387 * If we map the spte from nonpresent to present, We should store
388 * the high bits firstly, then set present bit, so cpu can not
389 * fetch this spte while we are setting the spte.
393 ssptep->spte_low = sspte.spte_low;
396 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
398 union split_spte *ssptep, sspte;
400 ssptep = (union split_spte *)sptep;
401 sspte = (union split_spte)spte;
403 ssptep->spte_low = sspte.spte_low;
406 * If we map the spte from present to nonpresent, we should clear
407 * present bit firstly to avoid vcpu fetch the old high bits.
411 ssptep->spte_high = sspte.spte_high;
412 count_spte_clear(sptep, spte);
415 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
417 union split_spte *ssptep, sspte, orig;
419 ssptep = (union split_spte *)sptep;
420 sspte = (union split_spte)spte;
422 /* xchg acts as a barrier before the setting of the high bits */
423 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
424 orig.spte_high = ssptep->spte_high;
425 ssptep->spte_high = sspte.spte_high;
426 count_spte_clear(sptep, spte);
432 * The idea using the light way get the spte on x86_32 guest is from
433 * gup_get_pte(arch/x86/mm/gup.c).
435 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
436 * coalesces them and we are running out of the MMU lock. Therefore
437 * we need to protect against in-progress updates of the spte.
439 * Reading the spte while an update is in progress may get the old value
440 * for the high part of the spte. The race is fine for a present->non-present
441 * change (because the high part of the spte is ignored for non-present spte),
442 * but for a present->present change we must reread the spte.
444 * All such changes are done in two steps (present->non-present and
445 * non-present->present), hence it is enough to count the number of
446 * present->non-present updates: if it changed while reading the spte,
447 * we might have hit the race. This is done using clear_spte_count.
449 static u64 __get_spte_lockless(u64 *sptep)
451 struct kvm_mmu_page *sp = page_header(__pa(sptep));
452 union split_spte spte, *orig = (union split_spte *)sptep;
456 count = sp->clear_spte_count;
459 spte.spte_low = orig->spte_low;
462 spte.spte_high = orig->spte_high;
465 if (unlikely(spte.spte_low != orig->spte_low ||
466 count != sp->clear_spte_count))
473 static bool spte_is_locklessly_modifiable(u64 spte)
475 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
476 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
479 static bool spte_has_volatile_bits(u64 spte)
482 * Always atomicly update spte if it can be updated
483 * out of mmu-lock, it can ensure dirty bit is not lost,
484 * also, it can help us to get a stable is_writable_pte()
485 * to ensure tlb flush is not missed.
487 if (spte_is_locklessly_modifiable(spte))
490 if (!shadow_accessed_mask)
493 if (!is_shadow_present_pte(spte))
496 if ((spte & shadow_accessed_mask) &&
497 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
503 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
505 return (old_spte & bit_mask) && !(new_spte & bit_mask);
508 static bool spte_is_bit_changed(u64 old_spte, u64 new_spte, u64 bit_mask)
510 return (old_spte & bit_mask) != (new_spte & bit_mask);
513 /* Rules for using mmu_spte_set:
514 * Set the sptep from nonpresent to present.
515 * Note: the sptep being assigned *must* be either not present
516 * or in a state where the hardware will not attempt to update
519 static void mmu_spte_set(u64 *sptep, u64 new_spte)
521 WARN_ON(is_shadow_present_pte(*sptep));
522 __set_spte(sptep, new_spte);
525 /* Rules for using mmu_spte_update:
526 * Update the state bits, it means the mapped pfn is not changged.
528 * Whenever we overwrite a writable spte with a read-only one we
529 * should flush remote TLBs. Otherwise rmap_write_protect
530 * will find a read-only spte, even though the writable spte
531 * might be cached on a CPU's TLB, the return value indicates this
534 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
536 u64 old_spte = *sptep;
539 WARN_ON(!is_shadow_present_pte(new_spte));
541 if (!is_shadow_present_pte(old_spte)) {
542 mmu_spte_set(sptep, new_spte);
546 if (!spte_has_volatile_bits(old_spte))
547 __update_clear_spte_fast(sptep, new_spte);
549 old_spte = __update_clear_spte_slow(sptep, new_spte);
552 * For the spte updated out of mmu-lock is safe, since
553 * we always atomicly update it, see the comments in
554 * spte_has_volatile_bits().
556 if (spte_is_locklessly_modifiable(old_spte) &&
557 !is_writable_pte(new_spte))
560 if (!shadow_accessed_mask)
564 * Flush TLB when accessed/dirty bits are changed in the page tables,
565 * to guarantee consistency between TLB and page tables.
567 if (spte_is_bit_changed(old_spte, new_spte,
568 shadow_accessed_mask | shadow_dirty_mask))
571 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
572 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
573 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
574 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
580 * Rules for using mmu_spte_clear_track_bits:
581 * It sets the sptep from present to nonpresent, and track the
582 * state bits, it is used to clear the last level sptep.
584 static int mmu_spte_clear_track_bits(u64 *sptep)
587 u64 old_spte = *sptep;
589 if (!spte_has_volatile_bits(old_spte))
590 __update_clear_spte_fast(sptep, 0ull);
592 old_spte = __update_clear_spte_slow(sptep, 0ull);
594 if (!is_shadow_present_pte(old_spte))
597 pfn = spte_to_pfn(old_spte);
600 * KVM does not hold the refcount of the page used by
601 * kvm mmu, before reclaiming the page, we should
602 * unmap it from mmu first.
604 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
606 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
607 kvm_set_pfn_accessed(pfn);
608 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
609 kvm_set_pfn_dirty(pfn);
614 * Rules for using mmu_spte_clear_no_track:
615 * Directly clear spte without caring the state bits of sptep,
616 * it is used to set the upper level spte.
618 static void mmu_spte_clear_no_track(u64 *sptep)
620 __update_clear_spte_fast(sptep, 0ull);
623 static u64 mmu_spte_get_lockless(u64 *sptep)
625 return __get_spte_lockless(sptep);
628 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
631 * Prevent page table teardown by making any free-er wait during
632 * kvm_flush_remote_tlbs() IPI to all active vcpus.
635 vcpu->mode = READING_SHADOW_PAGE_TABLES;
637 * Make sure a following spte read is not reordered ahead of the write
643 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
646 * Make sure the write to vcpu->mode is not reordered in front of
647 * reads to sptes. If it does, kvm_commit_zap_page() can see us
648 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
651 vcpu->mode = OUTSIDE_GUEST_MODE;
655 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
656 struct kmem_cache *base_cache, int min)
660 if (cache->nobjs >= min)
662 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
663 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
666 cache->objects[cache->nobjs++] = obj;
671 static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
676 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
677 struct kmem_cache *cache)
680 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
683 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
688 if (cache->nobjs >= min)
690 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
691 page = (void *)__get_free_page(GFP_KERNEL);
694 cache->objects[cache->nobjs++] = page;
699 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
702 free_page((unsigned long)mc->objects[--mc->nobjs]);
705 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
709 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
710 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
713 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
716 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
717 mmu_page_header_cache, 4);
722 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
724 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
725 pte_list_desc_cache);
726 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
727 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
728 mmu_page_header_cache);
731 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
736 p = mc->objects[--mc->nobjs];
740 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
742 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
745 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
747 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
750 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
752 if (!sp->role.direct)
753 return sp->gfns[index];
755 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
758 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
761 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
763 sp->gfns[index] = gfn;
767 * Return the pointer to the large page information for a given gfn,
768 * handling slots that are not large page aligned.
770 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
771 struct kvm_memory_slot *slot,
776 idx = gfn_to_index(gfn, slot->base_gfn, level);
777 return &slot->arch.lpage_info[level - 2][idx];
780 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
781 gfn_t gfn, int count)
783 struct kvm_lpage_info *linfo;
786 for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
787 linfo = lpage_info_slot(gfn, slot, i);
788 linfo->disallow_lpage += count;
789 WARN_ON(linfo->disallow_lpage < 0);
793 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
795 update_gfn_disallow_lpage_count(slot, gfn, 1);
798 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
800 update_gfn_disallow_lpage_count(slot, gfn, -1);
803 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
805 struct kvm_memslots *slots;
806 struct kvm_memory_slot *slot;
810 slots = kvm_memslots_for_spte_role(kvm, sp->role);
811 slot = __gfn_to_memslot(slots, gfn);
812 kvm_mmu_gfn_disallow_lpage(slot, gfn);
813 kvm->arch.indirect_shadow_pages++;
816 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
818 struct kvm_memslots *slots;
819 struct kvm_memory_slot *slot;
823 slots = kvm_memslots_for_spte_role(kvm, sp->role);
824 slot = __gfn_to_memslot(slots, gfn);
825 kvm_mmu_gfn_allow_lpage(slot, gfn);
826 kvm->arch.indirect_shadow_pages--;
829 static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level,
830 struct kvm_memory_slot *slot)
832 struct kvm_lpage_info *linfo;
835 linfo = lpage_info_slot(gfn, slot, level);
836 return !!linfo->disallow_lpage;
842 static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn,
845 struct kvm_memory_slot *slot;
847 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
848 return __mmu_gfn_lpage_is_disallowed(gfn, level, slot);
851 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
853 unsigned long page_size;
856 page_size = kvm_host_page_size(kvm, gfn);
858 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
859 if (page_size >= KVM_HPAGE_SIZE(i))
868 static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot,
871 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
873 if (no_dirty_log && slot->dirty_bitmap)
879 static struct kvm_memory_slot *
880 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
883 struct kvm_memory_slot *slot;
885 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
886 if (!memslot_valid_for_gpte(slot, no_dirty_log))
892 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn,
893 bool *force_pt_level)
895 int host_level, level, max_level;
896 struct kvm_memory_slot *slot;
898 if (unlikely(*force_pt_level))
899 return PT_PAGE_TABLE_LEVEL;
901 slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn);
902 *force_pt_level = !memslot_valid_for_gpte(slot, true);
903 if (unlikely(*force_pt_level))
904 return PT_PAGE_TABLE_LEVEL;
906 host_level = host_mapping_level(vcpu->kvm, large_gfn);
908 if (host_level == PT_PAGE_TABLE_LEVEL)
911 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
913 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
914 if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot))
921 * About rmap_head encoding:
923 * If the bit zero of rmap_head->val is clear, then it points to the only spte
924 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
925 * pte_list_desc containing more mappings.
929 * Returns the number of pointers in the rmap chain, not counting the new one.
931 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
932 struct kvm_rmap_head *rmap_head)
934 struct pte_list_desc *desc;
937 if (!rmap_head->val) {
938 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
939 rmap_head->val = (unsigned long)spte;
940 } else if (!(rmap_head->val & 1)) {
941 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
942 desc = mmu_alloc_pte_list_desc(vcpu);
943 desc->sptes[0] = (u64 *)rmap_head->val;
944 desc->sptes[1] = spte;
945 rmap_head->val = (unsigned long)desc | 1;
948 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
949 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
950 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
952 count += PTE_LIST_EXT;
954 if (desc->sptes[PTE_LIST_EXT-1]) {
955 desc->more = mmu_alloc_pte_list_desc(vcpu);
958 for (i = 0; desc->sptes[i]; ++i)
960 desc->sptes[i] = spte;
966 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
967 struct pte_list_desc *desc, int i,
968 struct pte_list_desc *prev_desc)
972 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
974 desc->sptes[i] = desc->sptes[j];
975 desc->sptes[j] = NULL;
978 if (!prev_desc && !desc->more)
979 rmap_head->val = (unsigned long)desc->sptes[0];
982 prev_desc->more = desc->more;
984 rmap_head->val = (unsigned long)desc->more | 1;
985 mmu_free_pte_list_desc(desc);
988 static void pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
990 struct pte_list_desc *desc;
991 struct pte_list_desc *prev_desc;
994 if (!rmap_head->val) {
995 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
997 } else if (!(rmap_head->val & 1)) {
998 rmap_printk("pte_list_remove: %p 1->0\n", spte);
999 if ((u64 *)rmap_head->val != spte) {
1000 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
1005 rmap_printk("pte_list_remove: %p many->many\n", spte);
1006 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1009 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
1010 if (desc->sptes[i] == spte) {
1011 pte_list_desc_remove_entry(rmap_head,
1012 desc, i, prev_desc);
1019 pr_err("pte_list_remove: %p many->many\n", spte);
1024 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
1025 struct kvm_memory_slot *slot)
1029 idx = gfn_to_index(gfn, slot->base_gfn, level);
1030 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1033 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
1034 struct kvm_mmu_page *sp)
1036 struct kvm_memslots *slots;
1037 struct kvm_memory_slot *slot;
1039 slots = kvm_memslots_for_spte_role(kvm, sp->role);
1040 slot = __gfn_to_memslot(slots, gfn);
1041 return __gfn_to_rmap(gfn, sp->role.level, slot);
1044 static bool rmap_can_add(struct kvm_vcpu *vcpu)
1046 struct kvm_mmu_memory_cache *cache;
1048 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1049 return mmu_memory_cache_free_objects(cache);
1052 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1054 struct kvm_mmu_page *sp;
1055 struct kvm_rmap_head *rmap_head;
1057 sp = page_header(__pa(spte));
1058 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1059 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1060 return pte_list_add(vcpu, spte, rmap_head);
1063 static void rmap_remove(struct kvm *kvm, u64 *spte)
1065 struct kvm_mmu_page *sp;
1067 struct kvm_rmap_head *rmap_head;
1069 sp = page_header(__pa(spte));
1070 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1071 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1072 pte_list_remove(spte, rmap_head);
1076 * Used by the following functions to iterate through the sptes linked by a
1077 * rmap. All fields are private and not assumed to be used outside.
1079 struct rmap_iterator {
1080 /* private fields */
1081 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1082 int pos; /* index of the sptep */
1086 * Iteration must be started by this function. This should also be used after
1087 * removing/dropping sptes from the rmap link because in such cases the
1088 * information in the itererator may not be valid.
1090 * Returns sptep if found, NULL otherwise.
1092 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1093 struct rmap_iterator *iter)
1097 if (!rmap_head->val)
1100 if (!(rmap_head->val & 1)) {
1102 sptep = (u64 *)rmap_head->val;
1106 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1108 sptep = iter->desc->sptes[iter->pos];
1110 BUG_ON(!is_shadow_present_pte(*sptep));
1115 * Must be used with a valid iterator: e.g. after rmap_get_first().
1117 * Returns sptep if found, NULL otherwise.
1119 static u64 *rmap_get_next(struct rmap_iterator *iter)
1124 if (iter->pos < PTE_LIST_EXT - 1) {
1126 sptep = iter->desc->sptes[iter->pos];
1131 iter->desc = iter->desc->more;
1135 /* desc->sptes[0] cannot be NULL */
1136 sptep = iter->desc->sptes[iter->pos];
1143 BUG_ON(!is_shadow_present_pte(*sptep));
1147 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1148 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1149 _spte_; _spte_ = rmap_get_next(_iter_))
1151 static void drop_spte(struct kvm *kvm, u64 *sptep)
1153 if (mmu_spte_clear_track_bits(sptep))
1154 rmap_remove(kvm, sptep);
1158 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1160 if (is_large_pte(*sptep)) {
1161 WARN_ON(page_header(__pa(sptep))->role.level ==
1162 PT_PAGE_TABLE_LEVEL);
1163 drop_spte(kvm, sptep);
1171 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1173 if (__drop_large_spte(vcpu->kvm, sptep))
1174 kvm_flush_remote_tlbs(vcpu->kvm);
1178 * Write-protect on the specified @sptep, @pt_protect indicates whether
1179 * spte write-protection is caused by protecting shadow page table.
1181 * Note: write protection is difference between dirty logging and spte
1183 * - for dirty logging, the spte can be set to writable at anytime if
1184 * its dirty bitmap is properly set.
1185 * - for spte protection, the spte can be writable only after unsync-ing
1188 * Return true if tlb need be flushed.
1190 static bool spte_write_protect(struct kvm *kvm, u64 *sptep, bool pt_protect)
1194 if (!is_writable_pte(spte) &&
1195 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1198 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1201 spte &= ~SPTE_MMU_WRITEABLE;
1202 spte = spte & ~PT_WRITABLE_MASK;
1204 return mmu_spte_update(sptep, spte);
1207 static bool __rmap_write_protect(struct kvm *kvm,
1208 struct kvm_rmap_head *rmap_head,
1212 struct rmap_iterator iter;
1215 for_each_rmap_spte(rmap_head, &iter, sptep)
1216 flush |= spte_write_protect(kvm, sptep, pt_protect);
1221 static bool spte_clear_dirty(struct kvm *kvm, u64 *sptep)
1225 rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep);
1227 spte &= ~shadow_dirty_mask;
1229 return mmu_spte_update(sptep, spte);
1232 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1235 struct rmap_iterator iter;
1238 for_each_rmap_spte(rmap_head, &iter, sptep)
1239 flush |= spte_clear_dirty(kvm, sptep);
1244 static bool spte_set_dirty(struct kvm *kvm, u64 *sptep)
1248 rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep);
1250 spte |= shadow_dirty_mask;
1252 return mmu_spte_update(sptep, spte);
1255 static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1258 struct rmap_iterator iter;
1261 for_each_rmap_spte(rmap_head, &iter, sptep)
1262 flush |= spte_set_dirty(kvm, sptep);
1268 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1269 * @kvm: kvm instance
1270 * @slot: slot to protect
1271 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1272 * @mask: indicates which pages we should protect
1274 * Used when we do not need to care about huge page mappings: e.g. during dirty
1275 * logging we do not have any such mappings.
1277 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1278 struct kvm_memory_slot *slot,
1279 gfn_t gfn_offset, unsigned long mask)
1281 struct kvm_rmap_head *rmap_head;
1284 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1285 PT_PAGE_TABLE_LEVEL, slot);
1286 __rmap_write_protect(kvm, rmap_head, false);
1288 /* clear the first set bit */
1294 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages
1295 * @kvm: kvm instance
1296 * @slot: slot to clear D-bit
1297 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1298 * @mask: indicates which pages we should clear D-bit
1300 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1302 void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1303 struct kvm_memory_slot *slot,
1304 gfn_t gfn_offset, unsigned long mask)
1306 struct kvm_rmap_head *rmap_head;
1309 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1310 PT_PAGE_TABLE_LEVEL, slot);
1311 __rmap_clear_dirty(kvm, rmap_head);
1313 /* clear the first set bit */
1317 EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked);
1320 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1323 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1324 * enable dirty logging for them.
1326 * Used when we do not need to care about huge page mappings: e.g. during dirty
1327 * logging we do not have any such mappings.
1329 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1330 struct kvm_memory_slot *slot,
1331 gfn_t gfn_offset, unsigned long mask)
1333 if (kvm_x86_ops->enable_log_dirty_pt_masked)
1334 kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset,
1337 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1340 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1341 struct kvm_memory_slot *slot, u64 gfn)
1343 struct kvm_rmap_head *rmap_head;
1345 bool write_protected = false;
1347 for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) {
1348 rmap_head = __gfn_to_rmap(gfn, i, slot);
1349 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1352 return write_protected;
1355 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1357 struct kvm_memory_slot *slot;
1359 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1360 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn);
1363 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head)
1366 struct rmap_iterator iter;
1369 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1370 rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep);
1372 drop_spte(kvm, sptep);
1379 static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1380 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1383 return kvm_zap_rmapp(kvm, rmap_head);
1386 static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1387 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1391 struct rmap_iterator iter;
1394 pte_t *ptep = (pte_t *)data;
1397 WARN_ON(pte_huge(*ptep));
1398 new_pfn = pte_pfn(*ptep);
1401 for_each_rmap_spte(rmap_head, &iter, sptep) {
1402 rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n",
1403 sptep, *sptep, gfn, level);
1407 if (pte_write(*ptep)) {
1408 drop_spte(kvm, sptep);
1411 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1412 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1414 new_spte &= ~PT_WRITABLE_MASK;
1415 new_spte &= ~SPTE_HOST_WRITEABLE;
1416 new_spte &= ~shadow_accessed_mask;
1418 mmu_spte_clear_track_bits(sptep);
1419 mmu_spte_set(sptep, new_spte);
1424 kvm_flush_remote_tlbs(kvm);
1429 struct slot_rmap_walk_iterator {
1431 struct kvm_memory_slot *slot;
1437 /* output fields. */
1439 struct kvm_rmap_head *rmap;
1442 /* private field. */
1443 struct kvm_rmap_head *end_rmap;
1447 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1449 iterator->level = level;
1450 iterator->gfn = iterator->start_gfn;
1451 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1452 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1457 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1458 struct kvm_memory_slot *slot, int start_level,
1459 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1461 iterator->slot = slot;
1462 iterator->start_level = start_level;
1463 iterator->end_level = end_level;
1464 iterator->start_gfn = start_gfn;
1465 iterator->end_gfn = end_gfn;
1467 rmap_walk_init_level(iterator, iterator->start_level);
1470 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1472 return !!iterator->rmap;
1475 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1477 if (++iterator->rmap <= iterator->end_rmap) {
1478 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1482 if (++iterator->level > iterator->end_level) {
1483 iterator->rmap = NULL;
1487 rmap_walk_init_level(iterator, iterator->level);
1490 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1491 _start_gfn, _end_gfn, _iter_) \
1492 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1493 _end_level_, _start_gfn, _end_gfn); \
1494 slot_rmap_walk_okay(_iter_); \
1495 slot_rmap_walk_next(_iter_))
1497 static int kvm_handle_hva_range(struct kvm *kvm,
1498 unsigned long start,
1501 int (*handler)(struct kvm *kvm,
1502 struct kvm_rmap_head *rmap_head,
1503 struct kvm_memory_slot *slot,
1506 unsigned long data))
1508 struct kvm_memslots *slots;
1509 struct kvm_memory_slot *memslot;
1510 struct slot_rmap_walk_iterator iterator;
1514 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1515 slots = __kvm_memslots(kvm, i);
1516 kvm_for_each_memslot(memslot, slots) {
1517 unsigned long hva_start, hva_end;
1518 gfn_t gfn_start, gfn_end;
1520 hva_start = max(start, memslot->userspace_addr);
1521 hva_end = min(end, memslot->userspace_addr +
1522 (memslot->npages << PAGE_SHIFT));
1523 if (hva_start >= hva_end)
1526 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1527 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1529 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1530 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1532 for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL,
1533 PT_MAX_HUGEPAGE_LEVEL,
1534 gfn_start, gfn_end - 1,
1536 ret |= handler(kvm, iterator.rmap, memslot,
1537 iterator.gfn, iterator.level, data);
1544 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1546 int (*handler)(struct kvm *kvm,
1547 struct kvm_rmap_head *rmap_head,
1548 struct kvm_memory_slot *slot,
1549 gfn_t gfn, int level,
1550 unsigned long data))
1552 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1555 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1557 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1560 int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1562 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1565 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1567 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1570 static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1571 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1575 struct rmap_iterator uninitialized_var(iter);
1578 BUG_ON(!shadow_accessed_mask);
1580 for_each_rmap_spte(rmap_head, &iter, sptep) {
1581 if (*sptep & shadow_accessed_mask) {
1583 clear_bit((ffs(shadow_accessed_mask) - 1),
1584 (unsigned long *)sptep);
1588 trace_kvm_age_page(gfn, level, slot, young);
1592 static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1593 struct kvm_memory_slot *slot, gfn_t gfn,
1594 int level, unsigned long data)
1597 struct rmap_iterator iter;
1601 * If there's no access bit in the secondary pte set by the
1602 * hardware it's up to gup-fast/gup to set the access bit in
1603 * the primary pte or in the page structure.
1605 if (!shadow_accessed_mask)
1608 for_each_rmap_spte(rmap_head, &iter, sptep) {
1609 if (*sptep & shadow_accessed_mask) {
1618 #define RMAP_RECYCLE_THRESHOLD 1000
1620 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1622 struct kvm_rmap_head *rmap_head;
1623 struct kvm_mmu_page *sp;
1625 sp = page_header(__pa(spte));
1627 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1629 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0);
1630 kvm_flush_remote_tlbs(vcpu->kvm);
1633 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end)
1636 * In case of absence of EPT Access and Dirty Bits supports,
1637 * emulate the accessed bit for EPT, by checking if this page has
1638 * an EPT mapping, and clearing it if it does. On the next access,
1639 * a new EPT mapping will be established.
1640 * This has some overhead, but not as much as the cost of swapping
1641 * out actively used pages or breaking up actively used hugepages.
1643 if (!shadow_accessed_mask) {
1645 * We are holding the kvm->mmu_lock, and we are blowing up
1646 * shadow PTEs. MMU notifier consumers need to be kept at bay.
1647 * This is correct as long as we don't decouple the mmu_lock
1648 * protected regions (like invalidate_range_start|end does).
1650 kvm->mmu_notifier_seq++;
1651 return kvm_handle_hva_range(kvm, start, end, 0,
1655 return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp);
1658 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1660 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1664 static int is_empty_shadow_page(u64 *spt)
1669 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1670 if (is_shadow_present_pte(*pos)) {
1671 printk(KERN_ERR "%s: %p %llx\n", __func__,
1680 * This value is the sum of all of the kvm instances's
1681 * kvm->arch.n_used_mmu_pages values. We need a global,
1682 * aggregate version in order to make the slab shrinker
1685 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1687 kvm->arch.n_used_mmu_pages += nr;
1688 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1691 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1693 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1694 hlist_del(&sp->hash_link);
1695 list_del(&sp->link);
1696 free_page((unsigned long)sp->spt);
1697 if (!sp->role.direct)
1698 free_page((unsigned long)sp->gfns);
1699 kmem_cache_free(mmu_page_header_cache, sp);
1702 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1704 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1707 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1708 struct kvm_mmu_page *sp, u64 *parent_pte)
1713 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1716 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1719 pte_list_remove(parent_pte, &sp->parent_ptes);
1722 static void drop_parent_pte(struct kvm_mmu_page *sp,
1725 mmu_page_remove_parent_pte(sp, parent_pte);
1726 mmu_spte_clear_no_track(parent_pte);
1729 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1731 struct kvm_mmu_page *sp;
1733 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1734 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1736 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1737 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1740 * The active_mmu_pages list is the FIFO list, do not move the
1741 * page until it is zapped. kvm_zap_obsolete_pages depends on
1742 * this feature. See the comments in kvm_zap_obsolete_pages().
1744 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1745 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1749 static void mark_unsync(u64 *spte);
1750 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1753 struct rmap_iterator iter;
1755 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1760 static void mark_unsync(u64 *spte)
1762 struct kvm_mmu_page *sp;
1765 sp = page_header(__pa(spte));
1766 index = spte - sp->spt;
1767 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1769 if (sp->unsync_children++)
1771 kvm_mmu_mark_parents_unsync(sp);
1774 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1775 struct kvm_mmu_page *sp)
1780 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1784 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1785 struct kvm_mmu_page *sp, u64 *spte,
1791 #define KVM_PAGE_ARRAY_NR 16
1793 struct kvm_mmu_pages {
1794 struct mmu_page_and_offset {
1795 struct kvm_mmu_page *sp;
1797 } page[KVM_PAGE_ARRAY_NR];
1801 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1807 for (i=0; i < pvec->nr; i++)
1808 if (pvec->page[i].sp == sp)
1811 pvec->page[pvec->nr].sp = sp;
1812 pvec->page[pvec->nr].idx = idx;
1814 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1817 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1819 --sp->unsync_children;
1820 WARN_ON((int)sp->unsync_children < 0);
1821 __clear_bit(idx, sp->unsync_child_bitmap);
1824 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1825 struct kvm_mmu_pages *pvec)
1827 int i, ret, nr_unsync_leaf = 0;
1829 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1830 struct kvm_mmu_page *child;
1831 u64 ent = sp->spt[i];
1833 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1834 clear_unsync_child_bit(sp, i);
1838 child = page_header(ent & PT64_BASE_ADDR_MASK);
1840 if (child->unsync_children) {
1841 if (mmu_pages_add(pvec, child, i))
1844 ret = __mmu_unsync_walk(child, pvec);
1846 clear_unsync_child_bit(sp, i);
1848 } else if (ret > 0) {
1849 nr_unsync_leaf += ret;
1852 } else if (child->unsync) {
1854 if (mmu_pages_add(pvec, child, i))
1857 clear_unsync_child_bit(sp, i);
1860 return nr_unsync_leaf;
1863 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1864 struct kvm_mmu_pages *pvec)
1866 if (!sp->unsync_children)
1869 mmu_pages_add(pvec, sp, 0);
1870 return __mmu_unsync_walk(sp, pvec);
1873 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1875 WARN_ON(!sp->unsync);
1876 trace_kvm_mmu_sync_page(sp);
1878 --kvm->stat.mmu_unsync;
1881 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1882 struct list_head *invalid_list);
1883 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1884 struct list_head *invalid_list);
1887 * NOTE: we should pay more attention on the zapped-obsolete page
1888 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1889 * since it has been deleted from active_mmu_pages but still can be found
1892 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1893 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1894 * all the obsolete pages.
1896 #define for_each_gfn_sp(_kvm, _sp, _gfn) \
1897 hlist_for_each_entry(_sp, \
1898 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1899 if ((_sp)->gfn != (_gfn)) {} else
1901 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1902 for_each_gfn_sp(_kvm, _sp, _gfn) \
1903 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1905 /* @sp->gfn should be write-protected at the call site */
1906 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1907 struct list_head *invalid_list, bool clear_unsync)
1909 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1910 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1915 kvm_unlink_unsync_page(vcpu->kvm, sp);
1917 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1918 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1922 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1926 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1927 struct kvm_mmu_page *sp)
1929 LIST_HEAD(invalid_list);
1932 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1934 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1939 #ifdef CONFIG_KVM_MMU_AUDIT
1940 #include "mmu_audit.c"
1942 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1943 static void mmu_audit_disable(void) { }
1946 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1947 struct list_head *invalid_list)
1949 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1952 /* @gfn should be write-protected at the call site */
1953 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1955 struct kvm_mmu_page *s;
1956 LIST_HEAD(invalid_list);
1959 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1963 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1964 kvm_unlink_unsync_page(vcpu->kvm, s);
1965 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1966 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1967 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1973 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1975 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1978 struct mmu_page_path {
1979 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1980 unsigned int idx[PT64_ROOT_LEVEL-1];
1983 #define for_each_sp(pvec, sp, parents, i) \
1984 for (i = mmu_pages_next(&pvec, &parents, -1), \
1985 sp = pvec.page[i].sp; \
1986 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1987 i = mmu_pages_next(&pvec, &parents, i))
1989 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1990 struct mmu_page_path *parents,
1995 for (n = i+1; n < pvec->nr; n++) {
1996 struct kvm_mmu_page *sp = pvec->page[n].sp;
1998 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1999 parents->idx[0] = pvec->page[n].idx;
2003 parents->parent[sp->role.level-2] = sp;
2004 parents->idx[sp->role.level-1] = pvec->page[n].idx;
2010 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
2012 struct kvm_mmu_page *sp;
2013 unsigned int level = 0;
2016 unsigned int idx = parents->idx[level];
2018 sp = parents->parent[level];
2022 clear_unsync_child_bit(sp, idx);
2024 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
2027 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
2028 struct mmu_page_path *parents,
2029 struct kvm_mmu_pages *pvec)
2031 parents->parent[parent->role.level-1] = NULL;
2035 static void mmu_sync_children(struct kvm_vcpu *vcpu,
2036 struct kvm_mmu_page *parent)
2039 struct kvm_mmu_page *sp;
2040 struct mmu_page_path parents;
2041 struct kvm_mmu_pages pages;
2042 LIST_HEAD(invalid_list);
2044 kvm_mmu_pages_init(parent, &parents, &pages);
2045 while (mmu_unsync_walk(parent, &pages)) {
2046 bool protected = false;
2048 for_each_sp(pages, sp, parents, i)
2049 protected |= rmap_write_protect(vcpu, sp->gfn);
2052 kvm_flush_remote_tlbs(vcpu->kvm);
2054 for_each_sp(pages, sp, parents, i) {
2055 kvm_sync_page(vcpu, sp, &invalid_list);
2056 mmu_pages_clear_parents(&parents);
2058 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2059 cond_resched_lock(&vcpu->kvm->mmu_lock);
2060 kvm_mmu_pages_init(parent, &parents, &pages);
2064 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
2066 sp->write_flooding_count = 0;
2069 static void clear_sp_write_flooding_count(u64 *spte)
2071 struct kvm_mmu_page *sp = page_header(__pa(spte));
2073 __clear_sp_write_flooding_count(sp);
2076 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
2078 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
2081 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
2088 union kvm_mmu_page_role role;
2090 struct kvm_mmu_page *sp;
2091 bool need_sync = false;
2093 role = vcpu->arch.mmu.base_role;
2095 role.direct = direct;
2098 role.access = access;
2099 if (!vcpu->arch.mmu.direct_map
2100 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
2101 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2102 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2103 role.quadrant = quadrant;
2105 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
2106 if (is_obsolete_sp(vcpu->kvm, sp))
2109 if (!need_sync && sp->unsync)
2112 if (sp->role.word != role.word)
2115 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
2118 if (sp->unsync_children)
2119 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2121 __clear_sp_write_flooding_count(sp);
2122 trace_kvm_mmu_get_page(sp, false);
2126 ++vcpu->kvm->stat.mmu_cache_miss;
2128 sp = kvm_mmu_alloc_page(vcpu, direct);
2132 hlist_add_head(&sp->hash_link,
2133 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
2135 if (rmap_write_protect(vcpu, gfn))
2136 kvm_flush_remote_tlbs(vcpu->kvm);
2137 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
2138 kvm_sync_pages(vcpu, gfn);
2140 account_shadowed(vcpu->kvm, sp);
2142 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
2143 clear_page(sp->spt);
2144 trace_kvm_mmu_get_page(sp, true);
2148 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2149 struct kvm_vcpu *vcpu, u64 addr)
2151 iterator->addr = addr;
2152 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2153 iterator->level = vcpu->arch.mmu.shadow_root_level;
2155 if (iterator->level == PT64_ROOT_LEVEL &&
2156 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2157 !vcpu->arch.mmu.direct_map)
2160 if (iterator->level == PT32E_ROOT_LEVEL) {
2161 iterator->shadow_addr
2162 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2163 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2165 if (!iterator->shadow_addr)
2166 iterator->level = 0;
2170 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2172 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2175 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2176 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2180 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2183 if (is_last_spte(spte, iterator->level)) {
2184 iterator->level = 0;
2188 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2192 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2194 return __shadow_walk_next(iterator, *iterator->sptep);
2197 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2198 struct kvm_mmu_page *sp)
2202 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2203 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2205 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2206 shadow_user_mask | shadow_x_mask | shadow_accessed_mask;
2208 mmu_spte_set(sptep, spte);
2210 mmu_page_add_parent_pte(vcpu, sp, sptep);
2212 if (sp->unsync_children || sp->unsync)
2216 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2217 unsigned direct_access)
2219 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2220 struct kvm_mmu_page *child;
2223 * For the direct sp, if the guest pte's dirty bit
2224 * changed form clean to dirty, it will corrupt the
2225 * sp's access: allow writable in the read-only sp,
2226 * so we should update the spte at this point to get
2227 * a new sp with the correct access.
2229 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2230 if (child->role.access == direct_access)
2233 drop_parent_pte(child, sptep);
2234 kvm_flush_remote_tlbs(vcpu->kvm);
2238 static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2242 struct kvm_mmu_page *child;
2245 if (is_shadow_present_pte(pte)) {
2246 if (is_last_spte(pte, sp->role.level)) {
2247 drop_spte(kvm, spte);
2248 if (is_large_pte(pte))
2251 child = page_header(pte & PT64_BASE_ADDR_MASK);
2252 drop_parent_pte(child, spte);
2257 if (is_mmio_spte(pte))
2258 mmu_spte_clear_no_track(spte);
2263 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2264 struct kvm_mmu_page *sp)
2268 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2269 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2272 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2275 struct rmap_iterator iter;
2277 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2278 drop_parent_pte(sp, sptep);
2281 static int mmu_zap_unsync_children(struct kvm *kvm,
2282 struct kvm_mmu_page *parent,
2283 struct list_head *invalid_list)
2286 struct mmu_page_path parents;
2287 struct kvm_mmu_pages pages;
2289 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2292 kvm_mmu_pages_init(parent, &parents, &pages);
2293 while (mmu_unsync_walk(parent, &pages)) {
2294 struct kvm_mmu_page *sp;
2296 for_each_sp(pages, sp, parents, i) {
2297 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2298 mmu_pages_clear_parents(&parents);
2301 kvm_mmu_pages_init(parent, &parents, &pages);
2307 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2308 struct list_head *invalid_list)
2312 trace_kvm_mmu_prepare_zap_page(sp);
2313 ++kvm->stat.mmu_shadow_zapped;
2314 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2315 kvm_mmu_page_unlink_children(kvm, sp);
2316 kvm_mmu_unlink_parents(kvm, sp);
2318 if (!sp->role.invalid && !sp->role.direct)
2319 unaccount_shadowed(kvm, sp);
2322 kvm_unlink_unsync_page(kvm, sp);
2323 if (!sp->root_count) {
2326 list_move(&sp->link, invalid_list);
2327 kvm_mod_used_mmu_pages(kvm, -1);
2329 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2332 * The obsolete pages can not be used on any vcpus.
2333 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2335 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2336 kvm_reload_remote_mmus(kvm);
2339 sp->role.invalid = 1;
2343 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2344 struct list_head *invalid_list)
2346 struct kvm_mmu_page *sp, *nsp;
2348 if (list_empty(invalid_list))
2352 * wmb: make sure everyone sees our modifications to the page tables
2353 * rmb: make sure we see changes to vcpu->mode
2358 * Wait for all vcpus to exit guest mode and/or lockless shadow
2361 kvm_flush_remote_tlbs(kvm);
2363 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2364 WARN_ON(!sp->role.invalid || sp->root_count);
2365 kvm_mmu_free_page(sp);
2369 static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2370 struct list_head *invalid_list)
2372 struct kvm_mmu_page *sp;
2374 if (list_empty(&kvm->arch.active_mmu_pages))
2377 sp = list_last_entry(&kvm->arch.active_mmu_pages,
2378 struct kvm_mmu_page, link);
2379 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2385 * Changing the number of mmu pages allocated to the vm
2386 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2388 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2390 LIST_HEAD(invalid_list);
2392 spin_lock(&kvm->mmu_lock);
2394 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2395 /* Need to free some mmu pages to achieve the goal. */
2396 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2397 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2400 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2401 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2404 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2406 spin_unlock(&kvm->mmu_lock);
2409 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2411 struct kvm_mmu_page *sp;
2412 LIST_HEAD(invalid_list);
2415 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2417 spin_lock(&kvm->mmu_lock);
2418 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2419 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2422 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2424 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2425 spin_unlock(&kvm->mmu_lock);
2429 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2431 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2433 trace_kvm_mmu_unsync_page(sp);
2434 ++vcpu->kvm->stat.mmu_unsync;
2437 kvm_mmu_mark_parents_unsync(sp);
2440 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2442 struct kvm_mmu_page *s;
2444 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2447 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2448 __kvm_unsync_page(vcpu, s);
2452 static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2455 struct kvm_mmu_page *s;
2456 bool need_unsync = false;
2458 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2461 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2465 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2472 kvm_unsync_pages(vcpu, gfn);
2477 static bool kvm_is_mmio_pfn(kvm_pfn_t pfn)
2480 return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn));
2485 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2486 unsigned pte_access, int level,
2487 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2488 bool can_unsync, bool host_writable)
2493 if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
2496 spte = PT_PRESENT_MASK;
2498 spte |= shadow_accessed_mask;
2500 if (pte_access & ACC_EXEC_MASK)
2501 spte |= shadow_x_mask;
2503 spte |= shadow_nx_mask;
2505 if (pte_access & ACC_USER_MASK)
2506 spte |= shadow_user_mask;
2508 if (level > PT_PAGE_TABLE_LEVEL)
2509 spte |= PT_PAGE_SIZE_MASK;
2511 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2512 kvm_is_mmio_pfn(pfn));
2515 spte |= SPTE_HOST_WRITEABLE;
2517 pte_access &= ~ACC_WRITE_MASK;
2519 spte |= (u64)pfn << PAGE_SHIFT;
2521 if (pte_access & ACC_WRITE_MASK) {
2524 * Other vcpu creates new sp in the window between
2525 * mapping_level() and acquiring mmu-lock. We can
2526 * allow guest to retry the access, the mapping can
2527 * be fixed if guest refault.
2529 if (level > PT_PAGE_TABLE_LEVEL &&
2530 mmu_gfn_lpage_is_disallowed(vcpu, gfn, level))
2533 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2536 * Optimization: for pte sync, if spte was writable the hash
2537 * lookup is unnecessary (and expensive). Write protection
2538 * is responsibility of mmu_get_page / kvm_sync_page.
2539 * Same reasoning can be applied to dirty page accounting.
2541 if (!can_unsync && is_writable_pte(*sptep))
2544 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2545 pgprintk("%s: found shadow page for %llx, marking ro\n",
2548 pte_access &= ~ACC_WRITE_MASK;
2549 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2553 if (pte_access & ACC_WRITE_MASK) {
2554 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2555 spte |= shadow_dirty_mask;
2559 if (mmu_spte_update(sptep, spte))
2560 kvm_flush_remote_tlbs(vcpu->kvm);
2565 static bool mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access,
2566 int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn,
2567 bool speculative, bool host_writable)
2569 int was_rmapped = 0;
2571 bool emulate = false;
2573 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2574 *sptep, write_fault, gfn);
2576 if (is_shadow_present_pte(*sptep)) {
2578 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2579 * the parent of the now unreachable PTE.
2581 if (level > PT_PAGE_TABLE_LEVEL &&
2582 !is_large_pte(*sptep)) {
2583 struct kvm_mmu_page *child;
2586 child = page_header(pte & PT64_BASE_ADDR_MASK);
2587 drop_parent_pte(child, sptep);
2588 kvm_flush_remote_tlbs(vcpu->kvm);
2589 } else if (pfn != spte_to_pfn(*sptep)) {
2590 pgprintk("hfn old %llx new %llx\n",
2591 spte_to_pfn(*sptep), pfn);
2592 drop_spte(vcpu->kvm, sptep);
2593 kvm_flush_remote_tlbs(vcpu->kvm);
2598 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2599 true, host_writable)) {
2602 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2605 if (unlikely(is_mmio_spte(*sptep)))
2608 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2609 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2610 is_large_pte(*sptep)? "2MB" : "4kB",
2611 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2613 if (!was_rmapped && is_large_pte(*sptep))
2614 ++vcpu->kvm->stat.lpages;
2616 if (is_shadow_present_pte(*sptep)) {
2618 rmap_count = rmap_add(vcpu, sptep, gfn);
2619 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2620 rmap_recycle(vcpu, sptep, gfn);
2624 kvm_release_pfn_clean(pfn);
2629 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2632 struct kvm_memory_slot *slot;
2634 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2636 return KVM_PFN_ERR_FAULT;
2638 return gfn_to_pfn_memslot_atomic(slot, gfn);
2641 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2642 struct kvm_mmu_page *sp,
2643 u64 *start, u64 *end)
2645 struct page *pages[PTE_PREFETCH_NUM];
2646 struct kvm_memory_slot *slot;
2647 unsigned access = sp->role.access;
2651 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2652 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2656 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2660 for (i = 0; i < ret; i++, gfn++, start++)
2661 mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn,
2662 page_to_pfn(pages[i]), true, true);
2667 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2668 struct kvm_mmu_page *sp, u64 *sptep)
2670 u64 *spte, *start = NULL;
2673 WARN_ON(!sp->role.direct);
2675 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2678 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2679 if (is_shadow_present_pte(*spte) || spte == sptep) {
2682 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2690 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2692 struct kvm_mmu_page *sp;
2695 * Since it's no accessed bit on EPT, it's no way to
2696 * distinguish between actually accessed translations
2697 * and prefetched, so disable pte prefetch if EPT is
2700 if (!shadow_accessed_mask)
2703 sp = page_header(__pa(sptep));
2704 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2707 __direct_pte_prefetch(vcpu, sp, sptep);
2710 static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable,
2711 int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
2713 struct kvm_shadow_walk_iterator iterator;
2714 struct kvm_mmu_page *sp;
2718 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2721 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2722 if (iterator.level == level) {
2723 emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2724 write, level, gfn, pfn, prefault,
2726 direct_pte_prefetch(vcpu, iterator.sptep);
2727 ++vcpu->stat.pf_fixed;
2731 drop_large_spte(vcpu, iterator.sptep);
2732 if (!is_shadow_present_pte(*iterator.sptep)) {
2733 u64 base_addr = iterator.addr;
2735 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2736 pseudo_gfn = base_addr >> PAGE_SHIFT;
2737 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2738 iterator.level - 1, 1, ACC_ALL);
2740 link_shadow_page(vcpu, iterator.sptep, sp);
2746 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2750 info.si_signo = SIGBUS;
2752 info.si_code = BUS_MCEERR_AR;
2753 info.si_addr = (void __user *)address;
2754 info.si_addr_lsb = PAGE_SHIFT;
2756 send_sig_info(SIGBUS, &info, tsk);
2759 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2762 * Do not cache the mmio info caused by writing the readonly gfn
2763 * into the spte otherwise read access on readonly gfn also can
2764 * caused mmio page fault and treat it as mmio access.
2765 * Return 1 to tell kvm to emulate it.
2767 if (pfn == KVM_PFN_ERR_RO_FAULT)
2770 if (pfn == KVM_PFN_ERR_HWPOISON) {
2771 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2778 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2779 gfn_t *gfnp, kvm_pfn_t *pfnp,
2782 kvm_pfn_t pfn = *pfnp;
2784 int level = *levelp;
2787 * Check if it's a transparent hugepage. If this would be an
2788 * hugetlbfs page, level wouldn't be set to
2789 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2792 if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) &&
2793 level == PT_PAGE_TABLE_LEVEL &&
2794 PageTransCompound(pfn_to_page(pfn)) &&
2795 !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) {
2798 * mmu_notifier_retry was successful and we hold the
2799 * mmu_lock here, so the pmd can't become splitting
2800 * from under us, and in turn
2801 * __split_huge_page_refcount() can't run from under
2802 * us and we can safely transfer the refcount from
2803 * PG_tail to PG_head as we switch the pfn to tail to
2806 *levelp = level = PT_DIRECTORY_LEVEL;
2807 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2808 VM_BUG_ON((gfn & mask) != (pfn & mask));
2812 kvm_release_pfn_clean(pfn);
2820 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2821 kvm_pfn_t pfn, unsigned access, int *ret_val)
2825 /* The pfn is invalid, report the error! */
2826 if (unlikely(is_error_pfn(pfn))) {
2827 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2831 if (unlikely(is_noslot_pfn(pfn)))
2832 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2839 static bool page_fault_can_be_fast(u32 error_code)
2842 * Do not fix the mmio spte with invalid generation number which
2843 * need to be updated by slow page fault path.
2845 if (unlikely(error_code & PFERR_RSVD_MASK))
2849 * #PF can be fast only if the shadow page table is present and it
2850 * is caused by write-protect, that means we just need change the
2851 * W bit of the spte which can be done out of mmu-lock.
2853 if (!(error_code & PFERR_PRESENT_MASK) ||
2854 !(error_code & PFERR_WRITE_MASK))
2861 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
2862 u64 *sptep, u64 spte)
2866 WARN_ON(!sp->role.direct);
2869 * The gfn of direct spte is stable since it is calculated
2872 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2875 * Theoretically we could also set dirty bit (and flush TLB) here in
2876 * order to eliminate unnecessary PML logging. See comments in
2877 * set_spte. But fast_page_fault is very unlikely to happen with PML
2878 * enabled, so we do not do this. This might result in the same GPA
2879 * to be logged in PML buffer again when the write really happens, and
2880 * eventually to be called by mark_page_dirty twice. But it's also no
2881 * harm. This also avoids the TLB flush needed after setting dirty bit
2882 * so non-PML cases won't be impacted.
2884 * Compare with set_spte where instead shadow_dirty_mask is set.
2886 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2887 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2894 * - true: let the vcpu to access on the same address again.
2895 * - false: let the real page fault path to fix it.
2897 static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2900 struct kvm_shadow_walk_iterator iterator;
2901 struct kvm_mmu_page *sp;
2905 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2908 if (!page_fault_can_be_fast(error_code))
2911 walk_shadow_page_lockless_begin(vcpu);
2912 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2913 if (!is_shadow_present_pte(spte) || iterator.level < level)
2917 * If the mapping has been changed, let the vcpu fault on the
2918 * same address again.
2920 if (!is_shadow_present_pte(spte)) {
2925 sp = page_header(__pa(iterator.sptep));
2926 if (!is_last_spte(spte, sp->role.level))
2930 * Check if it is a spurious fault caused by TLB lazily flushed.
2932 * Need not check the access of upper level table entries since
2933 * they are always ACC_ALL.
2935 if (is_writable_pte(spte)) {
2941 * Currently, to simplify the code, only the spte write-protected
2942 * by dirty-log can be fast fixed.
2944 if (!spte_is_locklessly_modifiable(spte))
2948 * Do not fix write-permission on the large spte since we only dirty
2949 * the first page into the dirty-bitmap in fast_pf_fix_direct_spte()
2950 * that means other pages are missed if its slot is dirty-logged.
2952 * Instead, we let the slow page fault path create a normal spte to
2955 * See the comments in kvm_arch_commit_memory_region().
2957 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2961 * Currently, fast page fault only works for direct mapping since
2962 * the gfn is not stable for indirect shadow page.
2963 * See Documentation/virtual/kvm/locking.txt to get more detail.
2965 ret = fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte);
2967 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2969 walk_shadow_page_lockless_end(vcpu);
2974 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2975 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable);
2976 static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2978 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2979 gfn_t gfn, bool prefault)
2983 bool force_pt_level = false;
2985 unsigned long mmu_seq;
2986 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2988 level = mapping_level(vcpu, gfn, &force_pt_level);
2989 if (likely(!force_pt_level)) {
2991 * This path builds a PAE pagetable - so we can map
2992 * 2mb pages at maximum. Therefore check if the level
2993 * is larger than that.
2995 if (level > PT_DIRECTORY_LEVEL)
2996 level = PT_DIRECTORY_LEVEL;
2998 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3001 if (fast_page_fault(vcpu, v, level, error_code))
3004 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3007 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
3010 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
3013 spin_lock(&vcpu->kvm->mmu_lock);
3014 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3016 make_mmu_pages_available(vcpu);
3017 if (likely(!force_pt_level))
3018 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3019 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3020 spin_unlock(&vcpu->kvm->mmu_lock);
3025 spin_unlock(&vcpu->kvm->mmu_lock);
3026 kvm_release_pfn_clean(pfn);
3031 static void mmu_free_roots(struct kvm_vcpu *vcpu)
3034 struct kvm_mmu_page *sp;
3035 LIST_HEAD(invalid_list);
3037 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3040 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
3041 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
3042 vcpu->arch.mmu.direct_map)) {
3043 hpa_t root = vcpu->arch.mmu.root_hpa;
3045 spin_lock(&vcpu->kvm->mmu_lock);
3046 sp = page_header(root);
3048 if (!sp->root_count && sp->role.invalid) {
3049 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3050 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3052 spin_unlock(&vcpu->kvm->mmu_lock);
3053 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3057 spin_lock(&vcpu->kvm->mmu_lock);
3058 for (i = 0; i < 4; ++i) {
3059 hpa_t root = vcpu->arch.mmu.pae_root[i];
3062 root &= PT64_BASE_ADDR_MASK;
3063 sp = page_header(root);
3065 if (!sp->root_count && sp->role.invalid)
3066 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3069 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3071 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3072 spin_unlock(&vcpu->kvm->mmu_lock);
3073 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
3076 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3080 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3081 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3088 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3090 struct kvm_mmu_page *sp;
3093 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3094 spin_lock(&vcpu->kvm->mmu_lock);
3095 make_mmu_pages_available(vcpu);
3096 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL, 1, ACC_ALL);
3098 spin_unlock(&vcpu->kvm->mmu_lock);
3099 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3100 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3101 for (i = 0; i < 4; ++i) {
3102 hpa_t root = vcpu->arch.mmu.pae_root[i];
3104 MMU_WARN_ON(VALID_PAGE(root));
3105 spin_lock(&vcpu->kvm->mmu_lock);
3106 make_mmu_pages_available(vcpu);
3107 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3108 i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL);
3109 root = __pa(sp->spt);
3111 spin_unlock(&vcpu->kvm->mmu_lock);
3112 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3114 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3121 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3123 struct kvm_mmu_page *sp;
3128 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3130 if (mmu_check_root(vcpu, root_gfn))
3134 * Do we shadow a long mode page table? If so we need to
3135 * write-protect the guests page table root.
3137 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3138 hpa_t root = vcpu->arch.mmu.root_hpa;
3140 MMU_WARN_ON(VALID_PAGE(root));
3142 spin_lock(&vcpu->kvm->mmu_lock);
3143 make_mmu_pages_available(vcpu);
3144 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3146 root = __pa(sp->spt);
3148 spin_unlock(&vcpu->kvm->mmu_lock);
3149 vcpu->arch.mmu.root_hpa = root;
3154 * We shadow a 32 bit page table. This may be a legacy 2-level
3155 * or a PAE 3-level page table. In either case we need to be aware that
3156 * the shadow page table may be a PAE or a long mode page table.
3158 pm_mask = PT_PRESENT_MASK;
3159 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3160 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3162 for (i = 0; i < 4; ++i) {
3163 hpa_t root = vcpu->arch.mmu.pae_root[i];
3165 MMU_WARN_ON(VALID_PAGE(root));
3166 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3167 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3168 if (!is_present_gpte(pdptr)) {
3169 vcpu->arch.mmu.pae_root[i] = 0;
3172 root_gfn = pdptr >> PAGE_SHIFT;
3173 if (mmu_check_root(vcpu, root_gfn))
3176 spin_lock(&vcpu->kvm->mmu_lock);
3177 make_mmu_pages_available(vcpu);
3178 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL,
3180 root = __pa(sp->spt);
3182 spin_unlock(&vcpu->kvm->mmu_lock);
3184 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3186 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3189 * If we shadow a 32 bit page table with a long mode page
3190 * table we enter this path.
3192 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3193 if (vcpu->arch.mmu.lm_root == NULL) {
3195 * The additional page necessary for this is only
3196 * allocated on demand.
3201 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3202 if (lm_root == NULL)
3205 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3207 vcpu->arch.mmu.lm_root = lm_root;
3210 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3216 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3218 if (vcpu->arch.mmu.direct_map)
3219 return mmu_alloc_direct_roots(vcpu);
3221 return mmu_alloc_shadow_roots(vcpu);
3224 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3227 struct kvm_mmu_page *sp;
3229 if (vcpu->arch.mmu.direct_map)
3232 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3235 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3236 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3237 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3238 hpa_t root = vcpu->arch.mmu.root_hpa;
3239 sp = page_header(root);
3240 mmu_sync_children(vcpu, sp);
3241 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3244 for (i = 0; i < 4; ++i) {
3245 hpa_t root = vcpu->arch.mmu.pae_root[i];
3247 if (root && VALID_PAGE(root)) {
3248 root &= PT64_BASE_ADDR_MASK;
3249 sp = page_header(root);
3250 mmu_sync_children(vcpu, sp);
3253 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3256 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3258 spin_lock(&vcpu->kvm->mmu_lock);
3259 mmu_sync_roots(vcpu);
3260 spin_unlock(&vcpu->kvm->mmu_lock);
3262 EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3264 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3265 u32 access, struct x86_exception *exception)
3268 exception->error_code = 0;
3272 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3274 struct x86_exception *exception)
3277 exception->error_code = 0;
3278 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3282 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3284 int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f;
3286 return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) |
3287 ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0);
3290 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3292 return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level);
3295 static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level)
3297 return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level);
3300 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3303 return vcpu_match_mmio_gpa(vcpu, addr);
3305 return vcpu_match_mmio_gva(vcpu, addr);
3308 /* return true if reserved bit is detected on spte. */
3310 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3312 struct kvm_shadow_walk_iterator iterator;
3313 u64 sptes[PT64_ROOT_LEVEL], spte = 0ull;
3315 bool reserved = false;
3317 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3320 walk_shadow_page_lockless_begin(vcpu);
3322 for (shadow_walk_init(&iterator, vcpu, addr),
3323 leaf = root = iterator.level;
3324 shadow_walk_okay(&iterator);
3325 __shadow_walk_next(&iterator, spte)) {
3326 spte = mmu_spte_get_lockless(iterator.sptep);
3328 sptes[leaf - 1] = spte;
3331 if (!is_shadow_present_pte(spte))
3334 reserved |= is_shadow_zero_bits_set(&vcpu->arch.mmu, spte,
3338 walk_shadow_page_lockless_end(vcpu);
3341 pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
3343 while (root > leaf) {
3344 pr_err("------ spte 0x%llx level %d.\n",
3345 sptes[root - 1], root);
3354 int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3359 if (mmio_info_in_cache(vcpu, addr, direct))
3360 return RET_MMIO_PF_EMULATE;
3362 reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte);
3363 if (WARN_ON(reserved))
3364 return RET_MMIO_PF_BUG;
3366 if (is_mmio_spte(spte)) {
3367 gfn_t gfn = get_mmio_spte_gfn(spte);
3368 unsigned access = get_mmio_spte_access(spte);
3370 if (!check_mmio_spte(vcpu, spte))
3371 return RET_MMIO_PF_INVALID;
3376 trace_handle_mmio_page_fault(addr, gfn, access);
3377 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3378 return RET_MMIO_PF_EMULATE;
3382 * If the page table is zapped by other cpus, let CPU fault again on
3385 return RET_MMIO_PF_RETRY;
3387 EXPORT_SYMBOL_GPL(handle_mmio_page_fault);
3389 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3390 u32 error_code, gfn_t gfn)
3392 if (unlikely(error_code & PFERR_RSVD_MASK))
3395 if (!(error_code & PFERR_PRESENT_MASK) ||
3396 !(error_code & PFERR_WRITE_MASK))
3400 * guest is writing the page which is write tracked which can
3401 * not be fixed by page fault handler.
3403 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3409 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3410 u32 error_code, bool prefault)
3412 gfn_t gfn = gva >> PAGE_SHIFT;
3415 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3417 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3420 r = mmu_topup_memory_caches(vcpu);
3424 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3427 return nonpaging_map(vcpu, gva & PAGE_MASK,
3428 error_code, gfn, prefault);
3431 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3433 struct kvm_arch_async_pf arch;
3435 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3437 arch.direct_map = vcpu->arch.mmu.direct_map;
3438 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3440 return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3443 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3445 if (unlikely(!lapic_in_kernel(vcpu) ||
3446 kvm_event_needs_reinjection(vcpu)))
3449 return kvm_x86_ops->interrupt_allowed(vcpu);
3452 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3453 gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable)
3455 struct kvm_memory_slot *slot;
3458 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3460 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable);
3462 return false; /* *pfn has correct page already */
3464 if (!prefault && can_do_async_pf(vcpu)) {
3465 trace_kvm_try_async_get_page(gva, gfn);
3466 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3467 trace_kvm_async_pf_doublefault(gva, gfn);
3468 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3470 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3474 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable);
3479 check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level)
3481 int page_num = KVM_PAGES_PER_HPAGE(level);
3483 gfn &= ~(page_num - 1);
3485 return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num);
3488 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3494 bool force_pt_level;
3495 gfn_t gfn = gpa >> PAGE_SHIFT;
3496 unsigned long mmu_seq;
3497 int write = error_code & PFERR_WRITE_MASK;
3500 MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3502 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3505 r = mmu_topup_memory_caches(vcpu);
3509 force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn,
3510 PT_DIRECTORY_LEVEL);
3511 level = mapping_level(vcpu, gfn, &force_pt_level);
3512 if (likely(!force_pt_level)) {
3513 if (level > PT_DIRECTORY_LEVEL &&
3514 !check_hugepage_cache_consistency(vcpu, gfn, level))
3515 level = PT_DIRECTORY_LEVEL;
3516 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3519 if (fast_page_fault(vcpu, gpa, level, error_code))
3522 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3525 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3528 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3531 spin_lock(&vcpu->kvm->mmu_lock);
3532 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3534 make_mmu_pages_available(vcpu);
3535 if (likely(!force_pt_level))
3536 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3537 r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault);
3538 spin_unlock(&vcpu->kvm->mmu_lock);
3543 spin_unlock(&vcpu->kvm->mmu_lock);
3544 kvm_release_pfn_clean(pfn);
3548 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3549 struct kvm_mmu *context)
3551 context->page_fault = nonpaging_page_fault;
3552 context->gva_to_gpa = nonpaging_gva_to_gpa;
3553 context->sync_page = nonpaging_sync_page;
3554 context->invlpg = nonpaging_invlpg;
3555 context->update_pte = nonpaging_update_pte;
3556 context->root_level = 0;
3557 context->shadow_root_level = PT32E_ROOT_LEVEL;
3558 context->root_hpa = INVALID_PAGE;
3559 context->direct_map = true;
3560 context->nx = false;
3563 void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3565 mmu_free_roots(vcpu);
3568 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3570 return kvm_read_cr3(vcpu);
3573 static void inject_page_fault(struct kvm_vcpu *vcpu,
3574 struct x86_exception *fault)
3576 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3579 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
3580 unsigned access, int *nr_present)
3582 if (unlikely(is_mmio_spte(*sptep))) {
3583 if (gfn != get_mmio_spte_gfn(*sptep)) {
3584 mmu_spte_clear_no_track(sptep);
3589 mark_mmio_spte(vcpu, sptep, gfn, access);
3596 static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3601 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3602 return mmu->last_pte_bitmap & (1 << index);
3605 #define PTTYPE_EPT 18 /* arbitrary */
3606 #define PTTYPE PTTYPE_EPT
3607 #include "paging_tmpl.h"
3611 #include "paging_tmpl.h"
3615 #include "paging_tmpl.h"
3619 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3620 struct rsvd_bits_validate *rsvd_check,
3621 int maxphyaddr, int level, bool nx, bool gbpages,
3624 u64 exb_bit_rsvd = 0;
3625 u64 gbpages_bit_rsvd = 0;
3626 u64 nonleaf_bit8_rsvd = 0;
3628 rsvd_check->bad_mt_xwr = 0;
3631 exb_bit_rsvd = rsvd_bits(63, 63);
3633 gbpages_bit_rsvd = rsvd_bits(7, 7);
3636 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
3637 * leaf entries) on AMD CPUs only.
3640 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
3643 case PT32_ROOT_LEVEL:
3644 /* no rsvd bits for 2 level 4K page table entries */
3645 rsvd_check->rsvd_bits_mask[0][1] = 0;
3646 rsvd_check->rsvd_bits_mask[0][0] = 0;
3647 rsvd_check->rsvd_bits_mask[1][0] =
3648 rsvd_check->rsvd_bits_mask[0][0];
3651 rsvd_check->rsvd_bits_mask[1][1] = 0;
3655 if (is_cpuid_PSE36())
3656 /* 36bits PSE 4MB page */
3657 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3659 /* 32 bits PSE 4MB page */
3660 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3662 case PT32E_ROOT_LEVEL:
3663 rsvd_check->rsvd_bits_mask[0][2] =
3664 rsvd_bits(maxphyaddr, 63) |
3665 rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */
3666 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3667 rsvd_bits(maxphyaddr, 62); /* PDE */
3668 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3669 rsvd_bits(maxphyaddr, 62); /* PTE */
3670 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3671 rsvd_bits(maxphyaddr, 62) |
3672 rsvd_bits(13, 20); /* large page */
3673 rsvd_check->rsvd_bits_mask[1][0] =
3674 rsvd_check->rsvd_bits_mask[0][0];
3676 case PT64_ROOT_LEVEL:
3677 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3678 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
3679 rsvd_bits(maxphyaddr, 51);
3680 rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3681 nonleaf_bit8_rsvd | gbpages_bit_rsvd |
3682 rsvd_bits(maxphyaddr, 51);
3683 rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3684 rsvd_bits(maxphyaddr, 51);
3685 rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3686 rsvd_bits(maxphyaddr, 51);
3687 rsvd_check->rsvd_bits_mask[1][3] =
3688 rsvd_check->rsvd_bits_mask[0][3];
3689 rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3690 gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) |
3692 rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3693 rsvd_bits(maxphyaddr, 51) |
3694 rsvd_bits(13, 20); /* large page */
3695 rsvd_check->rsvd_bits_mask[1][0] =
3696 rsvd_check->rsvd_bits_mask[0][0];
3701 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3702 struct kvm_mmu *context)
3704 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
3705 cpuid_maxphyaddr(vcpu), context->root_level,
3706 context->nx, guest_cpuid_has_gbpages(vcpu),
3707 is_pse(vcpu), guest_cpuid_is_amd(vcpu));
3711 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
3712 int maxphyaddr, bool execonly)
3716 rsvd_check->rsvd_bits_mask[0][3] =
3717 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3718 rsvd_check->rsvd_bits_mask[0][2] =
3719 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3720 rsvd_check->rsvd_bits_mask[0][1] =
3721 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3722 rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3725 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
3726 rsvd_check->rsvd_bits_mask[1][2] =
3727 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3728 rsvd_check->rsvd_bits_mask[1][1] =
3729 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3730 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
3732 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
3733 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
3734 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
3735 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
3736 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
3738 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
3739 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
3741 rsvd_check->bad_mt_xwr = bad_mt_xwr;
3744 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3745 struct kvm_mmu *context, bool execonly)
3747 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
3748 cpuid_maxphyaddr(vcpu), execonly);
3752 * the page table on host is the shadow page table for the page
3753 * table in guest or amd nested guest, its mmu features completely
3754 * follow the features in guest.
3757 reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3760 * Passing "true" to the last argument is okay; it adds a check
3761 * on bit 8 of the SPTEs which KVM doesn't use anyway.
3763 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3764 boot_cpu_data.x86_phys_bits,
3765 context->shadow_root_level, context->nx,
3766 guest_cpuid_has_gbpages(vcpu), is_pse(vcpu),
3769 EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask);
3771 static inline bool boot_cpu_is_amd(void)
3773 WARN_ON_ONCE(!tdp_enabled);
3774 return shadow_x_mask == 0;
3778 * the direct page table on host, use as much mmu features as
3779 * possible, however, kvm currently does not do execution-protection.
3782 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3783 struct kvm_mmu *context)
3785 if (boot_cpu_is_amd())
3786 __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
3787 boot_cpu_data.x86_phys_bits,
3788 context->shadow_root_level, false,
3789 cpu_has_gbpages, true, true);
3791 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3792 boot_cpu_data.x86_phys_bits,
3798 * as the comments in reset_shadow_zero_bits_mask() except it
3799 * is the shadow page table for intel nested guest.
3802 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
3803 struct kvm_mmu *context, bool execonly)
3805 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
3806 boot_cpu_data.x86_phys_bits, execonly);
3809 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
3810 struct kvm_mmu *mmu, bool ept)
3812 unsigned bit, byte, pfec;
3814 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3816 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3817 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3818 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3821 wf = pfec & PFERR_WRITE_MASK;
3822 uf = pfec & PFERR_USER_MASK;
3823 ff = pfec & PFERR_FETCH_MASK;
3825 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3826 * subject to SMAP restrictions, and cleared otherwise. The
3827 * bit is only meaningful if the SMAP bit is set in CR4.
3829 smapf = !(pfec & PFERR_RSVD_MASK);
3830 for (bit = 0; bit < 8; ++bit) {
3831 x = bit & ACC_EXEC_MASK;
3832 w = bit & ACC_WRITE_MASK;
3833 u = bit & ACC_USER_MASK;
3836 /* Not really needed: !nx will cause pte.nx to fault */
3838 /* Allow supervisor writes if !cr0.wp */
3839 w |= !is_write_protection(vcpu) && !uf;
3840 /* Disallow supervisor fetches of user code if cr4.smep */
3841 x &= !(cr4_smep && u && !uf);
3844 * SMAP:kernel-mode data accesses from user-mode
3845 * mappings should fault. A fault is considered
3846 * as a SMAP violation if all of the following
3847 * conditions are ture:
3848 * - X86_CR4_SMAP is set in CR4
3849 * - An user page is accessed
3850 * - Page fault in kernel mode
3851 * - if CPL = 3 or X86_EFLAGS_AC is clear
3853 * Here, we cover the first three conditions.
3854 * The fourth is computed dynamically in
3855 * permission_fault() and is in smapf.
3857 * Also, SMAP does not affect instruction
3858 * fetches, add the !ff check here to make it
3861 smap = cr4_smap && u && !uf && !ff;
3863 /* Not really needed: no U/S accesses on ept */
3866 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3868 map |= fault << bit;
3870 mmu->permissions[byte] = map;
3874 static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3877 unsigned level, root_level = mmu->root_level;
3878 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3880 if (root_level == PT32E_ROOT_LEVEL)
3882 /* PT_PAGE_TABLE_LEVEL always terminates */
3883 map = 1 | (1 << ps_set_index);
3884 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3885 if (level <= PT_PDPE_LEVEL
3886 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3887 map |= 1 << (ps_set_index | (level - 1));
3889 mmu->last_pte_bitmap = map;
3892 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3893 struct kvm_mmu *context,
3896 context->nx = is_nx(vcpu);
3897 context->root_level = level;
3899 reset_rsvds_bits_mask(vcpu, context);
3900 update_permission_bitmask(vcpu, context, false);
3901 update_last_pte_bitmap(vcpu, context);
3903 MMU_WARN_ON(!is_pae(vcpu));
3904 context->page_fault = paging64_page_fault;
3905 context->gva_to_gpa = paging64_gva_to_gpa;
3906 context->sync_page = paging64_sync_page;
3907 context->invlpg = paging64_invlpg;
3908 context->update_pte = paging64_update_pte;
3909 context->shadow_root_level = level;
3910 context->root_hpa = INVALID_PAGE;
3911 context->direct_map = false;
3914 static void paging64_init_context(struct kvm_vcpu *vcpu,
3915 struct kvm_mmu *context)
3917 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3920 static void paging32_init_context(struct kvm_vcpu *vcpu,
3921 struct kvm_mmu *context)
3923 context->nx = false;
3924 context->root_level = PT32_ROOT_LEVEL;
3926 reset_rsvds_bits_mask(vcpu, context);
3927 update_permission_bitmask(vcpu, context, false);
3928 update_last_pte_bitmap(vcpu, context);
3930 context->page_fault = paging32_page_fault;
3931 context->gva_to_gpa = paging32_gva_to_gpa;
3932 context->sync_page = paging32_sync_page;
3933 context->invlpg = paging32_invlpg;
3934 context->update_pte = paging32_update_pte;
3935 context->shadow_root_level = PT32E_ROOT_LEVEL;
3936 context->root_hpa = INVALID_PAGE;
3937 context->direct_map = false;
3940 static void paging32E_init_context(struct kvm_vcpu *vcpu,
3941 struct kvm_mmu *context)
3943 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3946 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3948 struct kvm_mmu *context = &vcpu->arch.mmu;
3950 context->base_role.word = 0;
3951 context->base_role.smm = is_smm(vcpu);
3952 context->page_fault = tdp_page_fault;
3953 context->sync_page = nonpaging_sync_page;
3954 context->invlpg = nonpaging_invlpg;
3955 context->update_pte = nonpaging_update_pte;
3956 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3957 context->root_hpa = INVALID_PAGE;
3958 context->direct_map = true;
3959 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3960 context->get_cr3 = get_cr3;
3961 context->get_pdptr = kvm_pdptr_read;
3962 context->inject_page_fault = kvm_inject_page_fault;
3964 if (!is_paging(vcpu)) {
3965 context->nx = false;
3966 context->gva_to_gpa = nonpaging_gva_to_gpa;
3967 context->root_level = 0;
3968 } else if (is_long_mode(vcpu)) {
3969 context->nx = is_nx(vcpu);
3970 context->root_level = PT64_ROOT_LEVEL;
3971 reset_rsvds_bits_mask(vcpu, context);
3972 context->gva_to_gpa = paging64_gva_to_gpa;
3973 } else if (is_pae(vcpu)) {
3974 context->nx = is_nx(vcpu);
3975 context->root_level = PT32E_ROOT_LEVEL;
3976 reset_rsvds_bits_mask(vcpu, context);
3977 context->gva_to_gpa = paging64_gva_to_gpa;
3979 context->nx = false;
3980 context->root_level = PT32_ROOT_LEVEL;
3981 reset_rsvds_bits_mask(vcpu, context);
3982 context->gva_to_gpa = paging32_gva_to_gpa;
3985 update_permission_bitmask(vcpu, context, false);
3986 update_last_pte_bitmap(vcpu, context);
3987 reset_tdp_shadow_zero_bits_mask(vcpu, context);
3990 void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu)
3992 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3993 bool smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3994 struct kvm_mmu *context = &vcpu->arch.mmu;
3996 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
3998 if (!is_paging(vcpu))
3999 nonpaging_init_context(vcpu, context);
4000 else if (is_long_mode(vcpu))
4001 paging64_init_context(vcpu, context);
4002 else if (is_pae(vcpu))
4003 paging32E_init_context(vcpu, context);
4005 paging32_init_context(vcpu, context);
4007 context->base_role.nxe = is_nx(vcpu);
4008 context->base_role.cr4_pae = !!is_pae(vcpu);
4009 context->base_role.cr0_wp = is_write_protection(vcpu);
4010 context->base_role.smep_andnot_wp
4011 = smep && !is_write_protection(vcpu);
4012 context->base_role.smap_andnot_wp
4013 = smap && !is_write_protection(vcpu);
4014 context->base_role.smm = is_smm(vcpu);
4015 reset_shadow_zero_bits_mask(vcpu, context);
4017 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
4019 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly)
4021 struct kvm_mmu *context = &vcpu->arch.mmu;
4023 MMU_WARN_ON(VALID_PAGE(context->root_hpa));
4025 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
4028 context->page_fault = ept_page_fault;
4029 context->gva_to_gpa = ept_gva_to_gpa;
4030 context->sync_page = ept_sync_page;
4031 context->invlpg = ept_invlpg;
4032 context->update_pte = ept_update_pte;
4033 context->root_level = context->shadow_root_level;
4034 context->root_hpa = INVALID_PAGE;
4035 context->direct_map = false;
4037 update_permission_bitmask(vcpu, context, true);
4038 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4039 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4041 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4043 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4045 struct kvm_mmu *context = &vcpu->arch.mmu;
4047 kvm_init_shadow_mmu(vcpu);
4048 context->set_cr3 = kvm_x86_ops->set_cr3;
4049 context->get_cr3 = get_cr3;
4050 context->get_pdptr = kvm_pdptr_read;
4051 context->inject_page_fault = kvm_inject_page_fault;
4054 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4056 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4058 g_context->get_cr3 = get_cr3;
4059 g_context->get_pdptr = kvm_pdptr_read;
4060 g_context->inject_page_fault = kvm_inject_page_fault;
4063 * Note that arch.mmu.gva_to_gpa translates l2_gpa to l1_gpa using
4064 * L1's nested page tables (e.g. EPT12). The nested translation
4065 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4066 * L2's page tables as the first level of translation and L1's
4067 * nested page tables as the second level of translation. Basically
4068 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4070 if (!is_paging(vcpu)) {
4071 g_context->nx = false;
4072 g_context->root_level = 0;
4073 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4074 } else if (is_long_mode(vcpu)) {
4075 g_context->nx = is_nx(vcpu);
4076 g_context->root_level = PT64_ROOT_LEVEL;
4077 reset_rsvds_bits_mask(vcpu, g_context);
4078 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4079 } else if (is_pae(vcpu)) {
4080 g_context->nx = is_nx(vcpu);
4081 g_context->root_level = PT32E_ROOT_LEVEL;
4082 reset_rsvds_bits_mask(vcpu, g_context);
4083 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4085 g_context->nx = false;
4086 g_context->root_level = PT32_ROOT_LEVEL;
4087 reset_rsvds_bits_mask(vcpu, g_context);
4088 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4091 update_permission_bitmask(vcpu, g_context, false);
4092 update_last_pte_bitmap(vcpu, g_context);
4095 static void init_kvm_mmu(struct kvm_vcpu *vcpu)
4097 if (mmu_is_nested(vcpu))
4098 init_kvm_nested_mmu(vcpu);
4099 else if (tdp_enabled)
4100 init_kvm_tdp_mmu(vcpu);
4102 init_kvm_softmmu(vcpu);
4105 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4107 kvm_mmu_unload(vcpu);
4110 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4112 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4116 r = mmu_topup_memory_caches(vcpu);
4119 r = mmu_alloc_roots(vcpu);
4120 kvm_mmu_sync_roots(vcpu);
4123 /* set_cr3() should ensure TLB has been flushed */
4124 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
4128 EXPORT_SYMBOL_GPL(kvm_mmu_load);
4130 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4132 mmu_free_roots(vcpu);
4133 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4135 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
4137 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
4138 struct kvm_mmu_page *sp, u64 *spte,
4141 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
4142 ++vcpu->kvm->stat.mmu_pde_zapped;
4146 ++vcpu->kvm->stat.mmu_pte_updated;
4147 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
4150 static bool need_remote_flush(u64 old, u64 new)
4152 if (!is_shadow_present_pte(old))
4154 if (!is_shadow_present_pte(new))
4156 if ((old ^ new) & PT64_BASE_ADDR_MASK)
4158 old ^= shadow_nx_mask;
4159 new ^= shadow_nx_mask;
4160 return (old & ~new & PT64_PERM_MASK) != 0;
4163 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
4164 bool remote_flush, bool local_flush)
4170 kvm_flush_remote_tlbs(vcpu->kvm);
4171 else if (local_flush)
4172 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4175 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
4176 const u8 *new, int *bytes)
4182 * Assume that the pte write on a page table of the same type
4183 * as the current vcpu paging mode since we update the sptes only
4184 * when they have the same mode.
4186 if (is_pae(vcpu) && *bytes == 4) {
4187 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
4190 r = kvm_vcpu_read_guest(vcpu, *gpa, &gentry, 8);
4193 new = (const u8 *)&gentry;
4198 gentry = *(const u32 *)new;
4201 gentry = *(const u64 *)new;
4212 * If we're seeing too many writes to a page, it may no longer be a page table,
4213 * or we may be forking, in which case it is better to unmap the page.
4215 static bool detect_write_flooding(struct kvm_mmu_page *sp)
4218 * Skip write-flooding detected for the sp whose level is 1, because
4219 * it can become unsync, then the guest page is not write-protected.
4221 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4224 return ++sp->write_flooding_count >= 3;
4228 * Misaligned accesses are too much trouble to fix up; also, they usually
4229 * indicate a page is not used as a page table.
4231 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4234 unsigned offset, pte_size, misaligned;
4236 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4237 gpa, bytes, sp->role.word);
4239 offset = offset_in_page(gpa);
4240 pte_size = sp->role.cr4_pae ? 8 : 4;
4243 * Sometimes, the OS only writes the last one bytes to update status
4244 * bits, for example, in linux, andb instruction is used in clear_bit().
4246 if (!(offset & (pte_size - 1)) && bytes == 1)
4249 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4250 misaligned |= bytes < 4;
4255 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4257 unsigned page_offset, quadrant;
4261 page_offset = offset_in_page(gpa);
4262 level = sp->role.level;
4264 if (!sp->role.cr4_pae) {
4265 page_offset <<= 1; /* 32->64 */
4267 * A 32-bit pde maps 4MB while the shadow pdes map
4268 * only 2MB. So we need to double the offset again
4269 * and zap two pdes instead of one.
4271 if (level == PT32_ROOT_LEVEL) {
4272 page_offset &= ~7; /* kill rounding error */
4276 quadrant = page_offset >> PAGE_SHIFT;
4277 page_offset &= ~PAGE_MASK;
4278 if (quadrant != sp->role.quadrant)
4282 spte = &sp->spt[page_offset / sizeof(*spte)];
4286 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4287 const u8 *new, int bytes)
4289 gfn_t gfn = gpa >> PAGE_SHIFT;
4290 struct kvm_mmu_page *sp;
4291 LIST_HEAD(invalid_list);
4292 u64 entry, gentry, *spte;
4294 bool remote_flush, local_flush, zap_page;
4295 union kvm_mmu_page_role mask = { };
4300 mask.smep_andnot_wp = 1;
4301 mask.smap_andnot_wp = 1;
4305 * If we don't have indirect shadow pages, it means no page is
4306 * write-protected, so we can exit simply.
4308 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4311 zap_page = remote_flush = local_flush = false;
4313 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4315 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4318 * No need to care whether allocation memory is successful
4319 * or not since pte prefetch is skiped if it does not have
4320 * enough objects in the cache.
4322 mmu_topup_memory_caches(vcpu);
4324 spin_lock(&vcpu->kvm->mmu_lock);
4325 ++vcpu->kvm->stat.mmu_pte_write;
4326 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4328 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4329 if (detect_write_misaligned(sp, gpa, bytes) ||
4330 detect_write_flooding(sp)) {
4331 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4333 ++vcpu->kvm->stat.mmu_flooded;
4337 spte = get_written_sptes(sp, gpa, &npte);
4344 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4346 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4347 & mask.word) && rmap_can_add(vcpu))
4348 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4349 if (need_remote_flush(entry, *spte))
4350 remote_flush = true;
4354 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4355 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4356 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4357 spin_unlock(&vcpu->kvm->mmu_lock);
4360 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4365 if (vcpu->arch.mmu.direct_map)
4368 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4370 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4374 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4376 static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4378 LIST_HEAD(invalid_list);
4380 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4383 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4384 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4387 ++vcpu->kvm->stat.mmu_recycled;
4389 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4392 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4393 void *insn, int insn_len)
4395 int r, emulation_type = EMULTYPE_RETRY;
4396 enum emulation_result er;
4397 bool direct = vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu);
4399 if (unlikely(error_code & PFERR_RSVD_MASK)) {
4400 r = handle_mmio_page_fault(vcpu, cr2, direct);
4401 if (r == RET_MMIO_PF_EMULATE) {
4405 if (r == RET_MMIO_PF_RETRY)
4411 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4417 if (mmio_info_in_cache(vcpu, cr2, direct))
4420 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4425 case EMULATE_USER_EXIT:
4426 ++vcpu->stat.mmio_exits;
4434 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4436 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4438 vcpu->arch.mmu.invlpg(vcpu, gva);
4439 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
4440 ++vcpu->stat.invlpg;
4442 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4444 void kvm_enable_tdp(void)
4448 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4450 void kvm_disable_tdp(void)
4452 tdp_enabled = false;
4454 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4456 static void free_mmu_pages(struct kvm_vcpu *vcpu)
4458 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4459 if (vcpu->arch.mmu.lm_root != NULL)
4460 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4463 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4469 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4470 * Therefore we need to allocate shadow page tables in the first
4471 * 4GB of memory, which happens to fit the DMA32 zone.
4473 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4477 vcpu->arch.mmu.pae_root = page_address(page);
4478 for (i = 0; i < 4; ++i)
4479 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4484 int kvm_mmu_create(struct kvm_vcpu *vcpu)
4486 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4487 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4488 vcpu->arch.mmu.translate_gpa = translate_gpa;
4489 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4491 return alloc_mmu_pages(vcpu);
4494 void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4496 MMU_WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
4501 /* The return value indicates if tlb flush on all vcpus is needed. */
4502 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head);
4504 /* The caller should hold mmu-lock before calling this function. */
4506 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
4507 slot_level_handler fn, int start_level, int end_level,
4508 gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb)
4510 struct slot_rmap_walk_iterator iterator;
4513 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
4514 end_gfn, &iterator) {
4516 flush |= fn(kvm, iterator.rmap);
4518 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4519 if (flush && lock_flush_tlb) {
4520 kvm_flush_remote_tlbs(kvm);
4523 cond_resched_lock(&kvm->mmu_lock);
4527 if (flush && lock_flush_tlb) {
4528 kvm_flush_remote_tlbs(kvm);
4536 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4537 slot_level_handler fn, int start_level, int end_level,
4538 bool lock_flush_tlb)
4540 return slot_handle_level_range(kvm, memslot, fn, start_level,
4541 end_level, memslot->base_gfn,
4542 memslot->base_gfn + memslot->npages - 1,
4547 slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4548 slot_level_handler fn, bool lock_flush_tlb)
4550 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4551 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4555 slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
4556 slot_level_handler fn, bool lock_flush_tlb)
4558 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1,
4559 PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb);
4563 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
4564 slot_level_handler fn, bool lock_flush_tlb)
4566 return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL,
4567 PT_PAGE_TABLE_LEVEL, lock_flush_tlb);
4570 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
4572 struct kvm_memslots *slots;
4573 struct kvm_memory_slot *memslot;
4576 spin_lock(&kvm->mmu_lock);
4577 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4578 slots = __kvm_memslots(kvm, i);
4579 kvm_for_each_memslot(memslot, slots) {
4582 start = max(gfn_start, memslot->base_gfn);
4583 end = min(gfn_end, memslot->base_gfn + memslot->npages);
4587 slot_handle_level_range(kvm, memslot, kvm_zap_rmapp,
4588 PT_PAGE_TABLE_LEVEL, PT_MAX_HUGEPAGE_LEVEL,
4589 start, end - 1, true);
4593 spin_unlock(&kvm->mmu_lock);
4596 static bool slot_rmap_write_protect(struct kvm *kvm,
4597 struct kvm_rmap_head *rmap_head)
4599 return __rmap_write_protect(kvm, rmap_head, false);
4602 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
4603 struct kvm_memory_slot *memslot)
4607 spin_lock(&kvm->mmu_lock);
4608 flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect,
4610 spin_unlock(&kvm->mmu_lock);
4613 * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log()
4614 * which do tlb flush out of mmu-lock should be serialized by
4615 * kvm->slots_lock otherwise tlb flush would be missed.
4617 lockdep_assert_held(&kvm->slots_lock);
4620 * We can flush all the TLBs out of the mmu lock without TLB
4621 * corruption since we just change the spte from writable to
4622 * readonly so that we only need to care the case of changing
4623 * spte from present to present (changing the spte from present
4624 * to nonpresent will flush all the TLBs immediately), in other
4625 * words, the only case we care is mmu_spte_update() where we
4626 * haved checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE
4627 * instead of PT_WRITABLE_MASK, that means it does not depend
4628 * on PT_WRITABLE_MASK anymore.
4631 kvm_flush_remote_tlbs(kvm);
4634 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
4635 struct kvm_rmap_head *rmap_head)
4638 struct rmap_iterator iter;
4639 int need_tlb_flush = 0;
4641 struct kvm_mmu_page *sp;
4644 for_each_rmap_spte(rmap_head, &iter, sptep) {
4645 sp = page_header(__pa(sptep));
4646 pfn = spte_to_pfn(*sptep);
4649 * We cannot do huge page mapping for indirect shadow pages,
4650 * which are found on the last rmap (level = 1) when not using
4651 * tdp; such shadow pages are synced with the page table in
4652 * the guest, and the guest page table is using 4K page size
4653 * mapping if the indirect sp has level = 1.
4655 if (sp->role.direct &&
4656 !kvm_is_reserved_pfn(pfn) &&
4657 PageTransCompound(pfn_to_page(pfn))) {
4658 drop_spte(kvm, sptep);
4664 return need_tlb_flush;
4667 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
4668 const struct kvm_memory_slot *memslot)
4670 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
4671 spin_lock(&kvm->mmu_lock);
4672 slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot,
4673 kvm_mmu_zap_collapsible_spte, true);
4674 spin_unlock(&kvm->mmu_lock);
4677 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
4678 struct kvm_memory_slot *memslot)
4682 spin_lock(&kvm->mmu_lock);
4683 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false);
4684 spin_unlock(&kvm->mmu_lock);
4686 lockdep_assert_held(&kvm->slots_lock);
4689 * It's also safe to flush TLBs out of mmu lock here as currently this
4690 * function is only used for dirty logging, in which case flushing TLB
4691 * out of mmu lock also guarantees no dirty pages will be lost in
4695 kvm_flush_remote_tlbs(kvm);
4697 EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty);
4699 void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
4700 struct kvm_memory_slot *memslot)
4704 spin_lock(&kvm->mmu_lock);
4705 flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect,
4707 spin_unlock(&kvm->mmu_lock);
4709 /* see kvm_mmu_slot_remove_write_access */
4710 lockdep_assert_held(&kvm->slots_lock);
4713 kvm_flush_remote_tlbs(kvm);
4715 EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access);
4717 void kvm_mmu_slot_set_dirty(struct kvm *kvm,
4718 struct kvm_memory_slot *memslot)
4722 spin_lock(&kvm->mmu_lock);
4723 flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false);
4724 spin_unlock(&kvm->mmu_lock);
4726 lockdep_assert_held(&kvm->slots_lock);
4728 /* see kvm_mmu_slot_leaf_clear_dirty */
4730 kvm_flush_remote_tlbs(kvm);
4732 EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty);
4734 #define BATCH_ZAP_PAGES 10
4735 static void kvm_zap_obsolete_pages(struct kvm *kvm)
4737 struct kvm_mmu_page *sp, *node;
4741 list_for_each_entry_safe_reverse(sp, node,
4742 &kvm->arch.active_mmu_pages, link) {
4746 * No obsolete page exists before new created page since
4747 * active_mmu_pages is the FIFO list.
4749 if (!is_obsolete_sp(kvm, sp))
4753 * Since we are reversely walking the list and the invalid
4754 * list will be moved to the head, skip the invalid page
4755 * can help us to avoid the infinity list walking.
4757 if (sp->role.invalid)
4761 * Need not flush tlb since we only zap the sp with invalid
4762 * generation number.
4764 if (batch >= BATCH_ZAP_PAGES &&
4765 cond_resched_lock(&kvm->mmu_lock)) {
4770 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4771 &kvm->arch.zapped_obsolete_pages);
4779 * Should flush tlb before free page tables since lockless-walking
4780 * may use the pages.
4782 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4786 * Fast invalidate all shadow pages and use lock-break technique
4787 * to zap obsolete pages.
4789 * It's required when memslot is being deleted or VM is being
4790 * destroyed, in these cases, we should ensure that KVM MMU does
4791 * not use any resource of the being-deleted slot or all slots
4792 * after calling the function.
4794 void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4796 spin_lock(&kvm->mmu_lock);
4797 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4798 kvm->arch.mmu_valid_gen++;
4801 * Notify all vcpus to reload its shadow page table
4802 * and flush TLB. Then all vcpus will switch to new
4803 * shadow page table with the new mmu_valid_gen.
4805 * Note: we should do this under the protection of
4806 * mmu-lock, otherwise, vcpu would purge shadow page
4807 * but miss tlb flush.
4809 kvm_reload_remote_mmus(kvm);
4811 kvm_zap_obsolete_pages(kvm);
4812 spin_unlock(&kvm->mmu_lock);
4815 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4817 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4820 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots)
4823 * The very rare case: if the generation-number is round,
4824 * zap all shadow pages.
4826 if (unlikely((slots->generation & MMIO_GEN_MASK) == 0)) {
4827 printk_ratelimited(KERN_DEBUG "kvm: zapping shadow pages for mmio generation wraparound\n");
4828 kvm_mmu_invalidate_zap_all_pages(kvm);
4832 static unsigned long
4833 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4836 int nr_to_scan = sc->nr_to_scan;
4837 unsigned long freed = 0;
4839 spin_lock(&kvm_lock);
4841 list_for_each_entry(kvm, &vm_list, vm_list) {
4843 LIST_HEAD(invalid_list);
4846 * Never scan more than sc->nr_to_scan VM instances.
4847 * Will not hit this condition practically since we do not try
4848 * to shrink more than one VM and it is very unlikely to see
4849 * !n_used_mmu_pages so many times.
4854 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4855 * here. We may skip a VM instance errorneosly, but we do not
4856 * want to shrink a VM that only started to populate its MMU
4859 if (!kvm->arch.n_used_mmu_pages &&
4860 !kvm_has_zapped_obsolete_pages(kvm))
4863 idx = srcu_read_lock(&kvm->srcu);
4864 spin_lock(&kvm->mmu_lock);
4866 if (kvm_has_zapped_obsolete_pages(kvm)) {
4867 kvm_mmu_commit_zap_page(kvm,
4868 &kvm->arch.zapped_obsolete_pages);
4872 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
4874 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4877 spin_unlock(&kvm->mmu_lock);
4878 srcu_read_unlock(&kvm->srcu, idx);
4881 * unfair on small ones
4882 * per-vm shrinkers cry out
4883 * sadness comes quickly
4885 list_move_tail(&kvm->vm_list, &vm_list);
4889 spin_unlock(&kvm_lock);
4893 static unsigned long
4894 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
4896 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4899 static struct shrinker mmu_shrinker = {
4900 .count_objects = mmu_shrink_count,
4901 .scan_objects = mmu_shrink_scan,
4902 .seeks = DEFAULT_SEEKS * 10,
4905 static void mmu_destroy_caches(void)
4907 if (pte_list_desc_cache)
4908 kmem_cache_destroy(pte_list_desc_cache);
4909 if (mmu_page_header_cache)
4910 kmem_cache_destroy(mmu_page_header_cache);
4913 int kvm_mmu_module_init(void)
4915 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4916 sizeof(struct pte_list_desc),
4918 if (!pte_list_desc_cache)
4921 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4922 sizeof(struct kvm_mmu_page),
4924 if (!mmu_page_header_cache)
4927 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
4930 register_shrinker(&mmu_shrinker);
4935 mmu_destroy_caches();
4940 * Caculate mmu pages needed for kvm.
4942 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4944 unsigned int nr_mmu_pages;
4945 unsigned int nr_pages = 0;
4946 struct kvm_memslots *slots;
4947 struct kvm_memory_slot *memslot;
4950 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
4951 slots = __kvm_memslots(kvm, i);
4953 kvm_for_each_memslot(memslot, slots)
4954 nr_pages += memslot->npages;
4957 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4958 nr_mmu_pages = max(nr_mmu_pages,
4959 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4961 return nr_mmu_pages;
4964 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4966 kvm_mmu_unload(vcpu);
4967 free_mmu_pages(vcpu);
4968 mmu_free_memory_caches(vcpu);
4971 void kvm_mmu_module_exit(void)
4973 mmu_destroy_caches();
4974 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4975 unregister_shrinker(&mmu_shrinker);
4976 mmu_audit_disable();