2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
37 #define PT_MAX_FULL_LEVELS 4
38 #define CMPXCHG cmpxchg
40 #define CMPXCHG cmpxchg64
41 #define PT_MAX_FULL_LEVELS 2
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
53 #define PT_MAX_FULL_LEVELS 2
54 #define CMPXCHG cmpxchg
56 #error Invalid PTTYPE value
59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
63 * The guest_walker structure emulates the behavior of the hardware page
68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
70 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
71 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
78 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
83 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
84 gfn_t table_gfn, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
91 page = gfn_to_page(kvm, table_gfn);
93 table = kmap_atomic(page, KM_USER0);
94 ret = CMPXCHG(&table[index], orig_pte, new_pte);
95 kunmap_atomic(table, KM_USER0);
97 kvm_release_page_dirty(page);
99 return (ret != orig_pte);
102 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
106 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
108 if (vcpu->arch.mmu.nx)
109 access &= ~(gpte >> PT64_NX_SHIFT);
115 * Fetch a guest pte for a guest virtual address
117 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
118 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
119 gva_t addr, u32 access)
123 unsigned index, pt_access, uninitialized_var(pte_access);
125 bool eperm, present, rsvd_fault;
126 int offset, write_fault, user_fault, fetch_fault;
128 write_fault = access & PFERR_WRITE_MASK;
129 user_fault = access & PFERR_USER_MASK;
130 fetch_fault = access & PFERR_FETCH_MASK;
132 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
136 eperm = rsvd_fault = false;
137 walker->level = mmu->root_level;
138 pte = mmu->get_cr3(vcpu);
141 if (walker->level == PT32E_ROOT_LEVEL) {
142 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
143 trace_kvm_mmu_paging_element(pte, walker->level);
144 if (!is_present_gpte(pte)) {
151 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
152 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
157 index = PT_INDEX(addr, walker->level);
159 table_gfn = gpte_to_gfn(pte);
160 offset = index * sizeof(pt_element_t);
161 pte_gpa = gfn_to_gpa(table_gfn) + offset;
162 walker->table_gfn[walker->level - 1] = table_gfn;
163 walker->pte_gpa[walker->level - 1] = pte_gpa;
165 if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte,
167 PFERR_USER_MASK|PFERR_WRITE_MASK)) {
172 trace_kvm_mmu_paging_element(pte, walker->level);
174 if (!is_present_gpte(pte)) {
179 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
184 if (write_fault && !is_writable_pte(pte))
185 if (user_fault || is_write_protection(vcpu))
188 if (user_fault && !(pte & PT_USER_MASK))
192 if (fetch_fault && (pte & PT64_NX_MASK))
196 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
197 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
199 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
200 index, pte, pte|PT_ACCESSED_MASK))
202 mark_page_dirty(vcpu->kvm, table_gfn);
203 pte |= PT_ACCESSED_MASK;
206 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
208 walker->ptes[walker->level - 1] = pte;
210 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
211 ((walker->level == PT_DIRECTORY_LEVEL) &&
213 (PTTYPE == 64 || is_pse(vcpu))) ||
214 ((walker->level == PT_PDPE_LEVEL) &&
216 mmu->root_level == PT64_ROOT_LEVEL)) {
217 int lvl = walker->level;
222 gfn = gpte_to_gfn_lvl(pte, lvl);
223 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
226 walker->level == PT_DIRECTORY_LEVEL &&
228 gfn += pse36_gfn_delta(pte);
230 ac = write_fault | fetch_fault | user_fault;
232 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
234 if (real_gpa == UNMAPPED_GVA)
237 walker->gfn = real_gpa >> PAGE_SHIFT;
242 pt_access = pte_access;
246 if (!present || eperm || rsvd_fault)
249 if (write_fault && !is_dirty_gpte(pte)) {
252 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
253 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
257 mark_page_dirty(vcpu->kvm, table_gfn);
258 pte |= PT_DIRTY_MASK;
259 walker->ptes[walker->level - 1] = pte;
262 walker->pt_access = pt_access;
263 walker->pte_access = pte_access;
264 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
265 __func__, (u64)pte, pte_access, pt_access);
269 walker->error_code = 0;
271 walker->error_code |= PFERR_PRESENT_MASK;
273 walker->error_code |= write_fault | user_fault;
275 if (fetch_fault && mmu->nx)
276 walker->error_code |= PFERR_FETCH_MASK;
278 walker->error_code |= PFERR_RSVD_MASK;
280 vcpu->arch.fault.address = addr;
281 vcpu->arch.fault.error_code = walker->error_code;
283 trace_kvm_mmu_walker_error(walker->error_code);
287 static int FNAME(walk_addr)(struct guest_walker *walker,
288 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
290 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
294 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
295 struct kvm_vcpu *vcpu, gva_t addr,
298 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
302 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
303 struct kvm_mmu_page *sp, u64 *spte,
306 u64 nonpresent = shadow_trap_nonpresent_pte;
308 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
311 if (!is_present_gpte(gpte)) {
313 nonpresent = shadow_notrap_nonpresent_pte;
317 if (!(gpte & PT_ACCESSED_MASK))
323 drop_spte(vcpu->kvm, spte, nonpresent);
327 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
328 u64 *spte, const void *pte)
334 gpte = *(const pt_element_t *)pte;
335 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
338 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
339 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
340 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
342 pfn = vcpu->arch.update_pte.pfn;
343 if (is_error_pfn(pfn))
345 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
349 * we call mmu_set_spte() with host_writable = true beacuse that
350 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
352 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
353 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
354 gpte_to_gfn(gpte), pfn, true, true);
357 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
358 struct guest_walker *gw, int level)
360 pt_element_t curr_pte;
361 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
365 if (level == PT_PAGE_TABLE_LEVEL) {
366 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
367 base_gpa = pte_gpa & ~mask;
368 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
370 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
371 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
372 curr_pte = gw->prefetch_ptes[index];
374 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
375 &curr_pte, sizeof(curr_pte));
377 return r || curr_pte != gw->ptes[level - 1];
380 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
383 struct kvm_mmu_page *sp;
384 pt_element_t *gptep = gw->prefetch_ptes;
388 sp = page_header(__pa(sptep));
390 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
394 return __direct_pte_prefetch(vcpu, sp, sptep);
396 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
399 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
409 if (*spte != shadow_trap_nonpresent_pte)
414 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
417 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
418 gfn = gpte_to_gfn(gpte);
419 dirty = is_dirty_gpte(gpte);
420 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
421 (pte_access & ACC_WRITE_MASK) && dirty);
422 if (is_error_pfn(pfn)) {
423 kvm_release_pfn_clean(pfn);
427 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
428 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
434 * Fetch a shadow pte for a specific level in the paging hierarchy.
436 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
437 struct guest_walker *gw,
438 int user_fault, int write_fault, int hlevel,
439 int *ptwrite, pfn_t pfn, bool map_writable)
441 unsigned access = gw->pt_access;
442 struct kvm_mmu_page *sp = NULL;
443 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
445 unsigned direct_access;
446 struct kvm_shadow_walk_iterator it;
448 if (!is_present_gpte(gw->ptes[gw->level - 1]))
451 direct_access = gw->pt_access & gw->pte_access;
453 direct_access &= ~ACC_WRITE_MASK;
455 top_level = vcpu->arch.mmu.root_level;
456 if (top_level == PT32E_ROOT_LEVEL)
457 top_level = PT32_ROOT_LEVEL;
459 * Verify that the top-level gpte is still there. Since the page
460 * is a root page, it is either write protected (and cannot be
461 * changed from now on) or it is invalid (in which case, we don't
462 * really care if it changes underneath us after this point).
464 if (FNAME(gpte_changed)(vcpu, gw, top_level))
465 goto out_gpte_changed;
467 for (shadow_walk_init(&it, vcpu, addr);
468 shadow_walk_okay(&it) && it.level > gw->level;
469 shadow_walk_next(&it)) {
472 drop_large_spte(vcpu, it.sptep);
475 if (!is_shadow_present_pte(*it.sptep)) {
476 table_gfn = gw->table_gfn[it.level - 2];
477 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
478 false, access, it.sptep);
482 * Verify that the gpte in the page we've just write
483 * protected is still there.
485 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
486 goto out_gpte_changed;
489 link_shadow_page(it.sptep, sp);
493 shadow_walk_okay(&it) && it.level > hlevel;
494 shadow_walk_next(&it)) {
497 validate_direct_spte(vcpu, it.sptep, direct_access);
499 drop_large_spte(vcpu, it.sptep);
501 if (is_shadow_present_pte(*it.sptep))
504 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
506 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
507 true, direct_access, it.sptep);
508 link_shadow_page(it.sptep, sp);
511 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
512 user_fault, write_fault, dirty, ptwrite, it.level,
513 gw->gfn, pfn, false, map_writable);
514 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
520 kvm_mmu_put_page(sp, it.sptep);
521 kvm_release_pfn_clean(pfn);
526 * Page fault handler. There are several causes for a page fault:
527 * - there is no shadow pte for the guest pte
528 * - write access through a shadow pte marked read only so that we can set
530 * - write access to a shadow pte marked read only so we can update the page
531 * dirty bitmap, when userspace requests it
532 * - mmio access; in this case we will never install a present shadow pte
533 * - normal guest page fault due to the guest pte marked not present, not
534 * writable, or not executable
536 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
537 * a negative value on error.
539 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
542 int write_fault = error_code & PFERR_WRITE_MASK;
543 int user_fault = error_code & PFERR_USER_MASK;
544 struct guest_walker walker;
549 int level = PT_PAGE_TABLE_LEVEL;
550 unsigned long mmu_seq;
553 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
555 r = mmu_topup_memory_caches(vcpu);
560 * Look up the guest pte for the faulting address.
562 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
565 * The page is not mapped by the guest. Let the guest handle it.
568 pgprintk("%s: guest page fault\n", __func__);
569 inject_page_fault(vcpu);
570 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
574 if (walker.level >= PT_DIRECTORY_LEVEL) {
575 level = min(walker.level, mapping_level(vcpu, walker.gfn));
576 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
579 mmu_seq = vcpu->kvm->mmu_notifier_seq;
582 if (try_async_pf(vcpu, no_apf, walker.gfn, addr, &pfn, write_fault,
587 if (is_error_pfn(pfn))
588 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
591 walker.pte_access &= ~ACC_WRITE_MASK;
593 spin_lock(&vcpu->kvm->mmu_lock);
594 if (mmu_notifier_retry(vcpu, mmu_seq))
597 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
598 kvm_mmu_free_some_pages(vcpu);
599 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
600 level, &write_pt, pfn, map_writable);
602 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
603 sptep, *sptep, write_pt);
606 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
608 ++vcpu->stat.pf_fixed;
609 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
610 spin_unlock(&vcpu->kvm->mmu_lock);
615 spin_unlock(&vcpu->kvm->mmu_lock);
616 kvm_release_pfn_clean(pfn);
620 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
622 struct kvm_shadow_walk_iterator iterator;
623 struct kvm_mmu_page *sp;
629 spin_lock(&vcpu->kvm->mmu_lock);
631 for_each_shadow_entry(vcpu, gva, iterator) {
632 level = iterator.level;
633 sptep = iterator.sptep;
635 sp = page_header(__pa(sptep));
636 if (is_last_spte(*sptep, level)) {
643 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
644 offset = sp->role.quadrant << shift;
646 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
647 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
649 if (is_shadow_present_pte(*sptep)) {
650 if (is_large_pte(*sptep))
651 --vcpu->kvm->stat.lpages;
652 drop_spte(vcpu->kvm, sptep,
653 shadow_trap_nonpresent_pte);
656 __set_spte(sptep, shadow_trap_nonpresent_pte);
660 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
665 kvm_flush_remote_tlbs(vcpu->kvm);
667 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
669 spin_unlock(&vcpu->kvm->mmu_lock);
674 if (mmu_topup_memory_caches(vcpu))
676 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
679 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
682 struct guest_walker walker;
683 gpa_t gpa = UNMAPPED_GVA;
686 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
689 gpa = gfn_to_gpa(walker.gfn);
690 gpa |= vaddr & ~PAGE_MASK;
692 *error = walker.error_code;
697 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
698 u32 access, u32 *error)
700 struct guest_walker walker;
701 gpa_t gpa = UNMAPPED_GVA;
704 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
707 gpa = gfn_to_gpa(walker.gfn);
708 gpa |= vaddr & ~PAGE_MASK;
710 *error = walker.error_code;
715 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
716 struct kvm_mmu_page *sp)
719 pt_element_t pt[256 / sizeof(pt_element_t)];
723 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
724 nonpaging_prefetch_page(vcpu, sp);
728 pte_gpa = gfn_to_gpa(sp->gfn);
730 offset = sp->role.quadrant << PT64_LEVEL_BITS;
731 pte_gpa += offset * sizeof(pt_element_t);
734 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
735 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
736 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
737 for (j = 0; j < ARRAY_SIZE(pt); ++j)
738 if (r || is_present_gpte(pt[j]))
739 sp->spt[i+j] = shadow_trap_nonpresent_pte;
741 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
746 * Using the cached information from sp->gfns is safe because:
747 * - The spte has a reference to the struct page, so the pfn for a given gfn
748 * can't change unless all sptes pointing to it are nuked first.
751 * We should flush all tlbs if spte is dropped even though guest is
752 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
753 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
754 * used by guest then tlbs are not flushed, so guest is allowed to access the
756 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
758 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
760 int i, offset, nr_present;
764 offset = nr_present = 0;
766 /* direct kvm_mmu_page can not be unsync. */
767 BUG_ON(sp->role.direct);
770 offset = sp->role.quadrant << PT64_LEVEL_BITS;
772 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
774 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
780 if (!is_shadow_present_pte(sp->spt[i]))
783 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
785 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
786 sizeof(pt_element_t)))
789 gfn = gpte_to_gfn(gpte);
791 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
792 vcpu->kvm->tlbs_dirty++;
796 if (gfn != sp->gfns[i]) {
797 drop_spte(vcpu->kvm, &sp->spt[i],
798 shadow_trap_nonpresent_pte);
799 vcpu->kvm->tlbs_dirty++;
804 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
805 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
806 pte_access &= ~ACC_WRITE_MASK;
811 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
812 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
813 spte_to_pfn(sp->spt[i]), true, false,
823 #undef PT_BASE_ADDR_MASK
826 #undef PT_LVL_ADDR_MASK
827 #undef PT_LVL_OFFSET_MASK
829 #undef PT_MAX_FULL_LEVELS
831 #undef gpte_to_gfn_lvl