2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
36 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
37 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
39 #define PT_MAX_FULL_LEVELS 4
40 #define CMPXCHG cmpxchg
42 #define CMPXCHG cmpxchg64
43 #define PT_MAX_FULL_LEVELS 2
46 #define pt_element_t u32
47 #define guest_walker guest_walker32
48 #define FNAME(name) paging##32_##name
49 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
50 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
51 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
52 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
53 #define PT_LEVEL_BITS PT32_LEVEL_BITS
54 #define PT_MAX_FULL_LEVELS 2
55 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
56 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
57 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
58 #define CMPXCHG cmpxchg
59 #elif PTTYPE == PTTYPE_EPT
60 #define pt_element_t u64
61 #define guest_walker guest_walkerEPT
62 #define FNAME(name) ept_##name
63 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
64 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
65 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
66 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
67 #define PT_LEVEL_BITS PT64_LEVEL_BITS
68 #define PT_GUEST_DIRTY_SHIFT 9
69 #define PT_GUEST_ACCESSED_SHIFT 8
70 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
71 #define CMPXCHG cmpxchg64
72 #define PT_MAX_FULL_LEVELS 4
74 #error Invalid PTTYPE value
77 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
78 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
80 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
81 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
84 * The guest_walker structure emulates the behavior of the hardware page
90 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
91 pt_element_t ptes[PT_MAX_FULL_LEVELS];
92 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
93 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
94 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
95 bool pte_writable[PT_MAX_FULL_LEVELS];
99 struct x86_exception fault;
102 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
104 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
107 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
112 /* dirty bit is not supported, so no need to track it */
113 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
116 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
118 mask = (unsigned)~ACC_WRITE_MASK;
119 /* Allow write access to dirty gptes */
120 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
125 static inline int FNAME(is_present_gpte)(unsigned long pte)
127 #if PTTYPE != PTTYPE_EPT
128 return pte & PT_PRESENT_MASK;
134 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
135 pt_element_t __user *ptep_user, unsigned index,
136 pt_element_t orig_pte, pt_element_t new_pte)
143 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
144 /* Check if the user is doing something meaningless. */
145 if (unlikely(npages != 1))
148 table = kmap_atomic(page);
149 ret = CMPXCHG(&table[index], orig_pte, new_pte);
150 kunmap_atomic(table);
152 kvm_release_page_dirty(page);
154 return (ret != orig_pte);
157 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
158 struct kvm_mmu_page *sp, u64 *spte,
161 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
164 if (!FNAME(is_present_gpte)(gpte))
167 /* if accessed bit is not supported prefetch non accessed gpte */
168 if (PT_HAVE_ACCESSED_DIRTY(&vcpu->arch.mmu) && !(gpte & PT_GUEST_ACCESSED_MASK))
174 drop_spte(vcpu->kvm, spte);
179 * For PTTYPE_EPT, a page table can be executable but not readable
180 * on supported processors. Therefore, set_spte does not automatically
181 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
182 * to signify readability since it isn't used in the EPT case
184 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
187 #if PTTYPE == PTTYPE_EPT
188 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
189 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
190 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
192 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
193 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
194 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
195 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
196 access ^= (gpte >> PT64_NX_SHIFT);
202 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
204 struct guest_walker *walker,
207 unsigned level, index;
208 pt_element_t pte, orig_pte;
209 pt_element_t __user *ptep_user;
213 /* dirty/accessed bits are not supported, so no need to update them */
214 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
217 for (level = walker->max_level; level >= walker->level; --level) {
218 pte = orig_pte = walker->ptes[level - 1];
219 table_gfn = walker->table_gfn[level - 1];
220 ptep_user = walker->ptep_user[level - 1];
221 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
222 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
223 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
224 pte |= PT_GUEST_ACCESSED_MASK;
226 if (level == walker->level && write_fault &&
227 !(pte & PT_GUEST_DIRTY_MASK)) {
228 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
229 pte |= PT_GUEST_DIRTY_MASK;
235 * If the slot is read-only, simply do not process the accessed
236 * and dirty bits. This is the correct thing to do if the slot
237 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
238 * are only supported if the accessed and dirty bits are already
239 * set in the ROM (so that MMIO writes are never needed).
241 * Note that NPT does not allow this at all and faults, since
242 * it always wants nested page table entries for the guest
243 * page tables to be writable. And EPT works but will simply
244 * overwrite the read-only memory to set the accessed and dirty
247 if (unlikely(!walker->pte_writable[level - 1]))
250 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
254 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
255 walker->ptes[level - 1] = pte;
260 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
264 pte_t pte = {.pte = gpte};
266 pkeys = pte_flags_pkey(pte_flags(pte));
272 * Fetch a guest pte for a guest virtual address
274 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
275 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
276 gva_t addr, u32 access)
280 pt_element_t __user *uninitialized_var(ptep_user);
282 unsigned index, pt_access, pte_access, accessed_dirty, pte_pkey;
283 unsigned nested_access;
287 const int write_fault = access & PFERR_WRITE_MASK;
288 const int user_fault = access & PFERR_USER_MASK;
289 const int fetch_fault = access & PFERR_FETCH_MASK;
294 trace_kvm_mmu_pagetable_walk(addr, access);
296 walker->level = mmu->root_level;
297 pte = mmu->get_cr3(vcpu);
298 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
301 if (walker->level == PT32E_ROOT_LEVEL) {
302 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
303 trace_kvm_mmu_paging_element(pte, walker->level);
304 if (!FNAME(is_present_gpte)(pte))
309 walker->max_level = walker->level;
310 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
312 accessed_dirty = have_ad ? PT_GUEST_ACCESSED_MASK : 0;
315 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
316 * by the MOV to CR instruction are treated as reads and do not cause the
317 * processor to set the dirty flag in any EPT paging-structure entry.
319 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
321 pt_access = pte_access = ACC_ALL;
326 unsigned long host_addr;
328 pt_access &= pte_access;
331 index = PT_INDEX(addr, walker->level);
333 table_gfn = gpte_to_gfn(pte);
334 offset = index * sizeof(pt_element_t);
335 pte_gpa = gfn_to_gpa(table_gfn) + offset;
336 walker->table_gfn[walker->level - 1] = table_gfn;
337 walker->pte_gpa[walker->level - 1] = pte_gpa;
339 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
344 * FIXME: This can happen if emulation (for of an INS/OUTS
345 * instruction) triggers a nested page fault. The exit
346 * qualification / exit info field will incorrectly have
347 * "guest page access" as the nested page fault's cause,
348 * instead of "guest page structure access". To fix this,
349 * the x86_exception struct should be augmented with enough
350 * information to fix the exit_qualification or exit_info_1
353 if (unlikely(real_gfn == UNMAPPED_GVA))
356 real_gfn = gpa_to_gfn(real_gfn);
358 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
359 &walker->pte_writable[walker->level - 1]);
360 if (unlikely(kvm_is_error_hva(host_addr)))
363 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
364 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
366 walker->ptep_user[walker->level - 1] = ptep_user;
368 trace_kvm_mmu_paging_element(pte, walker->level);
370 if (unlikely(!FNAME(is_present_gpte)(pte)))
373 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
374 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
378 accessed_dirty &= pte;
379 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
381 walker->ptes[walker->level - 1] = pte;
382 } while (!is_last_gpte(mmu, walker->level, pte));
384 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
385 errcode = permission_fault(vcpu, mmu, pte_access, pte_pkey, access);
386 if (unlikely(errcode))
389 gfn = gpte_to_gfn_lvl(pte, walker->level);
390 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
392 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
393 gfn += pse36_gfn_delta(pte);
395 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
396 if (real_gpa == UNMAPPED_GVA)
399 walker->gfn = real_gpa >> PAGE_SHIFT;
402 FNAME(protect_clean_gpte)(mmu, &pte_access, pte);
405 * On a write fault, fold the dirty bit into accessed_dirty.
406 * For modes without A/D bits support accessed_dirty will be
409 accessed_dirty &= pte >>
410 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
412 if (unlikely(!accessed_dirty)) {
413 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
414 if (unlikely(ret < 0))
420 walker->pt_access = pt_access;
421 walker->pte_access = pte_access;
422 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
423 __func__, (u64)pte, pte_access, pt_access);
427 errcode |= write_fault | user_fault;
428 if (fetch_fault && (mmu->nx ||
429 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
430 errcode |= PFERR_FETCH_MASK;
432 walker->fault.vector = PF_VECTOR;
433 walker->fault.error_code_valid = true;
434 walker->fault.error_code = errcode;
436 #if PTTYPE == PTTYPE_EPT
438 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
439 * misconfiguration requires to be injected. The detection is
440 * done by is_rsvd_bits_set() above.
442 * We set up the value of exit_qualification to inject:
443 * [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
444 * [5:3] - Calculated by the page walk of the guest EPT page tables
445 * [7:8] - Derived from [7:8] of real exit_qualification
447 * The other bits are set to 0.
449 if (!(errcode & PFERR_RSVD_MASK)) {
450 vcpu->arch.exit_qualification &= 0x187;
451 vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
454 walker->fault.address = addr;
455 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
457 trace_kvm_mmu_walker_error(walker->fault.error_code);
461 static int FNAME(walk_addr)(struct guest_walker *walker,
462 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
464 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
468 #if PTTYPE != PTTYPE_EPT
469 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
470 struct kvm_vcpu *vcpu, gva_t addr,
473 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
479 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
480 u64 *spte, pt_element_t gpte, bool no_dirty_log)
486 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
489 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
491 gfn = gpte_to_gfn(gpte);
492 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
493 FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte);
494 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
495 no_dirty_log && (pte_access & ACC_WRITE_MASK));
496 if (is_error_pfn(pfn))
500 * we call mmu_set_spte() with host_writable = true because
501 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
503 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
509 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
510 u64 *spte, const void *pte)
512 pt_element_t gpte = *(const pt_element_t *)pte;
514 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
517 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
518 struct guest_walker *gw, int level)
520 pt_element_t curr_pte;
521 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
525 if (level == PT_PAGE_TABLE_LEVEL) {
526 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
527 base_gpa = pte_gpa & ~mask;
528 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
530 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
531 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
532 curr_pte = gw->prefetch_ptes[index];
534 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
535 &curr_pte, sizeof(curr_pte));
537 return r || curr_pte != gw->ptes[level - 1];
540 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
543 struct kvm_mmu_page *sp;
544 pt_element_t *gptep = gw->prefetch_ptes;
548 sp = page_header(__pa(sptep));
550 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
554 return __direct_pte_prefetch(vcpu, sp, sptep);
556 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
559 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
563 if (is_shadow_present_pte(*spte))
566 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
572 * Fetch a shadow pte for a specific level in the paging hierarchy.
573 * If the guest tries to write a write-protected page, we need to
574 * emulate this operation, return 1 to indicate this case.
576 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
577 struct guest_walker *gw,
578 int write_fault, int hlevel,
579 kvm_pfn_t pfn, bool map_writable, bool prefault)
581 struct kvm_mmu_page *sp = NULL;
582 struct kvm_shadow_walk_iterator it;
583 unsigned direct_access, access = gw->pt_access;
584 int top_level, emulate;
586 direct_access = gw->pte_access;
588 top_level = vcpu->arch.mmu.root_level;
589 if (top_level == PT32E_ROOT_LEVEL)
590 top_level = PT32_ROOT_LEVEL;
592 * Verify that the top-level gpte is still there. Since the page
593 * is a root page, it is either write protected (and cannot be
594 * changed from now on) or it is invalid (in which case, we don't
595 * really care if it changes underneath us after this point).
597 if (FNAME(gpte_changed)(vcpu, gw, top_level))
598 goto out_gpte_changed;
600 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
601 goto out_gpte_changed;
603 for (shadow_walk_init(&it, vcpu, addr);
604 shadow_walk_okay(&it) && it.level > gw->level;
605 shadow_walk_next(&it)) {
608 clear_sp_write_flooding_count(it.sptep);
609 drop_large_spte(vcpu, it.sptep);
612 if (!is_shadow_present_pte(*it.sptep)) {
613 table_gfn = gw->table_gfn[it.level - 2];
614 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
619 * Verify that the gpte in the page we've just write
620 * protected is still there.
622 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
623 goto out_gpte_changed;
626 link_shadow_page(vcpu, it.sptep, sp);
630 shadow_walk_okay(&it) && it.level > hlevel;
631 shadow_walk_next(&it)) {
634 clear_sp_write_flooding_count(it.sptep);
635 validate_direct_spte(vcpu, it.sptep, direct_access);
637 drop_large_spte(vcpu, it.sptep);
639 if (is_shadow_present_pte(*it.sptep))
642 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
644 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
645 true, direct_access);
646 link_shadow_page(vcpu, it.sptep, sp);
649 clear_sp_write_flooding_count(it.sptep);
650 emulate = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
651 it.level, gw->gfn, pfn, prefault, map_writable);
652 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
657 kvm_release_pfn_clean(pfn);
662 * To see whether the mapped gfn can write its page table in the current
665 * It is the helper function of FNAME(page_fault). When guest uses large page
666 * size to map the writable gfn which is used as current page table, we should
667 * force kvm to use small page size to map it because new shadow page will be
668 * created when kvm establishes shadow page table that stop kvm using large
669 * page size. Do it early can avoid unnecessary #PF and emulation.
671 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
672 * currently used as its page table.
674 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
675 * since the PDPT is always shadowed, that means, we can not use large page
676 * size to map the gfn which is used as PDPT.
679 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
680 struct guest_walker *walker, int user_fault,
681 bool *write_fault_to_shadow_pgtable)
684 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
685 bool self_changed = false;
687 if (!(walker->pte_access & ACC_WRITE_MASK ||
688 (!is_write_protection(vcpu) && !user_fault)))
691 for (level = walker->level; level <= walker->max_level; level++) {
692 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
694 self_changed |= !(gfn & mask);
695 *write_fault_to_shadow_pgtable |= !gfn;
702 * Page fault handler. There are several causes for a page fault:
703 * - there is no shadow pte for the guest pte
704 * - write access through a shadow pte marked read only so that we can set
706 * - write access to a shadow pte marked read only so we can update the page
707 * dirty bitmap, when userspace requests it
708 * - mmio access; in this case we will never install a present shadow pte
709 * - normal guest page fault due to the guest pte marked not present, not
710 * writable, or not executable
712 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
713 * a negative value on error.
715 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
718 int write_fault = error_code & PFERR_WRITE_MASK;
719 int user_fault = error_code & PFERR_USER_MASK;
720 struct guest_walker walker;
723 int level = PT_PAGE_TABLE_LEVEL;
724 bool force_pt_level = false;
725 unsigned long mmu_seq;
726 bool map_writable, is_self_change_mapping;
728 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
730 r = mmu_topup_memory_caches(vcpu);
735 * If PFEC.RSVD is set, this is a shadow page fault.
736 * The bit needs to be cleared before walking guest page tables.
738 error_code &= ~PFERR_RSVD_MASK;
741 * Look up the guest pte for the faulting address.
743 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
746 * The page is not mapped by the guest. Let the guest handle it.
749 pgprintk("%s: guest page fault\n", __func__);
751 inject_page_fault(vcpu, &walker.fault);
756 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
757 shadow_page_table_clear_flood(vcpu, addr);
761 vcpu->arch.write_fault_to_shadow_pgtable = false;
763 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
764 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
766 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
767 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
768 if (likely(!force_pt_level)) {
769 level = min(walker.level, level);
770 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
773 force_pt_level = true;
775 mmu_seq = vcpu->kvm->mmu_notifier_seq;
778 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
782 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
783 walker.gfn, pfn, walker.pte_access, &r))
787 * Do not change pte_access if the pfn is a mmio page, otherwise
788 * we will cache the incorrect access into mmio spte.
790 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
791 !is_write_protection(vcpu) && !user_fault &&
792 !is_noslot_pfn(pfn)) {
793 walker.pte_access |= ACC_WRITE_MASK;
794 walker.pte_access &= ~ACC_USER_MASK;
797 * If we converted a user page to a kernel page,
798 * so that the kernel can write to it when cr0.wp=0,
799 * then we should prevent the kernel from executing it
800 * if SMEP is enabled.
802 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
803 walker.pte_access &= ~ACC_EXEC_MASK;
806 spin_lock(&vcpu->kvm->mmu_lock);
807 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
810 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
811 make_mmu_pages_available(vcpu);
813 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
814 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
815 level, pfn, map_writable, prefault);
816 ++vcpu->stat.pf_fixed;
817 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
818 spin_unlock(&vcpu->kvm->mmu_lock);
823 spin_unlock(&vcpu->kvm->mmu_lock);
824 kvm_release_pfn_clean(pfn);
828 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
832 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
835 offset = sp->role.quadrant << PT64_LEVEL_BITS;
837 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
840 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
842 struct kvm_shadow_walk_iterator iterator;
843 struct kvm_mmu_page *sp;
847 vcpu_clear_mmio_info(vcpu, gva);
850 * No need to check return value here, rmap_can_add() can
851 * help us to skip pte prefetch later.
853 mmu_topup_memory_caches(vcpu);
855 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
860 spin_lock(&vcpu->kvm->mmu_lock);
861 for_each_shadow_entry(vcpu, gva, iterator) {
862 level = iterator.level;
863 sptep = iterator.sptep;
865 sp = page_header(__pa(sptep));
866 if (is_last_spte(*sptep, level)) {
873 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
874 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
876 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
877 kvm_flush_remote_tlbs(vcpu->kvm);
879 if (!rmap_can_add(vcpu))
882 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
883 sizeof(pt_element_t)))
886 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
889 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
892 spin_unlock(&vcpu->kvm->mmu_lock);
895 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
896 struct x86_exception *exception)
898 struct guest_walker walker;
899 gpa_t gpa = UNMAPPED_GVA;
902 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
905 gpa = gfn_to_gpa(walker.gfn);
906 gpa |= vaddr & ~PAGE_MASK;
907 } else if (exception)
908 *exception = walker.fault;
913 #if PTTYPE != PTTYPE_EPT
914 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
916 struct x86_exception *exception)
918 struct guest_walker walker;
919 gpa_t gpa = UNMAPPED_GVA;
922 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
925 gpa = gfn_to_gpa(walker.gfn);
926 gpa |= vaddr & ~PAGE_MASK;
927 } else if (exception)
928 *exception = walker.fault;
935 * Using the cached information from sp->gfns is safe because:
936 * - The spte has a reference to the struct page, so the pfn for a given gfn
937 * can't change unless all sptes pointing to it are nuked first.
940 * We should flush all tlbs if spte is dropped even though guest is
941 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
942 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
943 * used by guest then tlbs are not flushed, so guest is allowed to access the
945 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
947 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
949 int i, nr_present = 0;
953 /* direct kvm_mmu_page can not be unsync. */
954 BUG_ON(sp->role.direct);
956 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
958 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
967 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
969 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
970 sizeof(pt_element_t)))
973 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
975 * Update spte before increasing tlbs_dirty to make
976 * sure no tlb flush is lost after spte is zapped; see
977 * the comments in kvm_flush_remote_tlbs().
980 vcpu->kvm->tlbs_dirty++;
984 gfn = gpte_to_gfn(gpte);
985 pte_access = sp->role.access;
986 pte_access &= FNAME(gpte_access)(vcpu, gpte);
987 FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte);
989 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
993 if (gfn != sp->gfns[i]) {
994 drop_spte(vcpu->kvm, &sp->spt[i]);
996 * The same as above where we are doing
997 * prefetch_invalid_gpte().
1000 vcpu->kvm->tlbs_dirty++;
1006 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1008 set_spte(vcpu, &sp->spt[i], pte_access,
1009 PT_PAGE_TABLE_LEVEL, gfn,
1010 spte_to_pfn(sp->spt[i]), true, false,
1020 #undef PT_BASE_ADDR_MASK
1022 #undef PT_LVL_ADDR_MASK
1023 #undef PT_LVL_OFFSET_MASK
1024 #undef PT_LEVEL_BITS
1025 #undef PT_MAX_FULL_LEVELS
1027 #undef gpte_to_gfn_lvl
1029 #undef PT_GUEST_ACCESSED_MASK
1030 #undef PT_GUEST_DIRTY_MASK
1031 #undef PT_GUEST_DIRTY_SHIFT
1032 #undef PT_GUEST_ACCESSED_SHIFT
1033 #undef PT_HAVE_ACCESSED_DIRTY