2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
31 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
32 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
51 #define PT_LEVEL_BITS PT32_LEVEL_BITS
52 #define PT_MAX_FULL_LEVELS 2
53 #define CMPXCHG cmpxchg
55 #error Invalid PTTYPE value
58 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
59 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
62 * The guest_walker structure emulates the behavior of the hardware page
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
68 pt_element_t ptes[PT_MAX_FULL_LEVELS];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
81 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
82 gfn_t table_gfn, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
89 page = gfn_to_page(kvm, table_gfn);
91 table = kmap_atomic(page, KM_USER0);
92 ret = CMPXCHG(&table[index], orig_pte, new_pte);
93 kunmap_atomic(table, KM_USER0);
95 kvm_release_page_dirty(page);
97 return (ret != orig_pte);
100 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
104 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
107 access &= ~(gpte >> PT64_NX_SHIFT);
113 * Fetch a guest pte for a guest virtual address
115 static int FNAME(walk_addr)(struct guest_walker *walker,
116 struct kvm_vcpu *vcpu, gva_t addr,
117 int write_fault, int user_fault, int fetch_fault)
121 unsigned index, pt_access, pte_access;
125 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
128 walker->level = vcpu->arch.mmu.root_level;
129 pte = vcpu->arch.cr3;
131 if (!is_long_mode(vcpu)) {
132 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
133 trace_kvm_mmu_paging_element(pte, walker->level);
134 if (!is_present_gpte(pte))
139 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
140 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
145 index = PT_INDEX(addr, walker->level);
147 table_gfn = gpte_to_gfn(pte);
148 pte_gpa = gfn_to_gpa(table_gfn);
149 pte_gpa += index * sizeof(pt_element_t);
150 walker->table_gfn[walker->level - 1] = table_gfn;
151 walker->pte_gpa[walker->level - 1] = pte_gpa;
153 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
154 trace_kvm_mmu_paging_element(pte, walker->level);
156 if (!is_present_gpte(pte))
159 rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
163 if (write_fault && !is_writeble_pte(pte))
164 if (user_fault || is_write_protection(vcpu))
167 if (user_fault && !(pte & PT_USER_MASK))
171 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
175 if (!(pte & PT_ACCESSED_MASK)) {
176 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
178 mark_page_dirty(vcpu->kvm, table_gfn);
179 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
180 index, pte, pte|PT_ACCESSED_MASK))
182 pte |= PT_ACCESSED_MASK;
185 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
187 walker->ptes[walker->level - 1] = pte;
189 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
190 ((walker->level == PT_DIRECTORY_LEVEL) &&
191 (pte & PT_PAGE_SIZE_MASK) &&
192 (PTTYPE == 64 || is_pse(vcpu))) ||
193 ((walker->level == PT_PDPE_LEVEL) &&
194 (pte & PT_PAGE_SIZE_MASK) &&
195 is_long_mode(vcpu))) {
196 int lvl = walker->level;
198 walker->gfn = gpte_to_gfn_lvl(pte, lvl);
199 walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
203 walker->level == PT_DIRECTORY_LEVEL &&
205 walker->gfn += pse36_gfn_delta(pte);
210 pt_access = pte_access;
214 if (write_fault && !is_dirty_gpte(pte)) {
217 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
218 mark_page_dirty(vcpu->kvm, table_gfn);
219 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
223 pte |= PT_DIRTY_MASK;
224 walker->ptes[walker->level - 1] = pte;
227 walker->pt_access = pt_access;
228 walker->pte_access = pte_access;
229 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
230 __func__, (u64)pte, pt_access, pte_access);
234 walker->error_code = 0;
238 walker->error_code = PFERR_PRESENT_MASK;
242 walker->error_code |= PFERR_WRITE_MASK;
244 walker->error_code |= PFERR_USER_MASK;
246 walker->error_code |= PFERR_FETCH_MASK;
248 walker->error_code |= PFERR_RSVD_MASK;
249 trace_kvm_mmu_walker_error(walker->error_code);
253 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
254 u64 *spte, const void *pte)
260 gpte = *(const pt_element_t *)pte;
261 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
262 if (!is_present_gpte(gpte))
263 __set_spte(spte, shadow_notrap_nonpresent_pte);
266 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
267 pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
268 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
270 pfn = vcpu->arch.update_pte.pfn;
271 if (is_error_pfn(pfn))
273 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
277 * we call mmu_set_spte() with reset_host_protection = true beacuse that
278 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
280 mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
281 gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
282 gpte_to_gfn(gpte), pfn, true, true);
286 * Fetch a shadow pte for a specific level in the paging hierarchy.
288 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
289 struct guest_walker *gw,
290 int user_fault, int write_fault, int hlevel,
291 int *ptwrite, pfn_t pfn)
293 unsigned access = gw->pt_access;
294 struct kvm_mmu_page *shadow_page;
295 u64 spte, *sptep = NULL;
300 pt_element_t curr_pte;
301 struct kvm_shadow_walk_iterator iterator;
303 if (!is_present_gpte(gw->ptes[gw->level - 1]))
306 for_each_shadow_entry(vcpu, addr, iterator) {
307 level = iterator.level;
308 sptep = iterator.sptep;
309 if (iterator.level == hlevel) {
310 mmu_set_spte(vcpu, sptep, access,
311 gw->pte_access & access,
312 user_fault, write_fault,
313 gw->ptes[gw->level-1] & PT_DIRTY_MASK,
315 gw->gfn, pfn, false, true);
319 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
322 if (is_large_pte(*sptep)) {
323 rmap_remove(vcpu->kvm, sptep);
324 __set_spte(sptep, shadow_trap_nonpresent_pte);
325 kvm_flush_remote_tlbs(vcpu->kvm);
328 if (level <= gw->level) {
329 int delta = level - gw->level + 1;
331 if (!is_dirty_gpte(gw->ptes[level - delta]))
332 access &= ~ACC_WRITE_MASK;
333 table_gfn = gpte_to_gfn(gw->ptes[level - delta]);
334 /* advance table_gfn when emulating 1gb pages with 4k */
336 table_gfn += PT_INDEX(addr, level);
339 table_gfn = gw->table_gfn[level - 2];
341 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
342 direct, access, sptep);
344 r = kvm_read_guest_atomic(vcpu->kvm,
345 gw->pte_gpa[level - 2],
346 &curr_pte, sizeof(curr_pte));
347 if (r || curr_pte != gw->ptes[level - 2]) {
348 kvm_mmu_put_page(shadow_page, sptep);
349 kvm_release_pfn_clean(pfn);
355 spte = __pa(shadow_page->spt)
356 | PT_PRESENT_MASK | PT_ACCESSED_MASK
357 | PT_WRITABLE_MASK | PT_USER_MASK;
365 * Page fault handler. There are several causes for a page fault:
366 * - there is no shadow pte for the guest pte
367 * - write access through a shadow pte marked read only so that we can set
369 * - write access to a shadow pte marked read only so we can update the page
370 * dirty bitmap, when userspace requests it
371 * - mmio access; in this case we will never install a present shadow pte
372 * - normal guest page fault due to the guest pte marked not present, not
373 * writable, or not executable
375 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
376 * a negative value on error.
378 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
381 int write_fault = error_code & PFERR_WRITE_MASK;
382 int user_fault = error_code & PFERR_USER_MASK;
383 int fetch_fault = error_code & PFERR_FETCH_MASK;
384 struct guest_walker walker;
389 int level = PT_PAGE_TABLE_LEVEL;
390 unsigned long mmu_seq;
392 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
393 kvm_mmu_audit(vcpu, "pre page fault");
395 r = mmu_topup_memory_caches(vcpu);
400 * Look up the guest pte for the faulting address.
402 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
406 * The page is not mapped by the guest. Let the guest handle it.
409 pgprintk("%s: guest page fault\n", __func__);
410 inject_page_fault(vcpu, addr, walker.error_code);
411 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
415 if (walker.level >= PT_DIRECTORY_LEVEL) {
416 level = min(walker.level, mapping_level(vcpu, walker.gfn));
417 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
420 mmu_seq = vcpu->kvm->mmu_notifier_seq;
422 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
425 if (is_error_pfn(pfn)) {
426 pgprintk("gfn %lx is mmio\n", walker.gfn);
427 kvm_release_pfn_clean(pfn);
431 spin_lock(&vcpu->kvm->mmu_lock);
432 if (mmu_notifier_retry(vcpu, mmu_seq))
434 kvm_mmu_free_some_pages(vcpu);
435 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
436 level, &write_pt, pfn);
437 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
438 sptep, *sptep, write_pt);
441 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
443 ++vcpu->stat.pf_fixed;
444 kvm_mmu_audit(vcpu, "post page fault (fixed)");
445 spin_unlock(&vcpu->kvm->mmu_lock);
450 spin_unlock(&vcpu->kvm->mmu_lock);
451 kvm_release_pfn_clean(pfn);
455 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
457 struct kvm_shadow_walk_iterator iterator;
462 spin_lock(&vcpu->kvm->mmu_lock);
464 for_each_shadow_entry(vcpu, gva, iterator) {
465 level = iterator.level;
466 sptep = iterator.sptep;
468 if (level == PT_PAGE_TABLE_LEVEL ||
469 ((level == PT_DIRECTORY_LEVEL && is_large_pte(*sptep))) ||
470 ((level == PT_PDPE_LEVEL && is_large_pte(*sptep)))) {
472 if (is_shadow_present_pte(*sptep)) {
473 rmap_remove(vcpu->kvm, sptep);
474 if (is_large_pte(*sptep))
475 --vcpu->kvm->stat.lpages;
478 __set_spte(sptep, shadow_trap_nonpresent_pte);
482 if (!is_shadow_present_pte(*sptep))
487 kvm_flush_remote_tlbs(vcpu->kvm);
488 spin_unlock(&vcpu->kvm->mmu_lock);
491 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
493 struct guest_walker walker;
494 gpa_t gpa = UNMAPPED_GVA;
497 r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
500 gpa = gfn_to_gpa(walker.gfn);
501 gpa |= vaddr & ~PAGE_MASK;
507 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
508 struct kvm_mmu_page *sp)
511 pt_element_t pt[256 / sizeof(pt_element_t)];
515 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
516 nonpaging_prefetch_page(vcpu, sp);
520 pte_gpa = gfn_to_gpa(sp->gfn);
522 offset = sp->role.quadrant << PT64_LEVEL_BITS;
523 pte_gpa += offset * sizeof(pt_element_t);
526 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
527 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
528 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
529 for (j = 0; j < ARRAY_SIZE(pt); ++j)
530 if (r || is_present_gpte(pt[j]))
531 sp->spt[i+j] = shadow_trap_nonpresent_pte;
533 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
538 * Using the cached information from sp->gfns is safe because:
539 * - The spte has a reference to the struct page, so the pfn for a given gfn
540 * can't change unless all sptes pointing to it are nuked first.
541 * - Alias changes zap the entire shadow cache.
543 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
545 int i, offset, nr_present;
546 bool reset_host_protection;
548 offset = nr_present = 0;
551 offset = sp->role.quadrant << PT64_LEVEL_BITS;
553 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
557 gfn_t gfn = sp->gfns[i];
559 if (!is_shadow_present_pte(sp->spt[i]))
562 pte_gpa = gfn_to_gpa(sp->gfn);
563 pte_gpa += (i+offset) * sizeof(pt_element_t);
565 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
566 sizeof(pt_element_t)))
569 if (gpte_to_gfn(gpte) != gfn || !is_present_gpte(gpte) ||
570 !(gpte & PT_ACCESSED_MASK)) {
573 rmap_remove(vcpu->kvm, &sp->spt[i]);
574 if (is_present_gpte(gpte))
575 nonpresent = shadow_trap_nonpresent_pte;
577 nonpresent = shadow_notrap_nonpresent_pte;
578 __set_spte(&sp->spt[i], nonpresent);
583 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
584 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
585 pte_access &= ~ACC_WRITE_MASK;
586 reset_host_protection = 0;
588 reset_host_protection = 1;
590 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
591 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
592 spte_to_pfn(sp->spt[i]), true, false,
593 reset_host_protection);
602 #undef PT_BASE_ADDR_MASK
605 #undef PT_LVL_ADDR_MASK
606 #undef PT_LVL_OFFSET_MASK
608 #undef PT_MAX_FULL_LEVELS
610 #undef gpte_to_gfn_lvl