2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/kernel.h>
29 #include <linux/vmalloc.h>
30 #include <linux/highmem.h>
31 #include <linux/sched.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
35 #include <asm/perf_event.h>
36 #include <asm/tlbflush.h>
38 #include <asm/debugreg.h>
39 #include <asm/kvm_para.h>
41 #include <asm/virtext.h>
44 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 MODULE_AUTHOR("Qumranet");
47 MODULE_LICENSE("GPL");
49 static const struct x86_cpu_id svm_cpu_id[] = {
50 X86_FEATURE_MATCH(X86_FEATURE_SVM),
53 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
55 #define IOPM_ALLOC_ORDER 2
56 #define MSRPM_ALLOC_ORDER 1
58 #define SEG_TYPE_LDT 2
59 #define SEG_TYPE_BUSY_TSS16 3
61 #define SVM_FEATURE_NPT (1 << 0)
62 #define SVM_FEATURE_LBRV (1 << 1)
63 #define SVM_FEATURE_SVML (1 << 2)
64 #define SVM_FEATURE_NRIP (1 << 3)
65 #define SVM_FEATURE_TSC_RATE (1 << 4)
66 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
67 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
68 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
69 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
71 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
72 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
73 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
75 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
77 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
78 #define TSC_RATIO_MIN 0x0000000000000001ULL
79 #define TSC_RATIO_MAX 0x000000ffffffffffULL
81 static bool erratum_383_found __read_mostly;
83 static const u32 host_save_user_msrs[] = {
85 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
88 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
92 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
102 /* These are the merged vectors */
105 /* gpa pointers to the real vectors */
109 /* A VMEXIT is required but not yet emulated */
112 /* cache for intercepts of the guest */
115 u32 intercept_exceptions;
118 /* Nested Paging related state */
122 #define MSRPM_OFFSETS 16
123 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
126 * Set osvw_len to higher value when updated Revision Guides
127 * are published and we know what the new status bits are
129 static uint64_t osvw_len = 4, osvw_status;
132 struct kvm_vcpu vcpu;
134 unsigned long vmcb_pa;
135 struct svm_cpu_data *svm_data;
136 uint64_t asid_generation;
137 uint64_t sysenter_esp;
138 uint64_t sysenter_eip;
143 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
155 struct nested_state nested;
159 unsigned int3_injected;
160 unsigned long int3_rip;
163 /* cached guest cpuid flags for faster access */
164 bool nrips_enabled : 1;
167 static DEFINE_PER_CPU(u64, current_tsc_ratio);
168 #define TSC_RATIO_DEFAULT 0x0100000000ULL
170 #define MSR_INVALID 0xffffffffU
172 static const struct svm_direct_access_msrs {
173 u32 index; /* Index of the MSR */
174 bool always; /* True if intercept is always on */
175 } direct_access_msrs[] = {
176 { .index = MSR_STAR, .always = true },
177 { .index = MSR_IA32_SYSENTER_CS, .always = true },
179 { .index = MSR_GS_BASE, .always = true },
180 { .index = MSR_FS_BASE, .always = true },
181 { .index = MSR_KERNEL_GS_BASE, .always = true },
182 { .index = MSR_LSTAR, .always = true },
183 { .index = MSR_CSTAR, .always = true },
184 { .index = MSR_SYSCALL_MASK, .always = true },
186 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
187 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
188 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
189 { .index = MSR_IA32_LASTINTTOIP, .always = false },
190 { .index = MSR_INVALID, .always = false },
193 /* enable NPT for AMD64 and X86 with PAE */
194 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
195 static bool npt_enabled = true;
197 static bool npt_enabled;
200 /* allow nested paging (virtualized MMU) for all guests */
201 static int npt = true;
202 module_param(npt, int, S_IRUGO);
204 /* allow nested virtualization in KVM/SVM */
205 static int nested = true;
206 module_param(nested, int, S_IRUGO);
208 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
209 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
210 static void svm_complete_interrupts(struct vcpu_svm *svm);
212 static int nested_svm_exit_handled(struct vcpu_svm *svm);
213 static int nested_svm_intercept(struct vcpu_svm *svm);
214 static int nested_svm_vmexit(struct vcpu_svm *svm);
215 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
216 bool has_error_code, u32 error_code);
219 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
220 pause filter count */
221 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
222 VMCB_ASID, /* ASID */
223 VMCB_INTR, /* int_ctl, int_vector */
224 VMCB_NPT, /* npt_en, nCR3, gPAT */
225 VMCB_CR, /* CR0, CR3, CR4, EFER */
226 VMCB_DR, /* DR6, DR7 */
227 VMCB_DT, /* GDT, IDT */
228 VMCB_SEG, /* CS, DS, SS, ES, CPL */
229 VMCB_CR2, /* CR2 only */
230 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
234 /* TPR and CR2 are always written before VMRUN */
235 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
237 static inline void mark_all_dirty(struct vmcb *vmcb)
239 vmcb->control.clean = 0;
242 static inline void mark_all_clean(struct vmcb *vmcb)
244 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
245 & ~VMCB_ALWAYS_DIRTY_MASK;
248 static inline void mark_dirty(struct vmcb *vmcb, int bit)
250 vmcb->control.clean &= ~(1 << bit);
253 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
255 return container_of(vcpu, struct vcpu_svm, vcpu);
258 static void recalc_intercepts(struct vcpu_svm *svm)
260 struct vmcb_control_area *c, *h;
261 struct nested_state *g;
263 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
265 if (!is_guest_mode(&svm->vcpu))
268 c = &svm->vmcb->control;
269 h = &svm->nested.hsave->control;
272 c->intercept_cr = h->intercept_cr | g->intercept_cr;
273 c->intercept_dr = h->intercept_dr | g->intercept_dr;
274 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
275 c->intercept = h->intercept | g->intercept;
278 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
280 if (is_guest_mode(&svm->vcpu))
281 return svm->nested.hsave;
286 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
288 struct vmcb *vmcb = get_host_vmcb(svm);
290 vmcb->control.intercept_cr |= (1U << bit);
292 recalc_intercepts(svm);
295 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
297 struct vmcb *vmcb = get_host_vmcb(svm);
299 vmcb->control.intercept_cr &= ~(1U << bit);
301 recalc_intercepts(svm);
304 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
306 struct vmcb *vmcb = get_host_vmcb(svm);
308 return vmcb->control.intercept_cr & (1U << bit);
311 static inline void set_dr_intercepts(struct vcpu_svm *svm)
313 struct vmcb *vmcb = get_host_vmcb(svm);
315 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
316 | (1 << INTERCEPT_DR1_READ)
317 | (1 << INTERCEPT_DR2_READ)
318 | (1 << INTERCEPT_DR3_READ)
319 | (1 << INTERCEPT_DR4_READ)
320 | (1 << INTERCEPT_DR5_READ)
321 | (1 << INTERCEPT_DR6_READ)
322 | (1 << INTERCEPT_DR7_READ)
323 | (1 << INTERCEPT_DR0_WRITE)
324 | (1 << INTERCEPT_DR1_WRITE)
325 | (1 << INTERCEPT_DR2_WRITE)
326 | (1 << INTERCEPT_DR3_WRITE)
327 | (1 << INTERCEPT_DR4_WRITE)
328 | (1 << INTERCEPT_DR5_WRITE)
329 | (1 << INTERCEPT_DR6_WRITE)
330 | (1 << INTERCEPT_DR7_WRITE);
332 recalc_intercepts(svm);
335 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
337 struct vmcb *vmcb = get_host_vmcb(svm);
339 vmcb->control.intercept_dr = 0;
341 recalc_intercepts(svm);
344 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
346 struct vmcb *vmcb = get_host_vmcb(svm);
348 vmcb->control.intercept_exceptions |= (1U << bit);
350 recalc_intercepts(svm);
353 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
355 struct vmcb *vmcb = get_host_vmcb(svm);
357 vmcb->control.intercept_exceptions &= ~(1U << bit);
359 recalc_intercepts(svm);
362 static inline void set_intercept(struct vcpu_svm *svm, int bit)
364 struct vmcb *vmcb = get_host_vmcb(svm);
366 vmcb->control.intercept |= (1ULL << bit);
368 recalc_intercepts(svm);
371 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
373 struct vmcb *vmcb = get_host_vmcb(svm);
375 vmcb->control.intercept &= ~(1ULL << bit);
377 recalc_intercepts(svm);
380 static inline void enable_gif(struct vcpu_svm *svm)
382 svm->vcpu.arch.hflags |= HF_GIF_MASK;
385 static inline void disable_gif(struct vcpu_svm *svm)
387 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
390 static inline bool gif_set(struct vcpu_svm *svm)
392 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
395 static unsigned long iopm_base;
397 struct kvm_ldttss_desc {
400 unsigned base1:8, type:5, dpl:2, p:1;
401 unsigned limit1:4, zero0:3, g:1, base2:8;
404 } __attribute__((packed));
406 struct svm_cpu_data {
412 struct kvm_ldttss_desc *tss_desc;
414 struct page *save_area;
417 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
419 struct svm_init_data {
424 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
426 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
427 #define MSRS_RANGE_SIZE 2048
428 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
430 static u32 svm_msrpm_offset(u32 msr)
435 for (i = 0; i < NUM_MSR_MAPS; i++) {
436 if (msr < msrpm_ranges[i] ||
437 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
440 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
441 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
443 /* Now we have the u8 offset - but need the u32 offset */
447 /* MSR not in any range */
451 #define MAX_INST_SIZE 15
453 static inline void clgi(void)
455 asm volatile (__ex(SVM_CLGI));
458 static inline void stgi(void)
460 asm volatile (__ex(SVM_STGI));
463 static inline void invlpga(unsigned long addr, u32 asid)
465 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
468 static int get_npt_level(void)
471 return PT64_ROOT_LEVEL;
473 return PT32E_ROOT_LEVEL;
477 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
479 vcpu->arch.efer = efer;
480 if (!npt_enabled && !(efer & EFER_LMA))
483 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
484 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
487 static int is_external_interrupt(u32 info)
489 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
490 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
493 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
495 struct vcpu_svm *svm = to_svm(vcpu);
498 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
499 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
503 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
505 struct vcpu_svm *svm = to_svm(vcpu);
508 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
510 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
514 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
516 struct vcpu_svm *svm = to_svm(vcpu);
518 if (svm->vmcb->control.next_rip != 0) {
519 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
520 svm->next_rip = svm->vmcb->control.next_rip;
523 if (!svm->next_rip) {
524 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
526 printk(KERN_DEBUG "%s: NOP\n", __func__);
529 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
530 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
531 __func__, kvm_rip_read(vcpu), svm->next_rip);
533 kvm_rip_write(vcpu, svm->next_rip);
534 svm_set_interrupt_shadow(vcpu, 0);
537 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
538 bool has_error_code, u32 error_code,
541 struct vcpu_svm *svm = to_svm(vcpu);
544 * If we are within a nested VM we'd better #VMEXIT and let the guest
545 * handle the exception
548 nested_svm_check_exception(svm, nr, has_error_code, error_code))
551 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
552 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
555 * For guest debugging where we have to reinject #BP if some
556 * INT3 is guest-owned:
557 * Emulate nRIP by moving RIP forward. Will fail if injection
558 * raises a fault that is not intercepted. Still better than
559 * failing in all cases.
561 skip_emulated_instruction(&svm->vcpu);
562 rip = kvm_rip_read(&svm->vcpu);
563 svm->int3_rip = rip + svm->vmcb->save.cs.base;
564 svm->int3_injected = rip - old_rip;
567 svm->vmcb->control.event_inj = nr
569 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
570 | SVM_EVTINJ_TYPE_EXEPT;
571 svm->vmcb->control.event_inj_err = error_code;
574 static void svm_init_erratum_383(void)
580 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
583 /* Use _safe variants to not break nested virtualization */
584 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
590 low = lower_32_bits(val);
591 high = upper_32_bits(val);
593 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
595 erratum_383_found = true;
598 static void svm_init_osvw(struct kvm_vcpu *vcpu)
601 * Guests should see errata 400 and 415 as fixed (assuming that
602 * HLT and IO instructions are intercepted).
604 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
605 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
608 * By increasing VCPU's osvw.length to 3 we are telling the guest that
609 * all osvw.status bits inside that length, including bit 0 (which is
610 * reserved for erratum 298), are valid. However, if host processor's
611 * osvw_len is 0 then osvw_status[0] carries no information. We need to
612 * be conservative here and therefore we tell the guest that erratum 298
613 * is present (because we really don't know).
615 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
616 vcpu->arch.osvw.status |= 1;
619 static int has_svm(void)
623 if (!cpu_has_svm(&msg)) {
624 printk(KERN_INFO "has_svm: %s\n", msg);
631 static void svm_hardware_disable(void)
633 /* Make sure we clean up behind us */
634 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
635 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
639 amd_pmu_disable_virt();
642 static int svm_hardware_enable(void)
645 struct svm_cpu_data *sd;
647 struct desc_ptr gdt_descr;
648 struct desc_struct *gdt;
649 int me = raw_smp_processor_id();
651 rdmsrl(MSR_EFER, efer);
652 if (efer & EFER_SVME)
656 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
659 sd = per_cpu(svm_data, me);
661 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
665 sd->asid_generation = 1;
666 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
667 sd->next_asid = sd->max_asid + 1;
669 native_store_gdt(&gdt_descr);
670 gdt = (struct desc_struct *)gdt_descr.address;
671 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
673 wrmsrl(MSR_EFER, efer | EFER_SVME);
675 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
677 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
678 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
679 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
686 * Note that it is possible to have a system with mixed processor
687 * revisions and therefore different OSVW bits. If bits are not the same
688 * on different processors then choose the worst case (i.e. if erratum
689 * is present on one processor and not on another then assume that the
690 * erratum is present everywhere).
692 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
693 uint64_t len, status = 0;
696 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
698 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
702 osvw_status = osvw_len = 0;
706 osvw_status |= status;
707 osvw_status &= (1ULL << osvw_len) - 1;
710 osvw_status = osvw_len = 0;
712 svm_init_erratum_383();
714 amd_pmu_enable_virt();
719 static void svm_cpu_uninit(int cpu)
721 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
726 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
727 __free_page(sd->save_area);
731 static int svm_cpu_init(int cpu)
733 struct svm_cpu_data *sd;
736 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
740 sd->save_area = alloc_page(GFP_KERNEL);
745 per_cpu(svm_data, cpu) = sd;
755 static bool valid_msr_intercept(u32 index)
759 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
760 if (direct_access_msrs[i].index == index)
766 static void set_msr_interception(u32 *msrpm, unsigned msr,
769 u8 bit_read, bit_write;
774 * If this warning triggers extend the direct_access_msrs list at the
775 * beginning of the file
777 WARN_ON(!valid_msr_intercept(msr));
779 offset = svm_msrpm_offset(msr);
780 bit_read = 2 * (msr & 0x0f);
781 bit_write = 2 * (msr & 0x0f) + 1;
784 BUG_ON(offset == MSR_INVALID);
786 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
787 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
792 static void svm_vcpu_init_msrpm(u32 *msrpm)
796 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
798 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
799 if (!direct_access_msrs[i].always)
802 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
806 static void add_msr_offset(u32 offset)
810 for (i = 0; i < MSRPM_OFFSETS; ++i) {
812 /* Offset already in list? */
813 if (msrpm_offsets[i] == offset)
816 /* Slot used by another offset? */
817 if (msrpm_offsets[i] != MSR_INVALID)
820 /* Add offset to list */
821 msrpm_offsets[i] = offset;
827 * If this BUG triggers the msrpm_offsets table has an overflow. Just
828 * increase MSRPM_OFFSETS in this case.
833 static void init_msrpm_offsets(void)
837 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
839 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
842 offset = svm_msrpm_offset(direct_access_msrs[i].index);
843 BUG_ON(offset == MSR_INVALID);
845 add_msr_offset(offset);
849 static void svm_enable_lbrv(struct vcpu_svm *svm)
851 u32 *msrpm = svm->msrpm;
853 svm->vmcb->control.lbr_ctl = 1;
854 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
855 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
856 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
857 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
860 static void svm_disable_lbrv(struct vcpu_svm *svm)
862 u32 *msrpm = svm->msrpm;
864 svm->vmcb->control.lbr_ctl = 0;
865 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
866 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
867 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
868 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
871 static __init int svm_hardware_setup(void)
874 struct page *iopm_pages;
878 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
883 iopm_va = page_address(iopm_pages);
884 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
885 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
887 init_msrpm_offsets();
889 if (boot_cpu_has(X86_FEATURE_NX))
890 kvm_enable_efer_bits(EFER_NX);
892 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
893 kvm_enable_efer_bits(EFER_FFXSR);
895 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
896 kvm_has_tsc_control = true;
897 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
898 kvm_tsc_scaling_ratio_frac_bits = 32;
902 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
903 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
906 for_each_possible_cpu(cpu) {
907 r = svm_cpu_init(cpu);
912 if (!boot_cpu_has(X86_FEATURE_NPT))
915 if (npt_enabled && !npt) {
916 printk(KERN_INFO "kvm: Nested Paging disabled\n");
921 printk(KERN_INFO "kvm: Nested Paging enabled\n");
929 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
934 static __exit void svm_hardware_unsetup(void)
938 for_each_possible_cpu(cpu)
941 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
945 static void init_seg(struct vmcb_seg *seg)
948 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
949 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
954 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
957 seg->attrib = SVM_SELECTOR_P_MASK | type;
962 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
964 struct vcpu_svm *svm = to_svm(vcpu);
966 return svm->vmcb->control.tsc_offset;
969 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
971 struct vcpu_svm *svm = to_svm(vcpu);
972 u64 g_tsc_offset = 0;
974 if (is_guest_mode(vcpu)) {
975 g_tsc_offset = svm->vmcb->control.tsc_offset -
976 svm->nested.hsave->control.tsc_offset;
977 svm->nested.hsave->control.tsc_offset = offset;
979 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
980 svm->vmcb->control.tsc_offset,
983 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
985 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
988 static void svm_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
990 struct vcpu_svm *svm = to_svm(vcpu);
992 svm->vmcb->control.tsc_offset += adjustment;
993 if (is_guest_mode(vcpu))
994 svm->nested.hsave->control.tsc_offset += adjustment;
996 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
997 svm->vmcb->control.tsc_offset - adjustment,
998 svm->vmcb->control.tsc_offset);
1000 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1003 static void init_vmcb(struct vcpu_svm *svm)
1005 struct vmcb_control_area *control = &svm->vmcb->control;
1006 struct vmcb_save_area *save = &svm->vmcb->save;
1008 svm->vcpu.fpu_active = 1;
1009 svm->vcpu.arch.hflags = 0;
1011 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1012 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1013 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1014 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1015 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1016 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1017 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1019 set_dr_intercepts(svm);
1021 set_exception_intercept(svm, PF_VECTOR);
1022 set_exception_intercept(svm, UD_VECTOR);
1023 set_exception_intercept(svm, MC_VECTOR);
1024 set_exception_intercept(svm, AC_VECTOR);
1025 set_exception_intercept(svm, DB_VECTOR);
1027 set_intercept(svm, INTERCEPT_INTR);
1028 set_intercept(svm, INTERCEPT_NMI);
1029 set_intercept(svm, INTERCEPT_SMI);
1030 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1031 set_intercept(svm, INTERCEPT_RDPMC);
1032 set_intercept(svm, INTERCEPT_CPUID);
1033 set_intercept(svm, INTERCEPT_INVD);
1034 set_intercept(svm, INTERCEPT_HLT);
1035 set_intercept(svm, INTERCEPT_INVLPG);
1036 set_intercept(svm, INTERCEPT_INVLPGA);
1037 set_intercept(svm, INTERCEPT_IOIO_PROT);
1038 set_intercept(svm, INTERCEPT_MSR_PROT);
1039 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1040 set_intercept(svm, INTERCEPT_SHUTDOWN);
1041 set_intercept(svm, INTERCEPT_VMRUN);
1042 set_intercept(svm, INTERCEPT_VMMCALL);
1043 set_intercept(svm, INTERCEPT_VMLOAD);
1044 set_intercept(svm, INTERCEPT_VMSAVE);
1045 set_intercept(svm, INTERCEPT_STGI);
1046 set_intercept(svm, INTERCEPT_CLGI);
1047 set_intercept(svm, INTERCEPT_SKINIT);
1048 set_intercept(svm, INTERCEPT_WBINVD);
1049 set_intercept(svm, INTERCEPT_MONITOR);
1050 set_intercept(svm, INTERCEPT_MWAIT);
1051 set_intercept(svm, INTERCEPT_XSETBV);
1053 control->iopm_base_pa = iopm_base;
1054 control->msrpm_base_pa = __pa(svm->msrpm);
1055 control->int_ctl = V_INTR_MASKING_MASK;
1057 init_seg(&save->es);
1058 init_seg(&save->ss);
1059 init_seg(&save->ds);
1060 init_seg(&save->fs);
1061 init_seg(&save->gs);
1063 save->cs.selector = 0xf000;
1064 save->cs.base = 0xffff0000;
1065 /* Executable/Readable Code Segment */
1066 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1067 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1068 save->cs.limit = 0xffff;
1070 save->gdtr.limit = 0xffff;
1071 save->idtr.limit = 0xffff;
1073 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1074 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1076 svm_set_efer(&svm->vcpu, 0);
1077 save->dr6 = 0xffff0ff0;
1078 kvm_set_rflags(&svm->vcpu, 2);
1079 save->rip = 0x0000fff0;
1080 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1083 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1084 * It also updates the guest-visible cr0 value.
1086 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1087 kvm_mmu_reset_context(&svm->vcpu);
1089 save->cr4 = X86_CR4_PAE;
1093 /* Setup VMCB for Nested Paging */
1094 control->nested_ctl = 1;
1095 clr_intercept(svm, INTERCEPT_INVLPG);
1096 clr_exception_intercept(svm, PF_VECTOR);
1097 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1098 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1099 save->g_pat = svm->vcpu.arch.pat;
1103 svm->asid_generation = 0;
1105 svm->nested.vmcb = 0;
1106 svm->vcpu.arch.hflags = 0;
1108 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1109 control->pause_filter_count = 3000;
1110 set_intercept(svm, INTERCEPT_PAUSE);
1113 mark_all_dirty(svm->vmcb);
1118 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1120 struct vcpu_svm *svm = to_svm(vcpu);
1125 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1126 MSR_IA32_APICBASE_ENABLE;
1127 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1128 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1132 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1133 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1136 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1138 struct vcpu_svm *svm;
1140 struct page *msrpm_pages;
1141 struct page *hsave_page;
1142 struct page *nested_msrpm_pages;
1145 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1151 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1156 page = alloc_page(GFP_KERNEL);
1160 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1164 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1165 if (!nested_msrpm_pages)
1168 hsave_page = alloc_page(GFP_KERNEL);
1172 svm->nested.hsave = page_address(hsave_page);
1174 svm->msrpm = page_address(msrpm_pages);
1175 svm_vcpu_init_msrpm(svm->msrpm);
1177 svm->nested.msrpm = page_address(nested_msrpm_pages);
1178 svm_vcpu_init_msrpm(svm->nested.msrpm);
1180 svm->vmcb = page_address(page);
1181 clear_page(svm->vmcb);
1182 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1183 svm->asid_generation = 0;
1186 svm_init_osvw(&svm->vcpu);
1191 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1193 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1197 kvm_vcpu_uninit(&svm->vcpu);
1199 kmem_cache_free(kvm_vcpu_cache, svm);
1201 return ERR_PTR(err);
1204 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1206 struct vcpu_svm *svm = to_svm(vcpu);
1208 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1209 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1210 __free_page(virt_to_page(svm->nested.hsave));
1211 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1212 kvm_vcpu_uninit(vcpu);
1213 kmem_cache_free(kvm_vcpu_cache, svm);
1216 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1218 struct vcpu_svm *svm = to_svm(vcpu);
1221 if (unlikely(cpu != vcpu->cpu)) {
1222 svm->asid_generation = 0;
1223 mark_all_dirty(svm->vmcb);
1226 #ifdef CONFIG_X86_64
1227 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1229 savesegment(fs, svm->host.fs);
1230 savesegment(gs, svm->host.gs);
1231 svm->host.ldt = kvm_read_ldt();
1233 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1234 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1236 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1237 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1238 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1239 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1240 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1243 /* This assumes that the kernel never uses MSR_TSC_AUX */
1244 if (static_cpu_has(X86_FEATURE_RDTSCP))
1245 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1248 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1250 struct vcpu_svm *svm = to_svm(vcpu);
1253 ++vcpu->stat.host_state_reload;
1254 kvm_load_ldt(svm->host.ldt);
1255 #ifdef CONFIG_X86_64
1256 loadsegment(fs, svm->host.fs);
1257 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1258 load_gs_index(svm->host.gs);
1260 #ifdef CONFIG_X86_32_LAZY_GS
1261 loadsegment(gs, svm->host.gs);
1264 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1265 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1268 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1270 return to_svm(vcpu)->vmcb->save.rflags;
1273 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1276 * Any change of EFLAGS.VM is accompained by a reload of SS
1277 * (caused by either a task switch or an inter-privilege IRET),
1278 * so we do not need to update the CPL here.
1280 to_svm(vcpu)->vmcb->save.rflags = rflags;
1283 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1286 case VCPU_EXREG_PDPTR:
1287 BUG_ON(!npt_enabled);
1288 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1295 static void svm_set_vintr(struct vcpu_svm *svm)
1297 set_intercept(svm, INTERCEPT_VINTR);
1300 static void svm_clear_vintr(struct vcpu_svm *svm)
1302 clr_intercept(svm, INTERCEPT_VINTR);
1305 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1307 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1310 case VCPU_SREG_CS: return &save->cs;
1311 case VCPU_SREG_DS: return &save->ds;
1312 case VCPU_SREG_ES: return &save->es;
1313 case VCPU_SREG_FS: return &save->fs;
1314 case VCPU_SREG_GS: return &save->gs;
1315 case VCPU_SREG_SS: return &save->ss;
1316 case VCPU_SREG_TR: return &save->tr;
1317 case VCPU_SREG_LDTR: return &save->ldtr;
1323 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1325 struct vmcb_seg *s = svm_seg(vcpu, seg);
1330 static void svm_get_segment(struct kvm_vcpu *vcpu,
1331 struct kvm_segment *var, int seg)
1333 struct vmcb_seg *s = svm_seg(vcpu, seg);
1335 var->base = s->base;
1336 var->limit = s->limit;
1337 var->selector = s->selector;
1338 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1339 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1340 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1341 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1342 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1343 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1344 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1347 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1348 * However, the SVM spec states that the G bit is not observed by the
1349 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1350 * So let's synthesize a legal G bit for all segments, this helps
1351 * running KVM nested. It also helps cross-vendor migration, because
1352 * Intel's vmentry has a check on the 'G' bit.
1354 var->g = s->limit > 0xfffff;
1357 * AMD's VMCB does not have an explicit unusable field, so emulate it
1358 * for cross vendor migration purposes by "not present"
1360 var->unusable = !var->present || (var->type == 0);
1365 * Work around a bug where the busy flag in the tr selector
1375 * The accessed bit must always be set in the segment
1376 * descriptor cache, although it can be cleared in the
1377 * descriptor, the cached bit always remains at 1. Since
1378 * Intel has a check on this, set it here to support
1379 * cross-vendor migration.
1386 * On AMD CPUs sometimes the DB bit in the segment
1387 * descriptor is left as 1, although the whole segment has
1388 * been made unusable. Clear it here to pass an Intel VMX
1389 * entry check when cross vendor migrating.
1393 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1398 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1400 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1405 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1407 struct vcpu_svm *svm = to_svm(vcpu);
1409 dt->size = svm->vmcb->save.idtr.limit;
1410 dt->address = svm->vmcb->save.idtr.base;
1413 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1415 struct vcpu_svm *svm = to_svm(vcpu);
1417 svm->vmcb->save.idtr.limit = dt->size;
1418 svm->vmcb->save.idtr.base = dt->address ;
1419 mark_dirty(svm->vmcb, VMCB_DT);
1422 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1424 struct vcpu_svm *svm = to_svm(vcpu);
1426 dt->size = svm->vmcb->save.gdtr.limit;
1427 dt->address = svm->vmcb->save.gdtr.base;
1430 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1432 struct vcpu_svm *svm = to_svm(vcpu);
1434 svm->vmcb->save.gdtr.limit = dt->size;
1435 svm->vmcb->save.gdtr.base = dt->address ;
1436 mark_dirty(svm->vmcb, VMCB_DT);
1439 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1443 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1447 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1451 static void update_cr0_intercept(struct vcpu_svm *svm)
1453 ulong gcr0 = svm->vcpu.arch.cr0;
1454 u64 *hcr0 = &svm->vmcb->save.cr0;
1456 if (!svm->vcpu.fpu_active)
1457 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1459 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1460 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1462 mark_dirty(svm->vmcb, VMCB_CR);
1464 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1465 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1466 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1468 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1469 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1473 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1475 struct vcpu_svm *svm = to_svm(vcpu);
1477 #ifdef CONFIG_X86_64
1478 if (vcpu->arch.efer & EFER_LME) {
1479 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1480 vcpu->arch.efer |= EFER_LMA;
1481 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1484 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1485 vcpu->arch.efer &= ~EFER_LMA;
1486 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1490 vcpu->arch.cr0 = cr0;
1493 cr0 |= X86_CR0_PG | X86_CR0_WP;
1495 if (!vcpu->fpu_active)
1498 * re-enable caching here because the QEMU bios
1499 * does not do it - this results in some delay at
1502 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1503 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1504 svm->vmcb->save.cr0 = cr0;
1505 mark_dirty(svm->vmcb, VMCB_CR);
1506 update_cr0_intercept(svm);
1509 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1511 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1512 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1514 if (cr4 & X86_CR4_VMXE)
1517 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1518 svm_flush_tlb(vcpu);
1520 vcpu->arch.cr4 = cr4;
1523 cr4 |= host_cr4_mce;
1524 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1525 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1529 static void svm_set_segment(struct kvm_vcpu *vcpu,
1530 struct kvm_segment *var, int seg)
1532 struct vcpu_svm *svm = to_svm(vcpu);
1533 struct vmcb_seg *s = svm_seg(vcpu, seg);
1535 s->base = var->base;
1536 s->limit = var->limit;
1537 s->selector = var->selector;
1541 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1542 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1543 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1544 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1545 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1546 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1547 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1548 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1552 * This is always accurate, except if SYSRET returned to a segment
1553 * with SS.DPL != 3. Intel does not have this quirk, and always
1554 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1555 * would entail passing the CPL to userspace and back.
1557 if (seg == VCPU_SREG_SS)
1558 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1560 mark_dirty(svm->vmcb, VMCB_SEG);
1563 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1565 struct vcpu_svm *svm = to_svm(vcpu);
1567 clr_exception_intercept(svm, BP_VECTOR);
1569 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1570 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1571 set_exception_intercept(svm, BP_VECTOR);
1573 vcpu->guest_debug = 0;
1576 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1578 if (sd->next_asid > sd->max_asid) {
1579 ++sd->asid_generation;
1581 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1584 svm->asid_generation = sd->asid_generation;
1585 svm->vmcb->control.asid = sd->next_asid++;
1587 mark_dirty(svm->vmcb, VMCB_ASID);
1590 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1592 return to_svm(vcpu)->vmcb->save.dr6;
1595 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1597 struct vcpu_svm *svm = to_svm(vcpu);
1599 svm->vmcb->save.dr6 = value;
1600 mark_dirty(svm->vmcb, VMCB_DR);
1603 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1605 struct vcpu_svm *svm = to_svm(vcpu);
1607 get_debugreg(vcpu->arch.db[0], 0);
1608 get_debugreg(vcpu->arch.db[1], 1);
1609 get_debugreg(vcpu->arch.db[2], 2);
1610 get_debugreg(vcpu->arch.db[3], 3);
1611 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1612 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1614 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1615 set_dr_intercepts(svm);
1618 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1620 struct vcpu_svm *svm = to_svm(vcpu);
1622 svm->vmcb->save.dr7 = value;
1623 mark_dirty(svm->vmcb, VMCB_DR);
1626 static int pf_interception(struct vcpu_svm *svm)
1628 u64 fault_address = svm->vmcb->control.exit_info_2;
1632 switch (svm->apf_reason) {
1634 error_code = svm->vmcb->control.exit_info_1;
1636 trace_kvm_page_fault(fault_address, error_code);
1637 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1638 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1639 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1640 svm->vmcb->control.insn_bytes,
1641 svm->vmcb->control.insn_len);
1643 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1644 svm->apf_reason = 0;
1645 local_irq_disable();
1646 kvm_async_pf_task_wait(fault_address);
1649 case KVM_PV_REASON_PAGE_READY:
1650 svm->apf_reason = 0;
1651 local_irq_disable();
1652 kvm_async_pf_task_wake(fault_address);
1659 static int db_interception(struct vcpu_svm *svm)
1661 struct kvm_run *kvm_run = svm->vcpu.run;
1663 if (!(svm->vcpu.guest_debug &
1664 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1665 !svm->nmi_singlestep) {
1666 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1670 if (svm->nmi_singlestep) {
1671 svm->nmi_singlestep = false;
1672 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1673 svm->vmcb->save.rflags &=
1674 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1677 if (svm->vcpu.guest_debug &
1678 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1679 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1680 kvm_run->debug.arch.pc =
1681 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1682 kvm_run->debug.arch.exception = DB_VECTOR;
1689 static int bp_interception(struct vcpu_svm *svm)
1691 struct kvm_run *kvm_run = svm->vcpu.run;
1693 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1694 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1695 kvm_run->debug.arch.exception = BP_VECTOR;
1699 static int ud_interception(struct vcpu_svm *svm)
1703 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1704 if (er != EMULATE_DONE)
1705 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1709 static int ac_interception(struct vcpu_svm *svm)
1711 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1715 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1717 struct vcpu_svm *svm = to_svm(vcpu);
1719 clr_exception_intercept(svm, NM_VECTOR);
1721 svm->vcpu.fpu_active = 1;
1722 update_cr0_intercept(svm);
1725 static int nm_interception(struct vcpu_svm *svm)
1727 svm_fpu_activate(&svm->vcpu);
1731 static bool is_erratum_383(void)
1736 if (!erratum_383_found)
1739 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1743 /* Bit 62 may or may not be set for this mce */
1744 value &= ~(1ULL << 62);
1746 if (value != 0xb600000000010015ULL)
1749 /* Clear MCi_STATUS registers */
1750 for (i = 0; i < 6; ++i)
1751 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1753 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1757 value &= ~(1ULL << 2);
1758 low = lower_32_bits(value);
1759 high = upper_32_bits(value);
1761 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1764 /* Flush tlb to evict multi-match entries */
1770 static void svm_handle_mce(struct vcpu_svm *svm)
1772 if (is_erratum_383()) {
1774 * Erratum 383 triggered. Guest state is corrupt so kill the
1777 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1779 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1785 * On an #MC intercept the MCE handler is not called automatically in
1786 * the host. So do it by hand here.
1790 /* not sure if we ever come back to this point */
1795 static int mc_interception(struct vcpu_svm *svm)
1800 static int shutdown_interception(struct vcpu_svm *svm)
1802 struct kvm_run *kvm_run = svm->vcpu.run;
1805 * VMCB is undefined after a SHUTDOWN intercept
1806 * so reinitialize it.
1808 clear_page(svm->vmcb);
1811 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1815 static int io_interception(struct vcpu_svm *svm)
1817 struct kvm_vcpu *vcpu = &svm->vcpu;
1818 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1819 int size, in, string;
1822 ++svm->vcpu.stat.io_exits;
1823 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1824 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1826 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1828 port = io_info >> 16;
1829 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1830 svm->next_rip = svm->vmcb->control.exit_info_2;
1831 skip_emulated_instruction(&svm->vcpu);
1833 return kvm_fast_pio_out(vcpu, size, port);
1836 static int nmi_interception(struct vcpu_svm *svm)
1841 static int intr_interception(struct vcpu_svm *svm)
1843 ++svm->vcpu.stat.irq_exits;
1847 static int nop_on_interception(struct vcpu_svm *svm)
1852 static int halt_interception(struct vcpu_svm *svm)
1854 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1855 return kvm_emulate_halt(&svm->vcpu);
1858 static int vmmcall_interception(struct vcpu_svm *svm)
1860 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1861 kvm_emulate_hypercall(&svm->vcpu);
1865 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1867 struct vcpu_svm *svm = to_svm(vcpu);
1869 return svm->nested.nested_cr3;
1872 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1874 struct vcpu_svm *svm = to_svm(vcpu);
1875 u64 cr3 = svm->nested.nested_cr3;
1879 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
1880 offset_in_page(cr3) + index * 8, 8);
1886 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1889 struct vcpu_svm *svm = to_svm(vcpu);
1891 svm->vmcb->control.nested_cr3 = root;
1892 mark_dirty(svm->vmcb, VMCB_NPT);
1893 svm_flush_tlb(vcpu);
1896 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1897 struct x86_exception *fault)
1899 struct vcpu_svm *svm = to_svm(vcpu);
1901 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
1903 * TODO: track the cause of the nested page fault, and
1904 * correctly fill in the high bits of exit_info_1.
1906 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1907 svm->vmcb->control.exit_code_hi = 0;
1908 svm->vmcb->control.exit_info_1 = (1ULL << 32);
1909 svm->vmcb->control.exit_info_2 = fault->address;
1912 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
1913 svm->vmcb->control.exit_info_1 |= fault->error_code;
1916 * The present bit is always zero for page structure faults on real
1919 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
1920 svm->vmcb->control.exit_info_1 &= ~1;
1922 nested_svm_vmexit(svm);
1925 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1927 WARN_ON(mmu_is_nested(vcpu));
1928 kvm_init_shadow_mmu(vcpu);
1929 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1930 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1931 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1932 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1933 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1934 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
1935 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1938 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1940 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1943 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1945 if (!(svm->vcpu.arch.efer & EFER_SVME)
1946 || !is_paging(&svm->vcpu)) {
1947 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1951 if (svm->vmcb->save.cpl) {
1952 kvm_inject_gp(&svm->vcpu, 0);
1959 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1960 bool has_error_code, u32 error_code)
1964 if (!is_guest_mode(&svm->vcpu))
1967 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1968 svm->vmcb->control.exit_code_hi = 0;
1969 svm->vmcb->control.exit_info_1 = error_code;
1970 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1972 vmexit = nested_svm_intercept(svm);
1973 if (vmexit == NESTED_EXIT_DONE)
1974 svm->nested.exit_required = true;
1979 /* This function returns true if it is save to enable the irq window */
1980 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1982 if (!is_guest_mode(&svm->vcpu))
1985 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1988 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1992 * if vmexit was already requested (by intercepted exception
1993 * for instance) do not overwrite it with "external interrupt"
1996 if (svm->nested.exit_required)
1999 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2000 svm->vmcb->control.exit_info_1 = 0;
2001 svm->vmcb->control.exit_info_2 = 0;
2003 if (svm->nested.intercept & 1ULL) {
2005 * The #vmexit can't be emulated here directly because this
2006 * code path runs with irqs and preemption disabled. A
2007 * #vmexit emulation might sleep. Only signal request for
2010 svm->nested.exit_required = true;
2011 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2018 /* This function returns true if it is save to enable the nmi window */
2019 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2021 if (!is_guest_mode(&svm->vcpu))
2024 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2027 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2028 svm->nested.exit_required = true;
2033 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2039 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2040 if (is_error_page(page))
2048 kvm_inject_gp(&svm->vcpu, 0);
2053 static void nested_svm_unmap(struct page *page)
2056 kvm_release_page_dirty(page);
2059 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2061 unsigned port, size, iopm_len;
2066 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2067 return NESTED_EXIT_HOST;
2069 port = svm->vmcb->control.exit_info_1 >> 16;
2070 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2071 SVM_IOIO_SIZE_SHIFT;
2072 gpa = svm->nested.vmcb_iopm + (port / 8);
2073 start_bit = port % 8;
2074 iopm_len = (start_bit + size > 8) ? 2 : 1;
2075 mask = (0xf >> (4 - size)) << start_bit;
2078 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2079 return NESTED_EXIT_DONE;
2081 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2084 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2086 u32 offset, msr, value;
2089 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2090 return NESTED_EXIT_HOST;
2092 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2093 offset = svm_msrpm_offset(msr);
2094 write = svm->vmcb->control.exit_info_1 & 1;
2095 mask = 1 << ((2 * (msr & 0xf)) + write);
2097 if (offset == MSR_INVALID)
2098 return NESTED_EXIT_DONE;
2100 /* Offset is in 32 bit units but need in 8 bit units */
2103 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2104 return NESTED_EXIT_DONE;
2106 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2109 static int nested_svm_exit_special(struct vcpu_svm *svm)
2111 u32 exit_code = svm->vmcb->control.exit_code;
2113 switch (exit_code) {
2116 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2117 return NESTED_EXIT_HOST;
2119 /* For now we are always handling NPFs when using them */
2121 return NESTED_EXIT_HOST;
2123 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2124 /* When we're shadowing, trap PFs, but not async PF */
2125 if (!npt_enabled && svm->apf_reason == 0)
2126 return NESTED_EXIT_HOST;
2128 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2129 nm_interception(svm);
2135 return NESTED_EXIT_CONTINUE;
2139 * If this function returns true, this #vmexit was already handled
2141 static int nested_svm_intercept(struct vcpu_svm *svm)
2143 u32 exit_code = svm->vmcb->control.exit_code;
2144 int vmexit = NESTED_EXIT_HOST;
2146 switch (exit_code) {
2148 vmexit = nested_svm_exit_handled_msr(svm);
2151 vmexit = nested_svm_intercept_ioio(svm);
2153 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2154 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2155 if (svm->nested.intercept_cr & bit)
2156 vmexit = NESTED_EXIT_DONE;
2159 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2160 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2161 if (svm->nested.intercept_dr & bit)
2162 vmexit = NESTED_EXIT_DONE;
2165 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2166 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2167 if (svm->nested.intercept_exceptions & excp_bits)
2168 vmexit = NESTED_EXIT_DONE;
2169 /* async page fault always cause vmexit */
2170 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2171 svm->apf_reason != 0)
2172 vmexit = NESTED_EXIT_DONE;
2175 case SVM_EXIT_ERR: {
2176 vmexit = NESTED_EXIT_DONE;
2180 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2181 if (svm->nested.intercept & exit_bits)
2182 vmexit = NESTED_EXIT_DONE;
2189 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2193 vmexit = nested_svm_intercept(svm);
2195 if (vmexit == NESTED_EXIT_DONE)
2196 nested_svm_vmexit(svm);
2201 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2203 struct vmcb_control_area *dst = &dst_vmcb->control;
2204 struct vmcb_control_area *from = &from_vmcb->control;
2206 dst->intercept_cr = from->intercept_cr;
2207 dst->intercept_dr = from->intercept_dr;
2208 dst->intercept_exceptions = from->intercept_exceptions;
2209 dst->intercept = from->intercept;
2210 dst->iopm_base_pa = from->iopm_base_pa;
2211 dst->msrpm_base_pa = from->msrpm_base_pa;
2212 dst->tsc_offset = from->tsc_offset;
2213 dst->asid = from->asid;
2214 dst->tlb_ctl = from->tlb_ctl;
2215 dst->int_ctl = from->int_ctl;
2216 dst->int_vector = from->int_vector;
2217 dst->int_state = from->int_state;
2218 dst->exit_code = from->exit_code;
2219 dst->exit_code_hi = from->exit_code_hi;
2220 dst->exit_info_1 = from->exit_info_1;
2221 dst->exit_info_2 = from->exit_info_2;
2222 dst->exit_int_info = from->exit_int_info;
2223 dst->exit_int_info_err = from->exit_int_info_err;
2224 dst->nested_ctl = from->nested_ctl;
2225 dst->event_inj = from->event_inj;
2226 dst->event_inj_err = from->event_inj_err;
2227 dst->nested_cr3 = from->nested_cr3;
2228 dst->lbr_ctl = from->lbr_ctl;
2231 static int nested_svm_vmexit(struct vcpu_svm *svm)
2233 struct vmcb *nested_vmcb;
2234 struct vmcb *hsave = svm->nested.hsave;
2235 struct vmcb *vmcb = svm->vmcb;
2238 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2239 vmcb->control.exit_info_1,
2240 vmcb->control.exit_info_2,
2241 vmcb->control.exit_int_info,
2242 vmcb->control.exit_int_info_err,
2245 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2249 /* Exit Guest-Mode */
2250 leave_guest_mode(&svm->vcpu);
2251 svm->nested.vmcb = 0;
2253 /* Give the current vmcb to the guest */
2256 nested_vmcb->save.es = vmcb->save.es;
2257 nested_vmcb->save.cs = vmcb->save.cs;
2258 nested_vmcb->save.ss = vmcb->save.ss;
2259 nested_vmcb->save.ds = vmcb->save.ds;
2260 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2261 nested_vmcb->save.idtr = vmcb->save.idtr;
2262 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2263 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2264 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2265 nested_vmcb->save.cr2 = vmcb->save.cr2;
2266 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2267 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2268 nested_vmcb->save.rip = vmcb->save.rip;
2269 nested_vmcb->save.rsp = vmcb->save.rsp;
2270 nested_vmcb->save.rax = vmcb->save.rax;
2271 nested_vmcb->save.dr7 = vmcb->save.dr7;
2272 nested_vmcb->save.dr6 = vmcb->save.dr6;
2273 nested_vmcb->save.cpl = vmcb->save.cpl;
2275 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2276 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2277 nested_vmcb->control.int_state = vmcb->control.int_state;
2278 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2279 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2280 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2281 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2282 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2283 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2285 if (svm->nrips_enabled)
2286 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2289 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2290 * to make sure that we do not lose injected events. So check event_inj
2291 * here and copy it to exit_int_info if it is valid.
2292 * Exit_int_info and event_inj can't be both valid because the case
2293 * below only happens on a VMRUN instruction intercept which has
2294 * no valid exit_int_info set.
2296 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2297 struct vmcb_control_area *nc = &nested_vmcb->control;
2299 nc->exit_int_info = vmcb->control.event_inj;
2300 nc->exit_int_info_err = vmcb->control.event_inj_err;
2303 nested_vmcb->control.tlb_ctl = 0;
2304 nested_vmcb->control.event_inj = 0;
2305 nested_vmcb->control.event_inj_err = 0;
2307 /* We always set V_INTR_MASKING and remember the old value in hflags */
2308 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2309 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2311 /* Restore the original control entries */
2312 copy_vmcb_control_area(vmcb, hsave);
2314 kvm_clear_exception_queue(&svm->vcpu);
2315 kvm_clear_interrupt_queue(&svm->vcpu);
2317 svm->nested.nested_cr3 = 0;
2319 /* Restore selected save entries */
2320 svm->vmcb->save.es = hsave->save.es;
2321 svm->vmcb->save.cs = hsave->save.cs;
2322 svm->vmcb->save.ss = hsave->save.ss;
2323 svm->vmcb->save.ds = hsave->save.ds;
2324 svm->vmcb->save.gdtr = hsave->save.gdtr;
2325 svm->vmcb->save.idtr = hsave->save.idtr;
2326 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2327 svm_set_efer(&svm->vcpu, hsave->save.efer);
2328 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2329 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2331 svm->vmcb->save.cr3 = hsave->save.cr3;
2332 svm->vcpu.arch.cr3 = hsave->save.cr3;
2334 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2336 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2337 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2338 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2339 svm->vmcb->save.dr7 = 0;
2340 svm->vmcb->save.cpl = 0;
2341 svm->vmcb->control.exit_int_info = 0;
2343 mark_all_dirty(svm->vmcb);
2345 nested_svm_unmap(page);
2347 nested_svm_uninit_mmu_context(&svm->vcpu);
2348 kvm_mmu_reset_context(&svm->vcpu);
2349 kvm_mmu_load(&svm->vcpu);
2354 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2357 * This function merges the msr permission bitmaps of kvm and the
2358 * nested vmcb. It is optimized in that it only merges the parts where
2359 * the kvm msr permission bitmap may contain zero bits
2363 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2366 for (i = 0; i < MSRPM_OFFSETS; i++) {
2370 if (msrpm_offsets[i] == 0xffffffff)
2373 p = msrpm_offsets[i];
2374 offset = svm->nested.vmcb_msrpm + (p * 4);
2376 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2379 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2382 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2387 static bool nested_vmcb_checks(struct vmcb *vmcb)
2389 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2392 if (vmcb->control.asid == 0)
2395 if (vmcb->control.nested_ctl && !npt_enabled)
2401 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2403 struct vmcb *nested_vmcb;
2404 struct vmcb *hsave = svm->nested.hsave;
2405 struct vmcb *vmcb = svm->vmcb;
2409 vmcb_gpa = svm->vmcb->save.rax;
2411 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2415 if (!nested_vmcb_checks(nested_vmcb)) {
2416 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2417 nested_vmcb->control.exit_code_hi = 0;
2418 nested_vmcb->control.exit_info_1 = 0;
2419 nested_vmcb->control.exit_info_2 = 0;
2421 nested_svm_unmap(page);
2426 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2427 nested_vmcb->save.rip,
2428 nested_vmcb->control.int_ctl,
2429 nested_vmcb->control.event_inj,
2430 nested_vmcb->control.nested_ctl);
2432 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2433 nested_vmcb->control.intercept_cr >> 16,
2434 nested_vmcb->control.intercept_exceptions,
2435 nested_vmcb->control.intercept);
2437 /* Clear internal status */
2438 kvm_clear_exception_queue(&svm->vcpu);
2439 kvm_clear_interrupt_queue(&svm->vcpu);
2442 * Save the old vmcb, so we don't need to pick what we save, but can
2443 * restore everything when a VMEXIT occurs
2445 hsave->save.es = vmcb->save.es;
2446 hsave->save.cs = vmcb->save.cs;
2447 hsave->save.ss = vmcb->save.ss;
2448 hsave->save.ds = vmcb->save.ds;
2449 hsave->save.gdtr = vmcb->save.gdtr;
2450 hsave->save.idtr = vmcb->save.idtr;
2451 hsave->save.efer = svm->vcpu.arch.efer;
2452 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2453 hsave->save.cr4 = svm->vcpu.arch.cr4;
2454 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2455 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2456 hsave->save.rsp = vmcb->save.rsp;
2457 hsave->save.rax = vmcb->save.rax;
2459 hsave->save.cr3 = vmcb->save.cr3;
2461 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2463 copy_vmcb_control_area(hsave, vmcb);
2465 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2466 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2468 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2470 if (nested_vmcb->control.nested_ctl) {
2471 kvm_mmu_unload(&svm->vcpu);
2472 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2473 nested_svm_init_mmu_context(&svm->vcpu);
2476 /* Load the nested guest state */
2477 svm->vmcb->save.es = nested_vmcb->save.es;
2478 svm->vmcb->save.cs = nested_vmcb->save.cs;
2479 svm->vmcb->save.ss = nested_vmcb->save.ss;
2480 svm->vmcb->save.ds = nested_vmcb->save.ds;
2481 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2482 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2483 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2484 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2485 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2486 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2488 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2489 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2491 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2493 /* Guest paging mode is active - reset mmu */
2494 kvm_mmu_reset_context(&svm->vcpu);
2496 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2497 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2498 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2499 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2501 /* In case we don't even reach vcpu_run, the fields are not updated */
2502 svm->vmcb->save.rax = nested_vmcb->save.rax;
2503 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2504 svm->vmcb->save.rip = nested_vmcb->save.rip;
2505 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2506 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2507 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2509 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2510 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2512 /* cache intercepts */
2513 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2514 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2515 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2516 svm->nested.intercept = nested_vmcb->control.intercept;
2518 svm_flush_tlb(&svm->vcpu);
2519 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2520 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2521 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2523 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2525 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2526 /* We only want the cr8 intercept bits of the guest */
2527 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2528 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2531 /* We don't want to see VMMCALLs from a nested guest */
2532 clr_intercept(svm, INTERCEPT_VMMCALL);
2534 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2535 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2536 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2537 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2538 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2539 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2541 nested_svm_unmap(page);
2543 /* Enter Guest-Mode */
2544 enter_guest_mode(&svm->vcpu);
2547 * Merge guest and host intercepts - must be called with vcpu in
2548 * guest-mode to take affect here
2550 recalc_intercepts(svm);
2552 svm->nested.vmcb = vmcb_gpa;
2556 mark_all_dirty(svm->vmcb);
2561 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2563 to_vmcb->save.fs = from_vmcb->save.fs;
2564 to_vmcb->save.gs = from_vmcb->save.gs;
2565 to_vmcb->save.tr = from_vmcb->save.tr;
2566 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2567 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2568 to_vmcb->save.star = from_vmcb->save.star;
2569 to_vmcb->save.lstar = from_vmcb->save.lstar;
2570 to_vmcb->save.cstar = from_vmcb->save.cstar;
2571 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2572 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2573 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2574 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2577 static int vmload_interception(struct vcpu_svm *svm)
2579 struct vmcb *nested_vmcb;
2582 if (nested_svm_check_permissions(svm))
2585 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2589 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2590 skip_emulated_instruction(&svm->vcpu);
2592 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2593 nested_svm_unmap(page);
2598 static int vmsave_interception(struct vcpu_svm *svm)
2600 struct vmcb *nested_vmcb;
2603 if (nested_svm_check_permissions(svm))
2606 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2610 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2611 skip_emulated_instruction(&svm->vcpu);
2613 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2614 nested_svm_unmap(page);
2619 static int vmrun_interception(struct vcpu_svm *svm)
2621 if (nested_svm_check_permissions(svm))
2624 /* Save rip after vmrun instruction */
2625 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2627 if (!nested_svm_vmrun(svm))
2630 if (!nested_svm_vmrun_msrpm(svm))
2637 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2638 svm->vmcb->control.exit_code_hi = 0;
2639 svm->vmcb->control.exit_info_1 = 0;
2640 svm->vmcb->control.exit_info_2 = 0;
2642 nested_svm_vmexit(svm);
2647 static int stgi_interception(struct vcpu_svm *svm)
2649 if (nested_svm_check_permissions(svm))
2652 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2653 skip_emulated_instruction(&svm->vcpu);
2654 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2661 static int clgi_interception(struct vcpu_svm *svm)
2663 if (nested_svm_check_permissions(svm))
2666 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2667 skip_emulated_instruction(&svm->vcpu);
2671 /* After a CLGI no interrupts should come */
2672 svm_clear_vintr(svm);
2673 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2675 mark_dirty(svm->vmcb, VMCB_INTR);
2680 static int invlpga_interception(struct vcpu_svm *svm)
2682 struct kvm_vcpu *vcpu = &svm->vcpu;
2684 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
2685 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2687 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2688 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2690 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2691 skip_emulated_instruction(&svm->vcpu);
2695 static int skinit_interception(struct vcpu_svm *svm)
2697 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
2699 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2703 static int wbinvd_interception(struct vcpu_svm *svm)
2705 kvm_emulate_wbinvd(&svm->vcpu);
2709 static int xsetbv_interception(struct vcpu_svm *svm)
2711 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2712 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2714 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2715 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2716 skip_emulated_instruction(&svm->vcpu);
2722 static int task_switch_interception(struct vcpu_svm *svm)
2726 int int_type = svm->vmcb->control.exit_int_info &
2727 SVM_EXITINTINFO_TYPE_MASK;
2728 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2730 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2732 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2733 bool has_error_code = false;
2736 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2738 if (svm->vmcb->control.exit_info_2 &
2739 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2740 reason = TASK_SWITCH_IRET;
2741 else if (svm->vmcb->control.exit_info_2 &
2742 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2743 reason = TASK_SWITCH_JMP;
2745 reason = TASK_SWITCH_GATE;
2747 reason = TASK_SWITCH_CALL;
2749 if (reason == TASK_SWITCH_GATE) {
2751 case SVM_EXITINTINFO_TYPE_NMI:
2752 svm->vcpu.arch.nmi_injected = false;
2754 case SVM_EXITINTINFO_TYPE_EXEPT:
2755 if (svm->vmcb->control.exit_info_2 &
2756 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2757 has_error_code = true;
2759 (u32)svm->vmcb->control.exit_info_2;
2761 kvm_clear_exception_queue(&svm->vcpu);
2763 case SVM_EXITINTINFO_TYPE_INTR:
2764 kvm_clear_interrupt_queue(&svm->vcpu);
2771 if (reason != TASK_SWITCH_GATE ||
2772 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2773 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2774 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2775 skip_emulated_instruction(&svm->vcpu);
2777 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2780 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2781 has_error_code, error_code) == EMULATE_FAIL) {
2782 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2783 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2784 svm->vcpu.run->internal.ndata = 0;
2790 static int cpuid_interception(struct vcpu_svm *svm)
2792 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2793 kvm_emulate_cpuid(&svm->vcpu);
2797 static int iret_interception(struct vcpu_svm *svm)
2799 ++svm->vcpu.stat.nmi_window_exits;
2800 clr_intercept(svm, INTERCEPT_IRET);
2801 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2802 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2803 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2807 static int invlpg_interception(struct vcpu_svm *svm)
2809 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2810 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2812 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2813 skip_emulated_instruction(&svm->vcpu);
2817 static int emulate_on_interception(struct vcpu_svm *svm)
2819 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2822 static int rdpmc_interception(struct vcpu_svm *svm)
2826 if (!static_cpu_has(X86_FEATURE_NRIPS))
2827 return emulate_on_interception(svm);
2829 err = kvm_rdpmc(&svm->vcpu);
2830 kvm_complete_insn_gp(&svm->vcpu, err);
2835 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2838 unsigned long cr0 = svm->vcpu.arch.cr0;
2842 intercept = svm->nested.intercept;
2844 if (!is_guest_mode(&svm->vcpu) ||
2845 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2848 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2849 val &= ~SVM_CR0_SELECTIVE_MASK;
2852 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2853 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2859 #define CR_VALID (1ULL << 63)
2861 static int cr_interception(struct vcpu_svm *svm)
2867 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2868 return emulate_on_interception(svm);
2870 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2871 return emulate_on_interception(svm);
2873 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2874 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2875 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2877 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2880 if (cr >= 16) { /* mov to cr */
2882 val = kvm_register_read(&svm->vcpu, reg);
2885 if (!check_selective_cr0_intercepted(svm, val))
2886 err = kvm_set_cr0(&svm->vcpu, val);
2892 err = kvm_set_cr3(&svm->vcpu, val);
2895 err = kvm_set_cr4(&svm->vcpu, val);
2898 err = kvm_set_cr8(&svm->vcpu, val);
2901 WARN(1, "unhandled write to CR%d", cr);
2902 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2905 } else { /* mov from cr */
2908 val = kvm_read_cr0(&svm->vcpu);
2911 val = svm->vcpu.arch.cr2;
2914 val = kvm_read_cr3(&svm->vcpu);
2917 val = kvm_read_cr4(&svm->vcpu);
2920 val = kvm_get_cr8(&svm->vcpu);
2923 WARN(1, "unhandled read from CR%d", cr);
2924 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2927 kvm_register_write(&svm->vcpu, reg, val);
2929 kvm_complete_insn_gp(&svm->vcpu, err);
2934 static int dr_interception(struct vcpu_svm *svm)
2939 if (svm->vcpu.guest_debug == 0) {
2941 * No more DR vmexits; force a reload of the debug registers
2942 * and reenter on this instruction. The next vmexit will
2943 * retrieve the full state of the debug registers.
2945 clr_dr_intercepts(svm);
2946 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2950 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2951 return emulate_on_interception(svm);
2953 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2954 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2956 if (dr >= 16) { /* mov to DRn */
2957 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2959 val = kvm_register_read(&svm->vcpu, reg);
2960 kvm_set_dr(&svm->vcpu, dr - 16, val);
2962 if (!kvm_require_dr(&svm->vcpu, dr))
2964 kvm_get_dr(&svm->vcpu, dr, &val);
2965 kvm_register_write(&svm->vcpu, reg, val);
2968 skip_emulated_instruction(&svm->vcpu);
2973 static int cr8_write_interception(struct vcpu_svm *svm)
2975 struct kvm_run *kvm_run = svm->vcpu.run;
2978 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2979 /* instruction emulation calls kvm_set_cr8() */
2980 r = cr_interception(svm);
2981 if (lapic_in_kernel(&svm->vcpu))
2983 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2985 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2989 static u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2991 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
2992 return vmcb->control.tsc_offset + host_tsc;
2995 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2997 struct vcpu_svm *svm = to_svm(vcpu);
2999 switch (msr_info->index) {
3000 case MSR_IA32_TSC: {
3001 msr_info->data = svm->vmcb->control.tsc_offset +
3002 kvm_scale_tsc(vcpu, rdtsc());
3007 msr_info->data = svm->vmcb->save.star;
3009 #ifdef CONFIG_X86_64
3011 msr_info->data = svm->vmcb->save.lstar;
3014 msr_info->data = svm->vmcb->save.cstar;
3016 case MSR_KERNEL_GS_BASE:
3017 msr_info->data = svm->vmcb->save.kernel_gs_base;
3019 case MSR_SYSCALL_MASK:
3020 msr_info->data = svm->vmcb->save.sfmask;
3023 case MSR_IA32_SYSENTER_CS:
3024 msr_info->data = svm->vmcb->save.sysenter_cs;
3026 case MSR_IA32_SYSENTER_EIP:
3027 msr_info->data = svm->sysenter_eip;
3029 case MSR_IA32_SYSENTER_ESP:
3030 msr_info->data = svm->sysenter_esp;
3033 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3035 msr_info->data = svm->tsc_aux;
3038 * Nobody will change the following 5 values in the VMCB so we can
3039 * safely return them on rdmsr. They will always be 0 until LBRV is
3042 case MSR_IA32_DEBUGCTLMSR:
3043 msr_info->data = svm->vmcb->save.dbgctl;
3045 case MSR_IA32_LASTBRANCHFROMIP:
3046 msr_info->data = svm->vmcb->save.br_from;
3048 case MSR_IA32_LASTBRANCHTOIP:
3049 msr_info->data = svm->vmcb->save.br_to;
3051 case MSR_IA32_LASTINTFROMIP:
3052 msr_info->data = svm->vmcb->save.last_excp_from;
3054 case MSR_IA32_LASTINTTOIP:
3055 msr_info->data = svm->vmcb->save.last_excp_to;
3057 case MSR_VM_HSAVE_PA:
3058 msr_info->data = svm->nested.hsave_msr;
3061 msr_info->data = svm->nested.vm_cr_msr;
3063 case MSR_IA32_UCODE_REV:
3064 msr_info->data = 0x01000065;
3066 case MSR_F15H_IC_CFG: {
3070 family = guest_cpuid_family(vcpu);
3071 model = guest_cpuid_model(vcpu);
3073 if (family < 0 || model < 0)
3074 return kvm_get_msr_common(vcpu, msr_info);
3078 if (family == 0x15 &&
3079 (model >= 0x2 && model < 0x20))
3080 msr_info->data = 0x1E;
3084 return kvm_get_msr_common(vcpu, msr_info);
3089 static int rdmsr_interception(struct vcpu_svm *svm)
3091 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3092 struct msr_data msr_info;
3094 msr_info.index = ecx;
3095 msr_info.host_initiated = false;
3096 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3097 trace_kvm_msr_read_ex(ecx);
3098 kvm_inject_gp(&svm->vcpu, 0);
3100 trace_kvm_msr_read(ecx, msr_info.data);
3102 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3103 msr_info.data & 0xffffffff);
3104 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3105 msr_info.data >> 32);
3106 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3107 skip_emulated_instruction(&svm->vcpu);
3112 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3114 struct vcpu_svm *svm = to_svm(vcpu);
3115 int svm_dis, chg_mask;
3117 if (data & ~SVM_VM_CR_VALID_MASK)
3120 chg_mask = SVM_VM_CR_VALID_MASK;
3122 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3123 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3125 svm->nested.vm_cr_msr &= ~chg_mask;
3126 svm->nested.vm_cr_msr |= (data & chg_mask);
3128 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3130 /* check for svm_disable while efer.svme is set */
3131 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3137 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3139 struct vcpu_svm *svm = to_svm(vcpu);
3141 u32 ecx = msr->index;
3142 u64 data = msr->data;
3145 kvm_write_tsc(vcpu, msr);
3148 svm->vmcb->save.star = data;
3150 #ifdef CONFIG_X86_64
3152 svm->vmcb->save.lstar = data;
3155 svm->vmcb->save.cstar = data;
3157 case MSR_KERNEL_GS_BASE:
3158 svm->vmcb->save.kernel_gs_base = data;
3160 case MSR_SYSCALL_MASK:
3161 svm->vmcb->save.sfmask = data;
3164 case MSR_IA32_SYSENTER_CS:
3165 svm->vmcb->save.sysenter_cs = data;
3167 case MSR_IA32_SYSENTER_EIP:
3168 svm->sysenter_eip = data;
3169 svm->vmcb->save.sysenter_eip = data;
3171 case MSR_IA32_SYSENTER_ESP:
3172 svm->sysenter_esp = data;
3173 svm->vmcb->save.sysenter_esp = data;
3176 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3180 * This is rare, so we update the MSR here instead of using
3181 * direct_access_msrs. Doing that would require a rdmsr in
3184 svm->tsc_aux = data;
3185 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3187 case MSR_IA32_DEBUGCTLMSR:
3188 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3189 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3193 if (data & DEBUGCTL_RESERVED_BITS)
3196 svm->vmcb->save.dbgctl = data;
3197 mark_dirty(svm->vmcb, VMCB_LBR);
3198 if (data & (1ULL<<0))
3199 svm_enable_lbrv(svm);
3201 svm_disable_lbrv(svm);
3203 case MSR_VM_HSAVE_PA:
3204 svm->nested.hsave_msr = data;
3207 return svm_set_vm_cr(vcpu, data);
3209 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3212 return kvm_set_msr_common(vcpu, msr);
3217 static int wrmsr_interception(struct vcpu_svm *svm)
3219 struct msr_data msr;
3220 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3221 u64 data = kvm_read_edx_eax(&svm->vcpu);
3225 msr.host_initiated = false;
3227 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3228 if (kvm_set_msr(&svm->vcpu, &msr)) {
3229 trace_kvm_msr_write_ex(ecx, data);
3230 kvm_inject_gp(&svm->vcpu, 0);
3232 trace_kvm_msr_write(ecx, data);
3233 skip_emulated_instruction(&svm->vcpu);
3238 static int msr_interception(struct vcpu_svm *svm)
3240 if (svm->vmcb->control.exit_info_1)
3241 return wrmsr_interception(svm);
3243 return rdmsr_interception(svm);
3246 static int interrupt_window_interception(struct vcpu_svm *svm)
3248 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3249 svm_clear_vintr(svm);
3250 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3251 mark_dirty(svm->vmcb, VMCB_INTR);
3252 ++svm->vcpu.stat.irq_window_exits;
3256 static int pause_interception(struct vcpu_svm *svm)
3258 kvm_vcpu_on_spin(&(svm->vcpu));
3262 static int nop_interception(struct vcpu_svm *svm)
3264 skip_emulated_instruction(&(svm->vcpu));
3268 static int monitor_interception(struct vcpu_svm *svm)
3270 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3271 return nop_interception(svm);
3274 static int mwait_interception(struct vcpu_svm *svm)
3276 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3277 return nop_interception(svm);
3280 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3281 [SVM_EXIT_READ_CR0] = cr_interception,
3282 [SVM_EXIT_READ_CR3] = cr_interception,
3283 [SVM_EXIT_READ_CR4] = cr_interception,
3284 [SVM_EXIT_READ_CR8] = cr_interception,
3285 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3286 [SVM_EXIT_WRITE_CR0] = cr_interception,
3287 [SVM_EXIT_WRITE_CR3] = cr_interception,
3288 [SVM_EXIT_WRITE_CR4] = cr_interception,
3289 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3290 [SVM_EXIT_READ_DR0] = dr_interception,
3291 [SVM_EXIT_READ_DR1] = dr_interception,
3292 [SVM_EXIT_READ_DR2] = dr_interception,
3293 [SVM_EXIT_READ_DR3] = dr_interception,
3294 [SVM_EXIT_READ_DR4] = dr_interception,
3295 [SVM_EXIT_READ_DR5] = dr_interception,
3296 [SVM_EXIT_READ_DR6] = dr_interception,
3297 [SVM_EXIT_READ_DR7] = dr_interception,
3298 [SVM_EXIT_WRITE_DR0] = dr_interception,
3299 [SVM_EXIT_WRITE_DR1] = dr_interception,
3300 [SVM_EXIT_WRITE_DR2] = dr_interception,
3301 [SVM_EXIT_WRITE_DR3] = dr_interception,
3302 [SVM_EXIT_WRITE_DR4] = dr_interception,
3303 [SVM_EXIT_WRITE_DR5] = dr_interception,
3304 [SVM_EXIT_WRITE_DR6] = dr_interception,
3305 [SVM_EXIT_WRITE_DR7] = dr_interception,
3306 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3307 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3308 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3309 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3310 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3311 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3312 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3313 [SVM_EXIT_INTR] = intr_interception,
3314 [SVM_EXIT_NMI] = nmi_interception,
3315 [SVM_EXIT_SMI] = nop_on_interception,
3316 [SVM_EXIT_INIT] = nop_on_interception,
3317 [SVM_EXIT_VINTR] = interrupt_window_interception,
3318 [SVM_EXIT_RDPMC] = rdpmc_interception,
3319 [SVM_EXIT_CPUID] = cpuid_interception,
3320 [SVM_EXIT_IRET] = iret_interception,
3321 [SVM_EXIT_INVD] = emulate_on_interception,
3322 [SVM_EXIT_PAUSE] = pause_interception,
3323 [SVM_EXIT_HLT] = halt_interception,
3324 [SVM_EXIT_INVLPG] = invlpg_interception,
3325 [SVM_EXIT_INVLPGA] = invlpga_interception,
3326 [SVM_EXIT_IOIO] = io_interception,
3327 [SVM_EXIT_MSR] = msr_interception,
3328 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3329 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3330 [SVM_EXIT_VMRUN] = vmrun_interception,
3331 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3332 [SVM_EXIT_VMLOAD] = vmload_interception,
3333 [SVM_EXIT_VMSAVE] = vmsave_interception,
3334 [SVM_EXIT_STGI] = stgi_interception,
3335 [SVM_EXIT_CLGI] = clgi_interception,
3336 [SVM_EXIT_SKINIT] = skinit_interception,
3337 [SVM_EXIT_WBINVD] = wbinvd_interception,
3338 [SVM_EXIT_MONITOR] = monitor_interception,
3339 [SVM_EXIT_MWAIT] = mwait_interception,
3340 [SVM_EXIT_XSETBV] = xsetbv_interception,
3341 [SVM_EXIT_NPF] = pf_interception,
3342 [SVM_EXIT_RSM] = emulate_on_interception,
3345 static void dump_vmcb(struct kvm_vcpu *vcpu)
3347 struct vcpu_svm *svm = to_svm(vcpu);
3348 struct vmcb_control_area *control = &svm->vmcb->control;
3349 struct vmcb_save_area *save = &svm->vmcb->save;
3351 pr_err("VMCB Control Area:\n");
3352 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3353 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3354 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3355 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3356 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3357 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3358 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3359 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3360 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3361 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3362 pr_err("%-20s%d\n", "asid:", control->asid);
3363 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3364 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3365 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3366 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3367 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3368 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3369 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3370 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3371 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3372 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3373 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3374 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3375 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3376 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3377 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3378 pr_err("VMCB State Save Area:\n");
3379 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3381 save->es.selector, save->es.attrib,
3382 save->es.limit, save->es.base);
3383 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3385 save->cs.selector, save->cs.attrib,
3386 save->cs.limit, save->cs.base);
3387 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3389 save->ss.selector, save->ss.attrib,
3390 save->ss.limit, save->ss.base);
3391 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3393 save->ds.selector, save->ds.attrib,
3394 save->ds.limit, save->ds.base);
3395 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3397 save->fs.selector, save->fs.attrib,
3398 save->fs.limit, save->fs.base);
3399 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3401 save->gs.selector, save->gs.attrib,
3402 save->gs.limit, save->gs.base);
3403 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3405 save->gdtr.selector, save->gdtr.attrib,
3406 save->gdtr.limit, save->gdtr.base);
3407 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3409 save->ldtr.selector, save->ldtr.attrib,
3410 save->ldtr.limit, save->ldtr.base);
3411 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3413 save->idtr.selector, save->idtr.attrib,
3414 save->idtr.limit, save->idtr.base);
3415 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3417 save->tr.selector, save->tr.attrib,
3418 save->tr.limit, save->tr.base);
3419 pr_err("cpl: %d efer: %016llx\n",
3420 save->cpl, save->efer);
3421 pr_err("%-15s %016llx %-13s %016llx\n",
3422 "cr0:", save->cr0, "cr2:", save->cr2);
3423 pr_err("%-15s %016llx %-13s %016llx\n",
3424 "cr3:", save->cr3, "cr4:", save->cr4);
3425 pr_err("%-15s %016llx %-13s %016llx\n",
3426 "dr6:", save->dr6, "dr7:", save->dr7);
3427 pr_err("%-15s %016llx %-13s %016llx\n",
3428 "rip:", save->rip, "rflags:", save->rflags);
3429 pr_err("%-15s %016llx %-13s %016llx\n",
3430 "rsp:", save->rsp, "rax:", save->rax);
3431 pr_err("%-15s %016llx %-13s %016llx\n",
3432 "star:", save->star, "lstar:", save->lstar);
3433 pr_err("%-15s %016llx %-13s %016llx\n",
3434 "cstar:", save->cstar, "sfmask:", save->sfmask);
3435 pr_err("%-15s %016llx %-13s %016llx\n",
3436 "kernel_gs_base:", save->kernel_gs_base,
3437 "sysenter_cs:", save->sysenter_cs);
3438 pr_err("%-15s %016llx %-13s %016llx\n",
3439 "sysenter_esp:", save->sysenter_esp,
3440 "sysenter_eip:", save->sysenter_eip);
3441 pr_err("%-15s %016llx %-13s %016llx\n",
3442 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3443 pr_err("%-15s %016llx %-13s %016llx\n",
3444 "br_from:", save->br_from, "br_to:", save->br_to);
3445 pr_err("%-15s %016llx %-13s %016llx\n",
3446 "excp_from:", save->last_excp_from,
3447 "excp_to:", save->last_excp_to);
3450 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3452 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3454 *info1 = control->exit_info_1;
3455 *info2 = control->exit_info_2;
3458 static int handle_exit(struct kvm_vcpu *vcpu)
3460 struct vcpu_svm *svm = to_svm(vcpu);
3461 struct kvm_run *kvm_run = vcpu->run;
3462 u32 exit_code = svm->vmcb->control.exit_code;
3464 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3466 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3467 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3469 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3471 if (unlikely(svm->nested.exit_required)) {
3472 nested_svm_vmexit(svm);
3473 svm->nested.exit_required = false;
3478 if (is_guest_mode(vcpu)) {
3481 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3482 svm->vmcb->control.exit_info_1,
3483 svm->vmcb->control.exit_info_2,
3484 svm->vmcb->control.exit_int_info,
3485 svm->vmcb->control.exit_int_info_err,
3488 vmexit = nested_svm_exit_special(svm);
3490 if (vmexit == NESTED_EXIT_CONTINUE)
3491 vmexit = nested_svm_exit_handled(svm);
3493 if (vmexit == NESTED_EXIT_DONE)
3497 svm_complete_interrupts(svm);
3499 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3500 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3501 kvm_run->fail_entry.hardware_entry_failure_reason
3502 = svm->vmcb->control.exit_code;
3503 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3508 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3509 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3510 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3511 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3512 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3514 __func__, svm->vmcb->control.exit_int_info,
3517 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3518 || !svm_exit_handlers[exit_code]) {
3519 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
3520 kvm_queue_exception(vcpu, UD_VECTOR);
3524 return svm_exit_handlers[exit_code](svm);
3527 static void reload_tss(struct kvm_vcpu *vcpu)
3529 int cpu = raw_smp_processor_id();
3531 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3532 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3536 static void pre_svm_run(struct vcpu_svm *svm)
3538 int cpu = raw_smp_processor_id();
3540 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3542 /* FIXME: handle wraparound of asid_generation */
3543 if (svm->asid_generation != sd->asid_generation)
3547 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3549 struct vcpu_svm *svm = to_svm(vcpu);
3551 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3552 vcpu->arch.hflags |= HF_NMI_MASK;
3553 set_intercept(svm, INTERCEPT_IRET);
3554 ++vcpu->stat.nmi_injections;
3557 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3559 struct vmcb_control_area *control;
3561 control = &svm->vmcb->control;
3562 control->int_vector = irq;
3563 control->int_ctl &= ~V_INTR_PRIO_MASK;
3564 control->int_ctl |= V_IRQ_MASK |
3565 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3566 mark_dirty(svm->vmcb, VMCB_INTR);
3569 static void svm_set_irq(struct kvm_vcpu *vcpu)
3571 struct vcpu_svm *svm = to_svm(vcpu);
3573 BUG_ON(!(gif_set(svm)));
3575 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3576 ++vcpu->stat.irq_injections;
3578 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3579 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3582 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3584 struct vcpu_svm *svm = to_svm(vcpu);
3586 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3589 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3595 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3598 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3603 static bool svm_get_enable_apicv(void)
3608 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3612 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3617 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3622 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3624 struct vcpu_svm *svm = to_svm(vcpu);
3625 struct vmcb *vmcb = svm->vmcb;
3627 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3628 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3629 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3634 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3636 struct vcpu_svm *svm = to_svm(vcpu);
3638 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3641 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3643 struct vcpu_svm *svm = to_svm(vcpu);
3646 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3647 set_intercept(svm, INTERCEPT_IRET);
3649 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3650 clr_intercept(svm, INTERCEPT_IRET);
3654 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3656 struct vcpu_svm *svm = to_svm(vcpu);
3657 struct vmcb *vmcb = svm->vmcb;
3660 if (!gif_set(svm) ||
3661 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3664 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3666 if (is_guest_mode(vcpu))
3667 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3672 static void enable_irq_window(struct kvm_vcpu *vcpu)
3674 struct vcpu_svm *svm = to_svm(vcpu);
3677 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3678 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3679 * get that intercept, this function will be called again though and
3680 * we'll get the vintr intercept.
3682 if (gif_set(svm) && nested_svm_intr(svm)) {
3684 svm_inject_irq(svm, 0x0);
3688 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3690 struct vcpu_svm *svm = to_svm(vcpu);
3692 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3694 return; /* IRET will cause a vm exit */
3697 * Something prevents NMI from been injected. Single step over possible
3698 * problem (IRET or exception injection or interrupt shadow)
3700 svm->nmi_singlestep = true;
3701 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3704 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3709 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3711 struct vcpu_svm *svm = to_svm(vcpu);
3713 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3714 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3716 svm->asid_generation--;
3719 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3723 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3725 struct vcpu_svm *svm = to_svm(vcpu);
3727 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3730 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3731 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3732 kvm_set_cr8(vcpu, cr8);
3736 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3738 struct vcpu_svm *svm = to_svm(vcpu);
3741 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3744 cr8 = kvm_get_cr8(vcpu);
3745 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3746 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3749 static void svm_complete_interrupts(struct vcpu_svm *svm)
3753 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3754 unsigned int3_injected = svm->int3_injected;
3756 svm->int3_injected = 0;
3759 * If we've made progress since setting HF_IRET_MASK, we've
3760 * executed an IRET and can allow NMI injection.
3762 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3763 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3764 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3765 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3768 svm->vcpu.arch.nmi_injected = false;
3769 kvm_clear_exception_queue(&svm->vcpu);
3770 kvm_clear_interrupt_queue(&svm->vcpu);
3772 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3775 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3777 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3778 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3781 case SVM_EXITINTINFO_TYPE_NMI:
3782 svm->vcpu.arch.nmi_injected = true;
3784 case SVM_EXITINTINFO_TYPE_EXEPT:
3786 * In case of software exceptions, do not reinject the vector,
3787 * but re-execute the instruction instead. Rewind RIP first
3788 * if we emulated INT3 before.
3790 if (kvm_exception_is_soft(vector)) {
3791 if (vector == BP_VECTOR && int3_injected &&
3792 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3793 kvm_rip_write(&svm->vcpu,
3794 kvm_rip_read(&svm->vcpu) -
3798 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3799 u32 err = svm->vmcb->control.exit_int_info_err;
3800 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3803 kvm_requeue_exception(&svm->vcpu, vector);
3805 case SVM_EXITINTINFO_TYPE_INTR:
3806 kvm_queue_interrupt(&svm->vcpu, vector, false);
3813 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3815 struct vcpu_svm *svm = to_svm(vcpu);
3816 struct vmcb_control_area *control = &svm->vmcb->control;
3818 control->exit_int_info = control->event_inj;
3819 control->exit_int_info_err = control->event_inj_err;
3820 control->event_inj = 0;
3821 svm_complete_interrupts(svm);
3824 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3826 struct vcpu_svm *svm = to_svm(vcpu);
3828 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3829 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3830 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3833 * A vmexit emulation is required before the vcpu can be executed
3836 if (unlikely(svm->nested.exit_required))
3841 sync_lapic_to_cr8(vcpu);
3843 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3850 "push %%" _ASM_BP "; \n\t"
3851 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3852 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3853 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3854 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3855 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3856 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3857 #ifdef CONFIG_X86_64
3858 "mov %c[r8](%[svm]), %%r8 \n\t"
3859 "mov %c[r9](%[svm]), %%r9 \n\t"
3860 "mov %c[r10](%[svm]), %%r10 \n\t"
3861 "mov %c[r11](%[svm]), %%r11 \n\t"
3862 "mov %c[r12](%[svm]), %%r12 \n\t"
3863 "mov %c[r13](%[svm]), %%r13 \n\t"
3864 "mov %c[r14](%[svm]), %%r14 \n\t"
3865 "mov %c[r15](%[svm]), %%r15 \n\t"
3868 /* Enter guest mode */
3869 "push %%" _ASM_AX " \n\t"
3870 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3871 __ex(SVM_VMLOAD) "\n\t"
3872 __ex(SVM_VMRUN) "\n\t"
3873 __ex(SVM_VMSAVE) "\n\t"
3874 "pop %%" _ASM_AX " \n\t"
3876 /* Save guest registers, load host registers */
3877 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3878 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3879 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3880 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3881 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3882 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3883 #ifdef CONFIG_X86_64
3884 "mov %%r8, %c[r8](%[svm]) \n\t"
3885 "mov %%r9, %c[r9](%[svm]) \n\t"
3886 "mov %%r10, %c[r10](%[svm]) \n\t"
3887 "mov %%r11, %c[r11](%[svm]) \n\t"
3888 "mov %%r12, %c[r12](%[svm]) \n\t"
3889 "mov %%r13, %c[r13](%[svm]) \n\t"
3890 "mov %%r14, %c[r14](%[svm]) \n\t"
3891 "mov %%r15, %c[r15](%[svm]) \n\t"
3896 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3897 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3898 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3899 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3900 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3901 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3902 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3903 #ifdef CONFIG_X86_64
3904 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3905 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3906 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3907 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3908 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3909 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3910 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3911 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3914 #ifdef CONFIG_X86_64
3915 , "rbx", "rcx", "rdx", "rsi", "rdi"
3916 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3918 , "ebx", "ecx", "edx", "esi", "edi"
3922 #ifdef CONFIG_X86_64
3923 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3925 loadsegment(fs, svm->host.fs);
3926 #ifndef CONFIG_X86_32_LAZY_GS
3927 loadsegment(gs, svm->host.gs);
3933 local_irq_disable();
3935 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3936 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3937 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3938 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3940 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3941 kvm_before_handle_nmi(&svm->vcpu);
3945 /* Any pending NMI will happen here */
3947 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3948 kvm_after_handle_nmi(&svm->vcpu);
3950 sync_cr8_to_lapic(vcpu);
3954 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3956 /* if exit due to PF check for async PF */
3957 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3958 svm->apf_reason = kvm_read_and_reset_pf_reason();
3961 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3962 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3966 * We need to handle MC intercepts here before the vcpu has a chance to
3967 * change the physical cpu
3969 if (unlikely(svm->vmcb->control.exit_code ==
3970 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3971 svm_handle_mce(svm);
3973 mark_all_clean(svm->vmcb);
3976 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3978 struct vcpu_svm *svm = to_svm(vcpu);
3980 svm->vmcb->save.cr3 = root;
3981 mark_dirty(svm->vmcb, VMCB_CR);
3982 svm_flush_tlb(vcpu);
3985 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3987 struct vcpu_svm *svm = to_svm(vcpu);
3989 svm->vmcb->control.nested_cr3 = root;
3990 mark_dirty(svm->vmcb, VMCB_NPT);
3992 /* Also sync guest cr3 here in case we live migrate */
3993 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3994 mark_dirty(svm->vmcb, VMCB_CR);
3996 svm_flush_tlb(vcpu);
3999 static int is_disabled(void)
4003 rdmsrl(MSR_VM_CR, vm_cr);
4004 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4011 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4014 * Patch in the VMMCALL instruction:
4016 hypercall[0] = 0x0f;
4017 hypercall[1] = 0x01;
4018 hypercall[2] = 0xd9;
4021 static void svm_check_processor_compat(void *rtn)
4026 static bool svm_cpu_has_accelerated_tpr(void)
4031 static bool svm_has_high_real_mode_segbase(void)
4036 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4041 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4043 struct vcpu_svm *svm = to_svm(vcpu);
4045 /* Update nrips enabled cache */
4046 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
4049 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4054 entry->ecx |= (1 << 2); /* Set SVM bit */
4057 entry->eax = 1; /* SVM revision 1 */
4058 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4059 ASID emulation to nested SVM */
4060 entry->ecx = 0; /* Reserved */
4061 entry->edx = 0; /* Per default do not support any
4062 additional features */
4064 /* Support next_rip if host supports it */
4065 if (boot_cpu_has(X86_FEATURE_NRIPS))
4066 entry->edx |= SVM_FEATURE_NRIP;
4068 /* Support NPT for the guest if enabled */
4070 entry->edx |= SVM_FEATURE_NPT;
4076 static int svm_get_lpage_level(void)
4078 return PT_PDPE_LEVEL;
4081 static bool svm_rdtscp_supported(void)
4083 return boot_cpu_has(X86_FEATURE_RDTSCP);
4086 static bool svm_invpcid_supported(void)
4091 static bool svm_mpx_supported(void)
4096 static bool svm_xsaves_supported(void)
4101 static bool svm_has_wbinvd_exit(void)
4106 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4108 struct vcpu_svm *svm = to_svm(vcpu);
4110 set_exception_intercept(svm, NM_VECTOR);
4111 update_cr0_intercept(svm);
4114 #define PRE_EX(exit) { .exit_code = (exit), \
4115 .stage = X86_ICPT_PRE_EXCEPT, }
4116 #define POST_EX(exit) { .exit_code = (exit), \
4117 .stage = X86_ICPT_POST_EXCEPT, }
4118 #define POST_MEM(exit) { .exit_code = (exit), \
4119 .stage = X86_ICPT_POST_MEMACCESS, }
4121 static const struct __x86_intercept {
4123 enum x86_intercept_stage stage;
4124 } x86_intercept_map[] = {
4125 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4126 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4127 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4128 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4129 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4130 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4131 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4132 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4133 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4134 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4135 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4136 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4137 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4138 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4139 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4140 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4141 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4142 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4143 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4144 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4145 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4146 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4147 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4148 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4149 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4150 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4151 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4152 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4153 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4154 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4155 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4156 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4157 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4158 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4159 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4160 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4161 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4162 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4163 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4164 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4165 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4166 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4167 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4168 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4169 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4170 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4177 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4178 struct x86_instruction_info *info,
4179 enum x86_intercept_stage stage)
4181 struct vcpu_svm *svm = to_svm(vcpu);
4182 int vmexit, ret = X86EMUL_CONTINUE;
4183 struct __x86_intercept icpt_info;
4184 struct vmcb *vmcb = svm->vmcb;
4186 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4189 icpt_info = x86_intercept_map[info->intercept];
4191 if (stage != icpt_info.stage)
4194 switch (icpt_info.exit_code) {
4195 case SVM_EXIT_READ_CR0:
4196 if (info->intercept == x86_intercept_cr_read)
4197 icpt_info.exit_code += info->modrm_reg;
4199 case SVM_EXIT_WRITE_CR0: {
4200 unsigned long cr0, val;
4203 if (info->intercept == x86_intercept_cr_write)
4204 icpt_info.exit_code += info->modrm_reg;
4206 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4207 info->intercept == x86_intercept_clts)
4210 intercept = svm->nested.intercept;
4212 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4215 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4216 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4218 if (info->intercept == x86_intercept_lmsw) {
4221 /* lmsw can't clear PE - catch this here */
4222 if (cr0 & X86_CR0_PE)
4227 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4231 case SVM_EXIT_READ_DR0:
4232 case SVM_EXIT_WRITE_DR0:
4233 icpt_info.exit_code += info->modrm_reg;
4236 if (info->intercept == x86_intercept_wrmsr)
4237 vmcb->control.exit_info_1 = 1;
4239 vmcb->control.exit_info_1 = 0;
4241 case SVM_EXIT_PAUSE:
4243 * We get this for NOP only, but pause
4244 * is rep not, check this here
4246 if (info->rep_prefix != REPE_PREFIX)
4248 case SVM_EXIT_IOIO: {
4252 if (info->intercept == x86_intercept_in ||
4253 info->intercept == x86_intercept_ins) {
4254 exit_info = ((info->src_val & 0xffff) << 16) |
4256 bytes = info->dst_bytes;
4258 exit_info = (info->dst_val & 0xffff) << 16;
4259 bytes = info->src_bytes;
4262 if (info->intercept == x86_intercept_outs ||
4263 info->intercept == x86_intercept_ins)
4264 exit_info |= SVM_IOIO_STR_MASK;
4266 if (info->rep_prefix)
4267 exit_info |= SVM_IOIO_REP_MASK;
4269 bytes = min(bytes, 4u);
4271 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4273 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4275 vmcb->control.exit_info_1 = exit_info;
4276 vmcb->control.exit_info_2 = info->next_rip;
4284 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4285 if (static_cpu_has(X86_FEATURE_NRIPS))
4286 vmcb->control.next_rip = info->next_rip;
4287 vmcb->control.exit_code = icpt_info.exit_code;
4288 vmexit = nested_svm_exit_handled(svm);
4290 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4297 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4302 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4306 static struct kvm_x86_ops svm_x86_ops = {
4307 .cpu_has_kvm_support = has_svm,
4308 .disabled_by_bios = is_disabled,
4309 .hardware_setup = svm_hardware_setup,
4310 .hardware_unsetup = svm_hardware_unsetup,
4311 .check_processor_compatibility = svm_check_processor_compat,
4312 .hardware_enable = svm_hardware_enable,
4313 .hardware_disable = svm_hardware_disable,
4314 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4315 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
4317 .vcpu_create = svm_create_vcpu,
4318 .vcpu_free = svm_free_vcpu,
4319 .vcpu_reset = svm_vcpu_reset,
4321 .prepare_guest_switch = svm_prepare_guest_switch,
4322 .vcpu_load = svm_vcpu_load,
4323 .vcpu_put = svm_vcpu_put,
4325 .update_bp_intercept = update_bp_intercept,
4326 .get_msr = svm_get_msr,
4327 .set_msr = svm_set_msr,
4328 .get_segment_base = svm_get_segment_base,
4329 .get_segment = svm_get_segment,
4330 .set_segment = svm_set_segment,
4331 .get_cpl = svm_get_cpl,
4332 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4333 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4334 .decache_cr3 = svm_decache_cr3,
4335 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4336 .set_cr0 = svm_set_cr0,
4337 .set_cr3 = svm_set_cr3,
4338 .set_cr4 = svm_set_cr4,
4339 .set_efer = svm_set_efer,
4340 .get_idt = svm_get_idt,
4341 .set_idt = svm_set_idt,
4342 .get_gdt = svm_get_gdt,
4343 .set_gdt = svm_set_gdt,
4344 .get_dr6 = svm_get_dr6,
4345 .set_dr6 = svm_set_dr6,
4346 .set_dr7 = svm_set_dr7,
4347 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4348 .cache_reg = svm_cache_reg,
4349 .get_rflags = svm_get_rflags,
4350 .set_rflags = svm_set_rflags,
4351 .fpu_activate = svm_fpu_activate,
4352 .fpu_deactivate = svm_fpu_deactivate,
4354 .tlb_flush = svm_flush_tlb,
4356 .run = svm_vcpu_run,
4357 .handle_exit = handle_exit,
4358 .skip_emulated_instruction = skip_emulated_instruction,
4359 .set_interrupt_shadow = svm_set_interrupt_shadow,
4360 .get_interrupt_shadow = svm_get_interrupt_shadow,
4361 .patch_hypercall = svm_patch_hypercall,
4362 .set_irq = svm_set_irq,
4363 .set_nmi = svm_inject_nmi,
4364 .queue_exception = svm_queue_exception,
4365 .cancel_injection = svm_cancel_injection,
4366 .interrupt_allowed = svm_interrupt_allowed,
4367 .nmi_allowed = svm_nmi_allowed,
4368 .get_nmi_mask = svm_get_nmi_mask,
4369 .set_nmi_mask = svm_set_nmi_mask,
4370 .enable_nmi_window = enable_nmi_window,
4371 .enable_irq_window = enable_irq_window,
4372 .update_cr8_intercept = update_cr8_intercept,
4373 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4374 .get_enable_apicv = svm_get_enable_apicv,
4375 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4376 .load_eoi_exitmap = svm_load_eoi_exitmap,
4377 .sync_pir_to_irr = svm_sync_pir_to_irr,
4379 .set_tss_addr = svm_set_tss_addr,
4380 .get_tdp_level = get_npt_level,
4381 .get_mt_mask = svm_get_mt_mask,
4383 .get_exit_info = svm_get_exit_info,
4385 .get_lpage_level = svm_get_lpage_level,
4387 .cpuid_update = svm_cpuid_update,
4389 .rdtscp_supported = svm_rdtscp_supported,
4390 .invpcid_supported = svm_invpcid_supported,
4391 .mpx_supported = svm_mpx_supported,
4392 .xsaves_supported = svm_xsaves_supported,
4394 .set_supported_cpuid = svm_set_supported_cpuid,
4396 .has_wbinvd_exit = svm_has_wbinvd_exit,
4398 .read_tsc_offset = svm_read_tsc_offset,
4399 .write_tsc_offset = svm_write_tsc_offset,
4400 .adjust_tsc_offset_guest = svm_adjust_tsc_offset_guest,
4401 .read_l1_tsc = svm_read_l1_tsc,
4403 .set_tdp_cr3 = set_tdp_cr3,
4405 .check_intercept = svm_check_intercept,
4406 .handle_external_intr = svm_handle_external_intr,
4408 .sched_in = svm_sched_in,
4410 .pmu_ops = &amd_pmu_ops,
4413 static int __init svm_init(void)
4415 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4416 __alignof__(struct vcpu_svm), THIS_MODULE);
4419 static void __exit svm_exit(void)
4424 module_init(svm_init)
4425 module_exit(svm_exit)