2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/perf_event.h>
33 #include <asm/tlbflush.h>
35 #include <asm/kvm_para.h>
37 #include <asm/virtext.h>
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
45 #define IOPM_ALLOC_ORDER 2
46 #define MSRPM_ALLOC_ORDER 1
48 #define SEG_TYPE_LDT 2
49 #define SEG_TYPE_BUSY_TSS16 3
51 #define SVM_FEATURE_NPT (1 << 0)
52 #define SVM_FEATURE_LBRV (1 << 1)
53 #define SVM_FEATURE_SVML (1 << 2)
54 #define SVM_FEATURE_NRIP (1 << 3)
55 #define SVM_FEATURE_TSC_RATE (1 << 4)
56 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
57 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
58 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
59 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
61 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
62 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
63 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
65 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
67 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
68 #define TSC_RATIO_MIN 0x0000000000000001ULL
69 #define TSC_RATIO_MAX 0x000000ffffffffffULL
71 static bool erratum_383_found __read_mostly;
73 static const u32 host_save_user_msrs[] = {
75 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
78 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
81 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
91 /* These are the merged vectors */
94 /* gpa pointers to the real vectors */
98 /* A VMEXIT is required but not yet emulated */
101 /* cache for intercepts of the guest */
104 u32 intercept_exceptions;
107 /* Nested Paging related state */
111 #define MSRPM_OFFSETS 16
112 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
115 * Set osvw_len to higher value when updated Revision Guides
116 * are published and we know what the new status bits are
118 static uint64_t osvw_len = 4, osvw_status;
121 struct kvm_vcpu vcpu;
123 unsigned long vmcb_pa;
124 struct svm_cpu_data *svm_data;
125 uint64_t asid_generation;
126 uint64_t sysenter_esp;
127 uint64_t sysenter_eip;
131 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
143 struct nested_state nested;
147 unsigned int3_injected;
148 unsigned long int3_rip;
154 static DEFINE_PER_CPU(u64, current_tsc_ratio);
155 #define TSC_RATIO_DEFAULT 0x0100000000ULL
157 #define MSR_INVALID 0xffffffffU
159 static struct svm_direct_access_msrs {
160 u32 index; /* Index of the MSR */
161 bool always; /* True if intercept is always on */
162 } direct_access_msrs[] = {
163 { .index = MSR_STAR, .always = true },
164 { .index = MSR_IA32_SYSENTER_CS, .always = true },
166 { .index = MSR_GS_BASE, .always = true },
167 { .index = MSR_FS_BASE, .always = true },
168 { .index = MSR_KERNEL_GS_BASE, .always = true },
169 { .index = MSR_LSTAR, .always = true },
170 { .index = MSR_CSTAR, .always = true },
171 { .index = MSR_SYSCALL_MASK, .always = true },
173 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
174 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
175 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
176 { .index = MSR_IA32_LASTINTTOIP, .always = false },
177 { .index = MSR_INVALID, .always = false },
180 /* enable NPT for AMD64 and X86 with PAE */
181 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
182 static bool npt_enabled = true;
184 static bool npt_enabled;
187 /* allow nested paging (virtualized MMU) for all guests */
188 static int npt = true;
189 module_param(npt, int, S_IRUGO);
191 /* allow nested virtualization in KVM/SVM */
192 static int nested = true;
193 module_param(nested, int, S_IRUGO);
195 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
196 static void svm_complete_interrupts(struct vcpu_svm *svm);
198 static int nested_svm_exit_handled(struct vcpu_svm *svm);
199 static int nested_svm_intercept(struct vcpu_svm *svm);
200 static int nested_svm_vmexit(struct vcpu_svm *svm);
201 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
202 bool has_error_code, u32 error_code);
203 static u64 __scale_tsc(u64 ratio, u64 tsc);
206 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
207 pause filter count */
208 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
209 VMCB_ASID, /* ASID */
210 VMCB_INTR, /* int_ctl, int_vector */
211 VMCB_NPT, /* npt_en, nCR3, gPAT */
212 VMCB_CR, /* CR0, CR3, CR4, EFER */
213 VMCB_DR, /* DR6, DR7 */
214 VMCB_DT, /* GDT, IDT */
215 VMCB_SEG, /* CS, DS, SS, ES, CPL */
216 VMCB_CR2, /* CR2 only */
217 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
221 /* TPR and CR2 are always written before VMRUN */
222 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
224 static inline void mark_all_dirty(struct vmcb *vmcb)
226 vmcb->control.clean = 0;
229 static inline void mark_all_clean(struct vmcb *vmcb)
231 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
232 & ~VMCB_ALWAYS_DIRTY_MASK;
235 static inline void mark_dirty(struct vmcb *vmcb, int bit)
237 vmcb->control.clean &= ~(1 << bit);
240 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
242 return container_of(vcpu, struct vcpu_svm, vcpu);
245 static void recalc_intercepts(struct vcpu_svm *svm)
247 struct vmcb_control_area *c, *h;
248 struct nested_state *g;
250 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
252 if (!is_guest_mode(&svm->vcpu))
255 c = &svm->vmcb->control;
256 h = &svm->nested.hsave->control;
259 c->intercept_cr = h->intercept_cr | g->intercept_cr;
260 c->intercept_dr = h->intercept_dr | g->intercept_dr;
261 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
262 c->intercept = h->intercept | g->intercept;
265 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
267 if (is_guest_mode(&svm->vcpu))
268 return svm->nested.hsave;
273 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
275 struct vmcb *vmcb = get_host_vmcb(svm);
277 vmcb->control.intercept_cr |= (1U << bit);
279 recalc_intercepts(svm);
282 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
284 struct vmcb *vmcb = get_host_vmcb(svm);
286 vmcb->control.intercept_cr &= ~(1U << bit);
288 recalc_intercepts(svm);
291 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
293 struct vmcb *vmcb = get_host_vmcb(svm);
295 return vmcb->control.intercept_cr & (1U << bit);
298 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
300 struct vmcb *vmcb = get_host_vmcb(svm);
302 vmcb->control.intercept_dr |= (1U << bit);
304 recalc_intercepts(svm);
307 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
309 struct vmcb *vmcb = get_host_vmcb(svm);
311 vmcb->control.intercept_dr &= ~(1U << bit);
313 recalc_intercepts(svm);
316 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
318 struct vmcb *vmcb = get_host_vmcb(svm);
320 vmcb->control.intercept_exceptions |= (1U << bit);
322 recalc_intercepts(svm);
325 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
327 struct vmcb *vmcb = get_host_vmcb(svm);
329 vmcb->control.intercept_exceptions &= ~(1U << bit);
331 recalc_intercepts(svm);
334 static inline void set_intercept(struct vcpu_svm *svm, int bit)
336 struct vmcb *vmcb = get_host_vmcb(svm);
338 vmcb->control.intercept |= (1ULL << bit);
340 recalc_intercepts(svm);
343 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
345 struct vmcb *vmcb = get_host_vmcb(svm);
347 vmcb->control.intercept &= ~(1ULL << bit);
349 recalc_intercepts(svm);
352 static inline void enable_gif(struct vcpu_svm *svm)
354 svm->vcpu.arch.hflags |= HF_GIF_MASK;
357 static inline void disable_gif(struct vcpu_svm *svm)
359 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
362 static inline bool gif_set(struct vcpu_svm *svm)
364 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
367 static unsigned long iopm_base;
369 struct kvm_ldttss_desc {
372 unsigned base1:8, type:5, dpl:2, p:1;
373 unsigned limit1:4, zero0:3, g:1, base2:8;
376 } __attribute__((packed));
378 struct svm_cpu_data {
384 struct kvm_ldttss_desc *tss_desc;
386 struct page *save_area;
389 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
391 struct svm_init_data {
396 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
398 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
399 #define MSRS_RANGE_SIZE 2048
400 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
402 static u32 svm_msrpm_offset(u32 msr)
407 for (i = 0; i < NUM_MSR_MAPS; i++) {
408 if (msr < msrpm_ranges[i] ||
409 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
412 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
413 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
415 /* Now we have the u8 offset - but need the u32 offset */
419 /* MSR not in any range */
423 #define MAX_INST_SIZE 15
425 static inline void clgi(void)
427 asm volatile (__ex(SVM_CLGI));
430 static inline void stgi(void)
432 asm volatile (__ex(SVM_STGI));
435 static inline void invlpga(unsigned long addr, u32 asid)
437 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
440 static int get_npt_level(void)
443 return PT64_ROOT_LEVEL;
445 return PT32E_ROOT_LEVEL;
449 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
451 vcpu->arch.efer = efer;
452 if (!npt_enabled && !(efer & EFER_LMA))
455 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
456 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
459 static int is_external_interrupt(u32 info)
461 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
462 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
465 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
467 struct vcpu_svm *svm = to_svm(vcpu);
470 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
471 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
475 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
477 struct vcpu_svm *svm = to_svm(vcpu);
480 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
482 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
486 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
488 struct vcpu_svm *svm = to_svm(vcpu);
490 if (svm->vmcb->control.next_rip != 0)
491 svm->next_rip = svm->vmcb->control.next_rip;
493 if (!svm->next_rip) {
494 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
496 printk(KERN_DEBUG "%s: NOP\n", __func__);
499 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
500 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
501 __func__, kvm_rip_read(vcpu), svm->next_rip);
503 kvm_rip_write(vcpu, svm->next_rip);
504 svm_set_interrupt_shadow(vcpu, 0);
507 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
508 bool has_error_code, u32 error_code,
511 struct vcpu_svm *svm = to_svm(vcpu);
514 * If we are within a nested VM we'd better #VMEXIT and let the guest
515 * handle the exception
518 nested_svm_check_exception(svm, nr, has_error_code, error_code))
521 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
522 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
525 * For guest debugging where we have to reinject #BP if some
526 * INT3 is guest-owned:
527 * Emulate nRIP by moving RIP forward. Will fail if injection
528 * raises a fault that is not intercepted. Still better than
529 * failing in all cases.
531 skip_emulated_instruction(&svm->vcpu);
532 rip = kvm_rip_read(&svm->vcpu);
533 svm->int3_rip = rip + svm->vmcb->save.cs.base;
534 svm->int3_injected = rip - old_rip;
537 svm->vmcb->control.event_inj = nr
539 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
540 | SVM_EVTINJ_TYPE_EXEPT;
541 svm->vmcb->control.event_inj_err = error_code;
544 static void svm_init_erratum_383(void)
550 if (!cpu_has_amd_erratum(amd_erratum_383))
553 /* Use _safe variants to not break nested virtualization */
554 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
560 low = lower_32_bits(val);
561 high = upper_32_bits(val);
563 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
565 erratum_383_found = true;
568 static void svm_init_osvw(struct kvm_vcpu *vcpu)
571 * Guests should see errata 400 and 415 as fixed (assuming that
572 * HLT and IO instructions are intercepted).
574 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
575 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
578 * By increasing VCPU's osvw.length to 3 we are telling the guest that
579 * all osvw.status bits inside that length, including bit 0 (which is
580 * reserved for erratum 298), are valid. However, if host processor's
581 * osvw_len is 0 then osvw_status[0] carries no information. We need to
582 * be conservative here and therefore we tell the guest that erratum 298
583 * is present (because we really don't know).
585 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
586 vcpu->arch.osvw.status |= 1;
589 static int has_svm(void)
593 if (!cpu_has_svm(&msg)) {
594 printk(KERN_INFO "has_svm: %s\n", msg);
601 static void svm_hardware_disable(void *garbage)
603 /* Make sure we clean up behind us */
604 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
605 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
609 amd_pmu_disable_virt();
612 static int svm_hardware_enable(void *garbage)
615 struct svm_cpu_data *sd;
617 struct desc_ptr gdt_descr;
618 struct desc_struct *gdt;
619 int me = raw_smp_processor_id();
621 rdmsrl(MSR_EFER, efer);
622 if (efer & EFER_SVME)
626 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
630 sd = per_cpu(svm_data, me);
633 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
638 sd->asid_generation = 1;
639 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
640 sd->next_asid = sd->max_asid + 1;
642 native_store_gdt(&gdt_descr);
643 gdt = (struct desc_struct *)gdt_descr.address;
644 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
646 wrmsrl(MSR_EFER, efer | EFER_SVME);
648 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
650 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
651 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
652 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
659 * Note that it is possible to have a system with mixed processor
660 * revisions and therefore different OSVW bits. If bits are not the same
661 * on different processors then choose the worst case (i.e. if erratum
662 * is present on one processor and not on another then assume that the
663 * erratum is present everywhere).
665 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
666 uint64_t len, status = 0;
669 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
671 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
675 osvw_status = osvw_len = 0;
679 osvw_status |= status;
680 osvw_status &= (1ULL << osvw_len) - 1;
683 osvw_status = osvw_len = 0;
685 svm_init_erratum_383();
687 amd_pmu_enable_virt();
692 static void svm_cpu_uninit(int cpu)
694 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
699 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
700 __free_page(sd->save_area);
704 static int svm_cpu_init(int cpu)
706 struct svm_cpu_data *sd;
709 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
713 sd->save_area = alloc_page(GFP_KERNEL);
718 per_cpu(svm_data, cpu) = sd;
728 static bool valid_msr_intercept(u32 index)
732 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
733 if (direct_access_msrs[i].index == index)
739 static void set_msr_interception(u32 *msrpm, unsigned msr,
742 u8 bit_read, bit_write;
747 * If this warning triggers extend the direct_access_msrs list at the
748 * beginning of the file
750 WARN_ON(!valid_msr_intercept(msr));
752 offset = svm_msrpm_offset(msr);
753 bit_read = 2 * (msr & 0x0f);
754 bit_write = 2 * (msr & 0x0f) + 1;
757 BUG_ON(offset == MSR_INVALID);
759 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
760 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
765 static void svm_vcpu_init_msrpm(u32 *msrpm)
769 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
771 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
772 if (!direct_access_msrs[i].always)
775 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
779 static void add_msr_offset(u32 offset)
783 for (i = 0; i < MSRPM_OFFSETS; ++i) {
785 /* Offset already in list? */
786 if (msrpm_offsets[i] == offset)
789 /* Slot used by another offset? */
790 if (msrpm_offsets[i] != MSR_INVALID)
793 /* Add offset to list */
794 msrpm_offsets[i] = offset;
800 * If this BUG triggers the msrpm_offsets table has an overflow. Just
801 * increase MSRPM_OFFSETS in this case.
806 static void init_msrpm_offsets(void)
810 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
812 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
815 offset = svm_msrpm_offset(direct_access_msrs[i].index);
816 BUG_ON(offset == MSR_INVALID);
818 add_msr_offset(offset);
822 static void svm_enable_lbrv(struct vcpu_svm *svm)
824 u32 *msrpm = svm->msrpm;
826 svm->vmcb->control.lbr_ctl = 1;
827 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
828 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
829 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
830 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
833 static void svm_disable_lbrv(struct vcpu_svm *svm)
835 u32 *msrpm = svm->msrpm;
837 svm->vmcb->control.lbr_ctl = 0;
838 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
839 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
840 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
841 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
844 static __init int svm_hardware_setup(void)
847 struct page *iopm_pages;
851 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
856 iopm_va = page_address(iopm_pages);
857 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
858 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
860 init_msrpm_offsets();
862 if (boot_cpu_has(X86_FEATURE_NX))
863 kvm_enable_efer_bits(EFER_NX);
865 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
866 kvm_enable_efer_bits(EFER_FFXSR);
868 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
871 kvm_has_tsc_control = true;
874 * Make sure the user can only configure tsc_khz values that
875 * fit into a signed integer.
876 * A min value is not calculated needed because it will always
877 * be 1 on all machines and a value of 0 is used to disable
878 * tsc-scaling for the vcpu.
880 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
882 kvm_max_guest_tsc_khz = max;
886 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
887 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
890 for_each_possible_cpu(cpu) {
891 r = svm_cpu_init(cpu);
896 if (!boot_cpu_has(X86_FEATURE_NPT))
899 if (npt_enabled && !npt) {
900 printk(KERN_INFO "kvm: Nested Paging disabled\n");
905 printk(KERN_INFO "kvm: Nested Paging enabled\n");
913 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
918 static __exit void svm_hardware_unsetup(void)
922 for_each_possible_cpu(cpu)
925 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
929 static void init_seg(struct vmcb_seg *seg)
932 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
933 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
938 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
941 seg->attrib = SVM_SELECTOR_P_MASK | type;
946 static u64 __scale_tsc(u64 ratio, u64 tsc)
948 u64 mult, frac, _tsc;
951 frac = ratio & ((1ULL << 32) - 1);
955 _tsc += (tsc >> 32) * frac;
956 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
961 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
963 struct vcpu_svm *svm = to_svm(vcpu);
966 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
967 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
972 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
974 struct vcpu_svm *svm = to_svm(vcpu);
978 /* Guest TSC same frequency as host TSC? */
980 svm->tsc_ratio = TSC_RATIO_DEFAULT;
984 /* TSC scaling supported? */
985 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
986 if (user_tsc_khz > tsc_khz) {
987 vcpu->arch.tsc_catchup = 1;
988 vcpu->arch.tsc_always_catchup = 1;
990 WARN(1, "user requested TSC rate below hardware speed\n");
996 /* TSC scaling required - calculate ratio */
998 do_div(ratio, tsc_khz);
1000 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1001 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1005 svm->tsc_ratio = ratio;
1008 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1010 struct vcpu_svm *svm = to_svm(vcpu);
1011 u64 g_tsc_offset = 0;
1013 if (is_guest_mode(vcpu)) {
1014 g_tsc_offset = svm->vmcb->control.tsc_offset -
1015 svm->nested.hsave->control.tsc_offset;
1016 svm->nested.hsave->control.tsc_offset = offset;
1019 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1021 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1024 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1026 struct vcpu_svm *svm = to_svm(vcpu);
1028 WARN_ON(adjustment < 0);
1030 adjustment = svm_scale_tsc(vcpu, adjustment);
1032 svm->vmcb->control.tsc_offset += adjustment;
1033 if (is_guest_mode(vcpu))
1034 svm->nested.hsave->control.tsc_offset += adjustment;
1035 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1038 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1042 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1044 return target_tsc - tsc;
1047 static void init_vmcb(struct vcpu_svm *svm)
1049 struct vmcb_control_area *control = &svm->vmcb->control;
1050 struct vmcb_save_area *save = &svm->vmcb->save;
1052 svm->vcpu.fpu_active = 1;
1053 svm->vcpu.arch.hflags = 0;
1055 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1056 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1057 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1058 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1059 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1060 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1061 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1063 set_dr_intercept(svm, INTERCEPT_DR0_READ);
1064 set_dr_intercept(svm, INTERCEPT_DR1_READ);
1065 set_dr_intercept(svm, INTERCEPT_DR2_READ);
1066 set_dr_intercept(svm, INTERCEPT_DR3_READ);
1067 set_dr_intercept(svm, INTERCEPT_DR4_READ);
1068 set_dr_intercept(svm, INTERCEPT_DR5_READ);
1069 set_dr_intercept(svm, INTERCEPT_DR6_READ);
1070 set_dr_intercept(svm, INTERCEPT_DR7_READ);
1072 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1073 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1074 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1075 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1076 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1077 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1078 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1079 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1081 set_exception_intercept(svm, PF_VECTOR);
1082 set_exception_intercept(svm, UD_VECTOR);
1083 set_exception_intercept(svm, MC_VECTOR);
1085 set_intercept(svm, INTERCEPT_INTR);
1086 set_intercept(svm, INTERCEPT_NMI);
1087 set_intercept(svm, INTERCEPT_SMI);
1088 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1089 set_intercept(svm, INTERCEPT_RDPMC);
1090 set_intercept(svm, INTERCEPT_CPUID);
1091 set_intercept(svm, INTERCEPT_INVD);
1092 set_intercept(svm, INTERCEPT_HLT);
1093 set_intercept(svm, INTERCEPT_INVLPG);
1094 set_intercept(svm, INTERCEPT_INVLPGA);
1095 set_intercept(svm, INTERCEPT_IOIO_PROT);
1096 set_intercept(svm, INTERCEPT_MSR_PROT);
1097 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1098 set_intercept(svm, INTERCEPT_SHUTDOWN);
1099 set_intercept(svm, INTERCEPT_VMRUN);
1100 set_intercept(svm, INTERCEPT_VMMCALL);
1101 set_intercept(svm, INTERCEPT_VMLOAD);
1102 set_intercept(svm, INTERCEPT_VMSAVE);
1103 set_intercept(svm, INTERCEPT_STGI);
1104 set_intercept(svm, INTERCEPT_CLGI);
1105 set_intercept(svm, INTERCEPT_SKINIT);
1106 set_intercept(svm, INTERCEPT_WBINVD);
1107 set_intercept(svm, INTERCEPT_MONITOR);
1108 set_intercept(svm, INTERCEPT_MWAIT);
1109 set_intercept(svm, INTERCEPT_XSETBV);
1111 control->iopm_base_pa = iopm_base;
1112 control->msrpm_base_pa = __pa(svm->msrpm);
1113 control->int_ctl = V_INTR_MASKING_MASK;
1115 init_seg(&save->es);
1116 init_seg(&save->ss);
1117 init_seg(&save->ds);
1118 init_seg(&save->fs);
1119 init_seg(&save->gs);
1121 save->cs.selector = 0xf000;
1122 /* Executable/Readable Code Segment */
1123 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1124 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1125 save->cs.limit = 0xffff;
1127 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1128 * be consistent with it.
1130 * Replace when we have real mode working for vmx.
1132 save->cs.base = 0xf0000;
1134 save->gdtr.limit = 0xffff;
1135 save->idtr.limit = 0xffff;
1137 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1138 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1140 svm_set_efer(&svm->vcpu, 0);
1141 save->dr6 = 0xffff0ff0;
1143 kvm_set_rflags(&svm->vcpu, 2);
1144 save->rip = 0x0000fff0;
1145 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1148 * This is the guest-visible cr0 value.
1149 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1151 svm->vcpu.arch.cr0 = 0;
1152 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1154 save->cr4 = X86_CR4_PAE;
1158 /* Setup VMCB for Nested Paging */
1159 control->nested_ctl = 1;
1160 clr_intercept(svm, INTERCEPT_INVLPG);
1161 clr_exception_intercept(svm, PF_VECTOR);
1162 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1163 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1164 save->g_pat = 0x0007040600070406ULL;
1168 svm->asid_generation = 0;
1170 svm->nested.vmcb = 0;
1171 svm->vcpu.arch.hflags = 0;
1173 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1174 control->pause_filter_count = 3000;
1175 set_intercept(svm, INTERCEPT_PAUSE);
1178 mark_all_dirty(svm->vmcb);
1183 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1185 struct vcpu_svm *svm = to_svm(vcpu);
1189 if (!kvm_vcpu_is_bsp(vcpu)) {
1190 kvm_rip_write(vcpu, 0);
1191 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1192 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1194 vcpu->arch.regs_avail = ~0;
1195 vcpu->arch.regs_dirty = ~0;
1200 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1202 struct vcpu_svm *svm;
1204 struct page *msrpm_pages;
1205 struct page *hsave_page;
1206 struct page *nested_msrpm_pages;
1209 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1215 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1217 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1222 page = alloc_page(GFP_KERNEL);
1226 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1230 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1231 if (!nested_msrpm_pages)
1234 hsave_page = alloc_page(GFP_KERNEL);
1238 svm->nested.hsave = page_address(hsave_page);
1240 svm->msrpm = page_address(msrpm_pages);
1241 svm_vcpu_init_msrpm(svm->msrpm);
1243 svm->nested.msrpm = page_address(nested_msrpm_pages);
1244 svm_vcpu_init_msrpm(svm->nested.msrpm);
1246 svm->vmcb = page_address(page);
1247 clear_page(svm->vmcb);
1248 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1249 svm->asid_generation = 0;
1251 kvm_write_tsc(&svm->vcpu, 0);
1253 err = fx_init(&svm->vcpu);
1257 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1258 if (kvm_vcpu_is_bsp(&svm->vcpu))
1259 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1261 svm_init_osvw(&svm->vcpu);
1266 __free_page(hsave_page);
1268 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1270 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1274 kvm_vcpu_uninit(&svm->vcpu);
1276 kmem_cache_free(kvm_vcpu_cache, svm);
1278 return ERR_PTR(err);
1281 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1283 struct vcpu_svm *svm = to_svm(vcpu);
1285 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1286 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1287 __free_page(virt_to_page(svm->nested.hsave));
1288 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1289 kvm_vcpu_uninit(vcpu);
1290 kmem_cache_free(kvm_vcpu_cache, svm);
1293 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1295 struct vcpu_svm *svm = to_svm(vcpu);
1298 if (unlikely(cpu != vcpu->cpu)) {
1299 svm->asid_generation = 0;
1300 mark_all_dirty(svm->vmcb);
1303 #ifdef CONFIG_X86_64
1304 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1306 savesegment(fs, svm->host.fs);
1307 savesegment(gs, svm->host.gs);
1308 svm->host.ldt = kvm_read_ldt();
1310 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1311 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1313 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1314 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1315 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1316 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1320 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1322 struct vcpu_svm *svm = to_svm(vcpu);
1325 ++vcpu->stat.host_state_reload;
1326 kvm_load_ldt(svm->host.ldt);
1327 #ifdef CONFIG_X86_64
1328 loadsegment(fs, svm->host.fs);
1329 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1330 load_gs_index(svm->host.gs);
1332 #ifdef CONFIG_X86_32_LAZY_GS
1333 loadsegment(gs, svm->host.gs);
1336 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1337 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1340 static void svm_update_cpl(struct kvm_vcpu *vcpu)
1342 struct vcpu_svm *svm = to_svm(vcpu);
1345 if (!is_protmode(vcpu))
1347 else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1350 cpl = svm->vmcb->save.cs.selector & 0x3;
1352 svm->vmcb->save.cpl = cpl;
1355 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1357 return to_svm(vcpu)->vmcb->save.rflags;
1360 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1362 unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1364 to_svm(vcpu)->vmcb->save.rflags = rflags;
1365 if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1366 svm_update_cpl(vcpu);
1369 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1372 case VCPU_EXREG_PDPTR:
1373 BUG_ON(!npt_enabled);
1374 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1381 static void svm_set_vintr(struct vcpu_svm *svm)
1383 set_intercept(svm, INTERCEPT_VINTR);
1386 static void svm_clear_vintr(struct vcpu_svm *svm)
1388 clr_intercept(svm, INTERCEPT_VINTR);
1391 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1393 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1396 case VCPU_SREG_CS: return &save->cs;
1397 case VCPU_SREG_DS: return &save->ds;
1398 case VCPU_SREG_ES: return &save->es;
1399 case VCPU_SREG_FS: return &save->fs;
1400 case VCPU_SREG_GS: return &save->gs;
1401 case VCPU_SREG_SS: return &save->ss;
1402 case VCPU_SREG_TR: return &save->tr;
1403 case VCPU_SREG_LDTR: return &save->ldtr;
1409 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1411 struct vmcb_seg *s = svm_seg(vcpu, seg);
1416 static void svm_get_segment(struct kvm_vcpu *vcpu,
1417 struct kvm_segment *var, int seg)
1419 struct vmcb_seg *s = svm_seg(vcpu, seg);
1421 var->base = s->base;
1422 var->limit = s->limit;
1423 var->selector = s->selector;
1424 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1425 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1426 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1427 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1428 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1429 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1430 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1431 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1434 * AMD's VMCB does not have an explicit unusable field, so emulate it
1435 * for cross vendor migration purposes by "not present"
1437 var->unusable = !var->present || (var->type == 0);
1442 * SVM always stores 0 for the 'G' bit in the CS selector in
1443 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1444 * Intel's VMENTRY has a check on the 'G' bit.
1446 var->g = s->limit > 0xfffff;
1450 * Work around a bug where the busy flag in the tr selector
1460 * The accessed bit must always be set in the segment
1461 * descriptor cache, although it can be cleared in the
1462 * descriptor, the cached bit always remains at 1. Since
1463 * Intel has a check on this, set it here to support
1464 * cross-vendor migration.
1471 * On AMD CPUs sometimes the DB bit in the segment
1472 * descriptor is left as 1, although the whole segment has
1473 * been made unusable. Clear it here to pass an Intel VMX
1474 * entry check when cross vendor migrating.
1482 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1484 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1489 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1491 struct vcpu_svm *svm = to_svm(vcpu);
1493 dt->size = svm->vmcb->save.idtr.limit;
1494 dt->address = svm->vmcb->save.idtr.base;
1497 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1499 struct vcpu_svm *svm = to_svm(vcpu);
1501 svm->vmcb->save.idtr.limit = dt->size;
1502 svm->vmcb->save.idtr.base = dt->address ;
1503 mark_dirty(svm->vmcb, VMCB_DT);
1506 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1508 struct vcpu_svm *svm = to_svm(vcpu);
1510 dt->size = svm->vmcb->save.gdtr.limit;
1511 dt->address = svm->vmcb->save.gdtr.base;
1514 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1516 struct vcpu_svm *svm = to_svm(vcpu);
1518 svm->vmcb->save.gdtr.limit = dt->size;
1519 svm->vmcb->save.gdtr.base = dt->address ;
1520 mark_dirty(svm->vmcb, VMCB_DT);
1523 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1527 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1531 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1535 static void update_cr0_intercept(struct vcpu_svm *svm)
1537 ulong gcr0 = svm->vcpu.arch.cr0;
1538 u64 *hcr0 = &svm->vmcb->save.cr0;
1540 if (!svm->vcpu.fpu_active)
1541 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1543 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1544 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1546 mark_dirty(svm->vmcb, VMCB_CR);
1548 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1549 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1550 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1552 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1553 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1557 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1559 struct vcpu_svm *svm = to_svm(vcpu);
1561 #ifdef CONFIG_X86_64
1562 if (vcpu->arch.efer & EFER_LME) {
1563 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1564 vcpu->arch.efer |= EFER_LMA;
1565 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1568 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1569 vcpu->arch.efer &= ~EFER_LMA;
1570 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1574 vcpu->arch.cr0 = cr0;
1577 cr0 |= X86_CR0_PG | X86_CR0_WP;
1579 if (!vcpu->fpu_active)
1582 * re-enable caching here because the QEMU bios
1583 * does not do it - this results in some delay at
1586 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1587 svm->vmcb->save.cr0 = cr0;
1588 mark_dirty(svm->vmcb, VMCB_CR);
1589 update_cr0_intercept(svm);
1592 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1594 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1595 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1597 if (cr4 & X86_CR4_VMXE)
1600 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1601 svm_flush_tlb(vcpu);
1603 vcpu->arch.cr4 = cr4;
1606 cr4 |= host_cr4_mce;
1607 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1608 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1612 static void svm_set_segment(struct kvm_vcpu *vcpu,
1613 struct kvm_segment *var, int seg)
1615 struct vcpu_svm *svm = to_svm(vcpu);
1616 struct vmcb_seg *s = svm_seg(vcpu, seg);
1618 s->base = var->base;
1619 s->limit = var->limit;
1620 s->selector = var->selector;
1624 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1625 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1626 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1627 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1628 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1629 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1630 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1631 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1633 if (seg == VCPU_SREG_CS)
1634 svm_update_cpl(vcpu);
1636 mark_dirty(svm->vmcb, VMCB_SEG);
1639 static void update_db_intercept(struct kvm_vcpu *vcpu)
1641 struct vcpu_svm *svm = to_svm(vcpu);
1643 clr_exception_intercept(svm, DB_VECTOR);
1644 clr_exception_intercept(svm, BP_VECTOR);
1646 if (svm->nmi_singlestep)
1647 set_exception_intercept(svm, DB_VECTOR);
1649 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1650 if (vcpu->guest_debug &
1651 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1652 set_exception_intercept(svm, DB_VECTOR);
1653 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1654 set_exception_intercept(svm, BP_VECTOR);
1656 vcpu->guest_debug = 0;
1659 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1661 struct vcpu_svm *svm = to_svm(vcpu);
1663 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1664 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1666 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1668 mark_dirty(svm->vmcb, VMCB_DR);
1670 update_db_intercept(vcpu);
1673 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1675 if (sd->next_asid > sd->max_asid) {
1676 ++sd->asid_generation;
1678 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1681 svm->asid_generation = sd->asid_generation;
1682 svm->vmcb->control.asid = sd->next_asid++;
1684 mark_dirty(svm->vmcb, VMCB_ASID);
1687 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1689 struct vcpu_svm *svm = to_svm(vcpu);
1691 svm->vmcb->save.dr7 = value;
1692 mark_dirty(svm->vmcb, VMCB_DR);
1695 static int pf_interception(struct vcpu_svm *svm)
1697 u64 fault_address = svm->vmcb->control.exit_info_2;
1701 switch (svm->apf_reason) {
1703 error_code = svm->vmcb->control.exit_info_1;
1705 trace_kvm_page_fault(fault_address, error_code);
1706 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1707 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1708 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1709 svm->vmcb->control.insn_bytes,
1710 svm->vmcb->control.insn_len);
1712 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1713 svm->apf_reason = 0;
1714 local_irq_disable();
1715 kvm_async_pf_task_wait(fault_address);
1718 case KVM_PV_REASON_PAGE_READY:
1719 svm->apf_reason = 0;
1720 local_irq_disable();
1721 kvm_async_pf_task_wake(fault_address);
1728 static int db_interception(struct vcpu_svm *svm)
1730 struct kvm_run *kvm_run = svm->vcpu.run;
1732 if (!(svm->vcpu.guest_debug &
1733 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1734 !svm->nmi_singlestep) {
1735 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1739 if (svm->nmi_singlestep) {
1740 svm->nmi_singlestep = false;
1741 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1742 svm->vmcb->save.rflags &=
1743 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1744 update_db_intercept(&svm->vcpu);
1747 if (svm->vcpu.guest_debug &
1748 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1749 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1750 kvm_run->debug.arch.pc =
1751 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1752 kvm_run->debug.arch.exception = DB_VECTOR;
1759 static int bp_interception(struct vcpu_svm *svm)
1761 struct kvm_run *kvm_run = svm->vcpu.run;
1763 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1764 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1765 kvm_run->debug.arch.exception = BP_VECTOR;
1769 static int ud_interception(struct vcpu_svm *svm)
1773 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1774 if (er != EMULATE_DONE)
1775 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1779 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1781 struct vcpu_svm *svm = to_svm(vcpu);
1783 clr_exception_intercept(svm, NM_VECTOR);
1785 svm->vcpu.fpu_active = 1;
1786 update_cr0_intercept(svm);
1789 static int nm_interception(struct vcpu_svm *svm)
1791 svm_fpu_activate(&svm->vcpu);
1795 static bool is_erratum_383(void)
1800 if (!erratum_383_found)
1803 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1807 /* Bit 62 may or may not be set for this mce */
1808 value &= ~(1ULL << 62);
1810 if (value != 0xb600000000010015ULL)
1813 /* Clear MCi_STATUS registers */
1814 for (i = 0; i < 6; ++i)
1815 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1817 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1821 value &= ~(1ULL << 2);
1822 low = lower_32_bits(value);
1823 high = upper_32_bits(value);
1825 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1828 /* Flush tlb to evict multi-match entries */
1834 static void svm_handle_mce(struct vcpu_svm *svm)
1836 if (is_erratum_383()) {
1838 * Erratum 383 triggered. Guest state is corrupt so kill the
1841 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1843 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1849 * On an #MC intercept the MCE handler is not called automatically in
1850 * the host. So do it by hand here.
1854 /* not sure if we ever come back to this point */
1859 static int mc_interception(struct vcpu_svm *svm)
1864 static int shutdown_interception(struct vcpu_svm *svm)
1866 struct kvm_run *kvm_run = svm->vcpu.run;
1869 * VMCB is undefined after a SHUTDOWN intercept
1870 * so reinitialize it.
1872 clear_page(svm->vmcb);
1875 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1879 static int io_interception(struct vcpu_svm *svm)
1881 struct kvm_vcpu *vcpu = &svm->vcpu;
1882 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1883 int size, in, string;
1886 ++svm->vcpu.stat.io_exits;
1887 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1888 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1890 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1892 port = io_info >> 16;
1893 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1894 svm->next_rip = svm->vmcb->control.exit_info_2;
1895 skip_emulated_instruction(&svm->vcpu);
1897 return kvm_fast_pio_out(vcpu, size, port);
1900 static int nmi_interception(struct vcpu_svm *svm)
1905 static int intr_interception(struct vcpu_svm *svm)
1907 ++svm->vcpu.stat.irq_exits;
1911 static int nop_on_interception(struct vcpu_svm *svm)
1916 static int halt_interception(struct vcpu_svm *svm)
1918 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1919 skip_emulated_instruction(&svm->vcpu);
1920 return kvm_emulate_halt(&svm->vcpu);
1923 static int vmmcall_interception(struct vcpu_svm *svm)
1925 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1926 skip_emulated_instruction(&svm->vcpu);
1927 kvm_emulate_hypercall(&svm->vcpu);
1931 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1933 struct vcpu_svm *svm = to_svm(vcpu);
1935 return svm->nested.nested_cr3;
1938 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1940 struct vcpu_svm *svm = to_svm(vcpu);
1941 u64 cr3 = svm->nested.nested_cr3;
1945 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1946 offset_in_page(cr3) + index * 8, 8);
1952 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1955 struct vcpu_svm *svm = to_svm(vcpu);
1957 svm->vmcb->control.nested_cr3 = root;
1958 mark_dirty(svm->vmcb, VMCB_NPT);
1959 svm_flush_tlb(vcpu);
1962 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1963 struct x86_exception *fault)
1965 struct vcpu_svm *svm = to_svm(vcpu);
1967 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1968 svm->vmcb->control.exit_code_hi = 0;
1969 svm->vmcb->control.exit_info_1 = fault->error_code;
1970 svm->vmcb->control.exit_info_2 = fault->address;
1972 nested_svm_vmexit(svm);
1975 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1979 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1981 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1982 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1983 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1984 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1985 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1986 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1991 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1993 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1996 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1998 if (!(svm->vcpu.arch.efer & EFER_SVME)
1999 || !is_paging(&svm->vcpu)) {
2000 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2004 if (svm->vmcb->save.cpl) {
2005 kvm_inject_gp(&svm->vcpu, 0);
2012 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2013 bool has_error_code, u32 error_code)
2017 if (!is_guest_mode(&svm->vcpu))
2020 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2021 svm->vmcb->control.exit_code_hi = 0;
2022 svm->vmcb->control.exit_info_1 = error_code;
2023 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2025 vmexit = nested_svm_intercept(svm);
2026 if (vmexit == NESTED_EXIT_DONE)
2027 svm->nested.exit_required = true;
2032 /* This function returns true if it is save to enable the irq window */
2033 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2035 if (!is_guest_mode(&svm->vcpu))
2038 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2041 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2045 * if vmexit was already requested (by intercepted exception
2046 * for instance) do not overwrite it with "external interrupt"
2049 if (svm->nested.exit_required)
2052 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2053 svm->vmcb->control.exit_info_1 = 0;
2054 svm->vmcb->control.exit_info_2 = 0;
2056 if (svm->nested.intercept & 1ULL) {
2058 * The #vmexit can't be emulated here directly because this
2059 * code path runs with irqs and preemtion disabled. A
2060 * #vmexit emulation might sleep. Only signal request for
2063 svm->nested.exit_required = true;
2064 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2071 /* This function returns true if it is save to enable the nmi window */
2072 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2074 if (!is_guest_mode(&svm->vcpu))
2077 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2080 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2081 svm->nested.exit_required = true;
2086 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2092 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2093 if (is_error_page(page))
2101 kvm_release_page_clean(page);
2102 kvm_inject_gp(&svm->vcpu, 0);
2107 static void nested_svm_unmap(struct page *page)
2110 kvm_release_page_dirty(page);
2113 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2119 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2120 return NESTED_EXIT_HOST;
2122 port = svm->vmcb->control.exit_info_1 >> 16;
2123 gpa = svm->nested.vmcb_iopm + (port / 8);
2127 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2130 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2133 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2135 u32 offset, msr, value;
2138 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2139 return NESTED_EXIT_HOST;
2141 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2142 offset = svm_msrpm_offset(msr);
2143 write = svm->vmcb->control.exit_info_1 & 1;
2144 mask = 1 << ((2 * (msr & 0xf)) + write);
2146 if (offset == MSR_INVALID)
2147 return NESTED_EXIT_DONE;
2149 /* Offset is in 32 bit units but need in 8 bit units */
2152 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2153 return NESTED_EXIT_DONE;
2155 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2158 static int nested_svm_exit_special(struct vcpu_svm *svm)
2160 u32 exit_code = svm->vmcb->control.exit_code;
2162 switch (exit_code) {
2165 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2166 return NESTED_EXIT_HOST;
2168 /* For now we are always handling NPFs when using them */
2170 return NESTED_EXIT_HOST;
2172 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2173 /* When we're shadowing, trap PFs, but not async PF */
2174 if (!npt_enabled && svm->apf_reason == 0)
2175 return NESTED_EXIT_HOST;
2177 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2178 nm_interception(svm);
2184 return NESTED_EXIT_CONTINUE;
2188 * If this function returns true, this #vmexit was already handled
2190 static int nested_svm_intercept(struct vcpu_svm *svm)
2192 u32 exit_code = svm->vmcb->control.exit_code;
2193 int vmexit = NESTED_EXIT_HOST;
2195 switch (exit_code) {
2197 vmexit = nested_svm_exit_handled_msr(svm);
2200 vmexit = nested_svm_intercept_ioio(svm);
2202 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2203 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2204 if (svm->nested.intercept_cr & bit)
2205 vmexit = NESTED_EXIT_DONE;
2208 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2209 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2210 if (svm->nested.intercept_dr & bit)
2211 vmexit = NESTED_EXIT_DONE;
2214 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2215 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2216 if (svm->nested.intercept_exceptions & excp_bits)
2217 vmexit = NESTED_EXIT_DONE;
2218 /* async page fault always cause vmexit */
2219 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2220 svm->apf_reason != 0)
2221 vmexit = NESTED_EXIT_DONE;
2224 case SVM_EXIT_ERR: {
2225 vmexit = NESTED_EXIT_DONE;
2229 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2230 if (svm->nested.intercept & exit_bits)
2231 vmexit = NESTED_EXIT_DONE;
2238 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2242 vmexit = nested_svm_intercept(svm);
2244 if (vmexit == NESTED_EXIT_DONE)
2245 nested_svm_vmexit(svm);
2250 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2252 struct vmcb_control_area *dst = &dst_vmcb->control;
2253 struct vmcb_control_area *from = &from_vmcb->control;
2255 dst->intercept_cr = from->intercept_cr;
2256 dst->intercept_dr = from->intercept_dr;
2257 dst->intercept_exceptions = from->intercept_exceptions;
2258 dst->intercept = from->intercept;
2259 dst->iopm_base_pa = from->iopm_base_pa;
2260 dst->msrpm_base_pa = from->msrpm_base_pa;
2261 dst->tsc_offset = from->tsc_offset;
2262 dst->asid = from->asid;
2263 dst->tlb_ctl = from->tlb_ctl;
2264 dst->int_ctl = from->int_ctl;
2265 dst->int_vector = from->int_vector;
2266 dst->int_state = from->int_state;
2267 dst->exit_code = from->exit_code;
2268 dst->exit_code_hi = from->exit_code_hi;
2269 dst->exit_info_1 = from->exit_info_1;
2270 dst->exit_info_2 = from->exit_info_2;
2271 dst->exit_int_info = from->exit_int_info;
2272 dst->exit_int_info_err = from->exit_int_info_err;
2273 dst->nested_ctl = from->nested_ctl;
2274 dst->event_inj = from->event_inj;
2275 dst->event_inj_err = from->event_inj_err;
2276 dst->nested_cr3 = from->nested_cr3;
2277 dst->lbr_ctl = from->lbr_ctl;
2280 static int nested_svm_vmexit(struct vcpu_svm *svm)
2282 struct vmcb *nested_vmcb;
2283 struct vmcb *hsave = svm->nested.hsave;
2284 struct vmcb *vmcb = svm->vmcb;
2287 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2288 vmcb->control.exit_info_1,
2289 vmcb->control.exit_info_2,
2290 vmcb->control.exit_int_info,
2291 vmcb->control.exit_int_info_err,
2294 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2298 /* Exit Guest-Mode */
2299 leave_guest_mode(&svm->vcpu);
2300 svm->nested.vmcb = 0;
2302 /* Give the current vmcb to the guest */
2305 nested_vmcb->save.es = vmcb->save.es;
2306 nested_vmcb->save.cs = vmcb->save.cs;
2307 nested_vmcb->save.ss = vmcb->save.ss;
2308 nested_vmcb->save.ds = vmcb->save.ds;
2309 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2310 nested_vmcb->save.idtr = vmcb->save.idtr;
2311 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2312 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2313 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2314 nested_vmcb->save.cr2 = vmcb->save.cr2;
2315 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2316 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2317 nested_vmcb->save.rip = vmcb->save.rip;
2318 nested_vmcb->save.rsp = vmcb->save.rsp;
2319 nested_vmcb->save.rax = vmcb->save.rax;
2320 nested_vmcb->save.dr7 = vmcb->save.dr7;
2321 nested_vmcb->save.dr6 = vmcb->save.dr6;
2322 nested_vmcb->save.cpl = vmcb->save.cpl;
2324 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2325 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2326 nested_vmcb->control.int_state = vmcb->control.int_state;
2327 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2328 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2329 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2330 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2331 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2332 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2333 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2336 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2337 * to make sure that we do not lose injected events. So check event_inj
2338 * here and copy it to exit_int_info if it is valid.
2339 * Exit_int_info and event_inj can't be both valid because the case
2340 * below only happens on a VMRUN instruction intercept which has
2341 * no valid exit_int_info set.
2343 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2344 struct vmcb_control_area *nc = &nested_vmcb->control;
2346 nc->exit_int_info = vmcb->control.event_inj;
2347 nc->exit_int_info_err = vmcb->control.event_inj_err;
2350 nested_vmcb->control.tlb_ctl = 0;
2351 nested_vmcb->control.event_inj = 0;
2352 nested_vmcb->control.event_inj_err = 0;
2354 /* We always set V_INTR_MASKING and remember the old value in hflags */
2355 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2356 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2358 /* Restore the original control entries */
2359 copy_vmcb_control_area(vmcb, hsave);
2361 kvm_clear_exception_queue(&svm->vcpu);
2362 kvm_clear_interrupt_queue(&svm->vcpu);
2364 svm->nested.nested_cr3 = 0;
2366 /* Restore selected save entries */
2367 svm->vmcb->save.es = hsave->save.es;
2368 svm->vmcb->save.cs = hsave->save.cs;
2369 svm->vmcb->save.ss = hsave->save.ss;
2370 svm->vmcb->save.ds = hsave->save.ds;
2371 svm->vmcb->save.gdtr = hsave->save.gdtr;
2372 svm->vmcb->save.idtr = hsave->save.idtr;
2373 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2374 svm_set_efer(&svm->vcpu, hsave->save.efer);
2375 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2376 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2378 svm->vmcb->save.cr3 = hsave->save.cr3;
2379 svm->vcpu.arch.cr3 = hsave->save.cr3;
2381 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2383 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2384 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2385 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2386 svm->vmcb->save.dr7 = 0;
2387 svm->vmcb->save.cpl = 0;
2388 svm->vmcb->control.exit_int_info = 0;
2390 mark_all_dirty(svm->vmcb);
2392 nested_svm_unmap(page);
2394 nested_svm_uninit_mmu_context(&svm->vcpu);
2395 kvm_mmu_reset_context(&svm->vcpu);
2396 kvm_mmu_load(&svm->vcpu);
2401 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2404 * This function merges the msr permission bitmaps of kvm and the
2405 * nested vmcb. It is omptimized in that it only merges the parts where
2406 * the kvm msr permission bitmap may contain zero bits
2410 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2413 for (i = 0; i < MSRPM_OFFSETS; i++) {
2417 if (msrpm_offsets[i] == 0xffffffff)
2420 p = msrpm_offsets[i];
2421 offset = svm->nested.vmcb_msrpm + (p * 4);
2423 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2426 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2429 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2434 static bool nested_vmcb_checks(struct vmcb *vmcb)
2436 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2439 if (vmcb->control.asid == 0)
2442 if (vmcb->control.nested_ctl && !npt_enabled)
2448 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2450 struct vmcb *nested_vmcb;
2451 struct vmcb *hsave = svm->nested.hsave;
2452 struct vmcb *vmcb = svm->vmcb;
2456 vmcb_gpa = svm->vmcb->save.rax;
2458 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2462 if (!nested_vmcb_checks(nested_vmcb)) {
2463 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2464 nested_vmcb->control.exit_code_hi = 0;
2465 nested_vmcb->control.exit_info_1 = 0;
2466 nested_vmcb->control.exit_info_2 = 0;
2468 nested_svm_unmap(page);
2473 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2474 nested_vmcb->save.rip,
2475 nested_vmcb->control.int_ctl,
2476 nested_vmcb->control.event_inj,
2477 nested_vmcb->control.nested_ctl);
2479 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2480 nested_vmcb->control.intercept_cr >> 16,
2481 nested_vmcb->control.intercept_exceptions,
2482 nested_vmcb->control.intercept);
2484 /* Clear internal status */
2485 kvm_clear_exception_queue(&svm->vcpu);
2486 kvm_clear_interrupt_queue(&svm->vcpu);
2489 * Save the old vmcb, so we don't need to pick what we save, but can
2490 * restore everything when a VMEXIT occurs
2492 hsave->save.es = vmcb->save.es;
2493 hsave->save.cs = vmcb->save.cs;
2494 hsave->save.ss = vmcb->save.ss;
2495 hsave->save.ds = vmcb->save.ds;
2496 hsave->save.gdtr = vmcb->save.gdtr;
2497 hsave->save.idtr = vmcb->save.idtr;
2498 hsave->save.efer = svm->vcpu.arch.efer;
2499 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2500 hsave->save.cr4 = svm->vcpu.arch.cr4;
2501 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2502 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2503 hsave->save.rsp = vmcb->save.rsp;
2504 hsave->save.rax = vmcb->save.rax;
2506 hsave->save.cr3 = vmcb->save.cr3;
2508 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2510 copy_vmcb_control_area(hsave, vmcb);
2512 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2513 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2515 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2517 if (nested_vmcb->control.nested_ctl) {
2518 kvm_mmu_unload(&svm->vcpu);
2519 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2520 nested_svm_init_mmu_context(&svm->vcpu);
2523 /* Load the nested guest state */
2524 svm->vmcb->save.es = nested_vmcb->save.es;
2525 svm->vmcb->save.cs = nested_vmcb->save.cs;
2526 svm->vmcb->save.ss = nested_vmcb->save.ss;
2527 svm->vmcb->save.ds = nested_vmcb->save.ds;
2528 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2529 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2530 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2531 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2532 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2533 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2535 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2536 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2538 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2540 /* Guest paging mode is active - reset mmu */
2541 kvm_mmu_reset_context(&svm->vcpu);
2543 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2544 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2545 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2546 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2548 /* In case we don't even reach vcpu_run, the fields are not updated */
2549 svm->vmcb->save.rax = nested_vmcb->save.rax;
2550 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2551 svm->vmcb->save.rip = nested_vmcb->save.rip;
2552 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2553 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2554 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2556 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2557 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2559 /* cache intercepts */
2560 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2561 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2562 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2563 svm->nested.intercept = nested_vmcb->control.intercept;
2565 svm_flush_tlb(&svm->vcpu);
2566 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2567 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2568 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2570 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2572 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2573 /* We only want the cr8 intercept bits of the guest */
2574 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2575 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2578 /* We don't want to see VMMCALLs from a nested guest */
2579 clr_intercept(svm, INTERCEPT_VMMCALL);
2581 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2582 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2583 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2584 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2585 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2586 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2588 nested_svm_unmap(page);
2590 /* Enter Guest-Mode */
2591 enter_guest_mode(&svm->vcpu);
2594 * Merge guest and host intercepts - must be called with vcpu in
2595 * guest-mode to take affect here
2597 recalc_intercepts(svm);
2599 svm->nested.vmcb = vmcb_gpa;
2603 mark_all_dirty(svm->vmcb);
2608 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2610 to_vmcb->save.fs = from_vmcb->save.fs;
2611 to_vmcb->save.gs = from_vmcb->save.gs;
2612 to_vmcb->save.tr = from_vmcb->save.tr;
2613 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2614 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2615 to_vmcb->save.star = from_vmcb->save.star;
2616 to_vmcb->save.lstar = from_vmcb->save.lstar;
2617 to_vmcb->save.cstar = from_vmcb->save.cstar;
2618 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2619 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2620 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2621 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2624 static int vmload_interception(struct vcpu_svm *svm)
2626 struct vmcb *nested_vmcb;
2629 if (nested_svm_check_permissions(svm))
2632 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2636 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2637 skip_emulated_instruction(&svm->vcpu);
2639 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2640 nested_svm_unmap(page);
2645 static int vmsave_interception(struct vcpu_svm *svm)
2647 struct vmcb *nested_vmcb;
2650 if (nested_svm_check_permissions(svm))
2653 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2657 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2658 skip_emulated_instruction(&svm->vcpu);
2660 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2661 nested_svm_unmap(page);
2666 static int vmrun_interception(struct vcpu_svm *svm)
2668 if (nested_svm_check_permissions(svm))
2671 /* Save rip after vmrun instruction */
2672 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2674 if (!nested_svm_vmrun(svm))
2677 if (!nested_svm_vmrun_msrpm(svm))
2684 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2685 svm->vmcb->control.exit_code_hi = 0;
2686 svm->vmcb->control.exit_info_1 = 0;
2687 svm->vmcb->control.exit_info_2 = 0;
2689 nested_svm_vmexit(svm);
2694 static int stgi_interception(struct vcpu_svm *svm)
2696 if (nested_svm_check_permissions(svm))
2699 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2700 skip_emulated_instruction(&svm->vcpu);
2701 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2708 static int clgi_interception(struct vcpu_svm *svm)
2710 if (nested_svm_check_permissions(svm))
2713 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2714 skip_emulated_instruction(&svm->vcpu);
2718 /* After a CLGI no interrupts should come */
2719 svm_clear_vintr(svm);
2720 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2722 mark_dirty(svm->vmcb, VMCB_INTR);
2727 static int invlpga_interception(struct vcpu_svm *svm)
2729 struct kvm_vcpu *vcpu = &svm->vcpu;
2731 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2732 vcpu->arch.regs[VCPU_REGS_RAX]);
2734 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2735 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2737 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2738 skip_emulated_instruction(&svm->vcpu);
2742 static int skinit_interception(struct vcpu_svm *svm)
2744 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2746 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2750 static int xsetbv_interception(struct vcpu_svm *svm)
2752 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2753 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2755 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2756 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2757 skip_emulated_instruction(&svm->vcpu);
2763 static int invalid_op_interception(struct vcpu_svm *svm)
2765 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2769 static int task_switch_interception(struct vcpu_svm *svm)
2773 int int_type = svm->vmcb->control.exit_int_info &
2774 SVM_EXITINTINFO_TYPE_MASK;
2775 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2777 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2779 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2780 bool has_error_code = false;
2783 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2785 if (svm->vmcb->control.exit_info_2 &
2786 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2787 reason = TASK_SWITCH_IRET;
2788 else if (svm->vmcb->control.exit_info_2 &
2789 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2790 reason = TASK_SWITCH_JMP;
2792 reason = TASK_SWITCH_GATE;
2794 reason = TASK_SWITCH_CALL;
2796 if (reason == TASK_SWITCH_GATE) {
2798 case SVM_EXITINTINFO_TYPE_NMI:
2799 svm->vcpu.arch.nmi_injected = false;
2801 case SVM_EXITINTINFO_TYPE_EXEPT:
2802 if (svm->vmcb->control.exit_info_2 &
2803 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2804 has_error_code = true;
2806 (u32)svm->vmcb->control.exit_info_2;
2808 kvm_clear_exception_queue(&svm->vcpu);
2810 case SVM_EXITINTINFO_TYPE_INTR:
2811 kvm_clear_interrupt_queue(&svm->vcpu);
2818 if (reason != TASK_SWITCH_GATE ||
2819 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2820 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2821 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2822 skip_emulated_instruction(&svm->vcpu);
2824 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2827 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2828 has_error_code, error_code) == EMULATE_FAIL) {
2829 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2830 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2831 svm->vcpu.run->internal.ndata = 0;
2837 static int cpuid_interception(struct vcpu_svm *svm)
2839 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2840 kvm_emulate_cpuid(&svm->vcpu);
2844 static int iret_interception(struct vcpu_svm *svm)
2846 ++svm->vcpu.stat.nmi_window_exits;
2847 clr_intercept(svm, INTERCEPT_IRET);
2848 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2849 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2853 static int invlpg_interception(struct vcpu_svm *svm)
2855 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2856 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2858 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2859 skip_emulated_instruction(&svm->vcpu);
2863 static int emulate_on_interception(struct vcpu_svm *svm)
2865 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2868 static int rdpmc_interception(struct vcpu_svm *svm)
2872 if (!static_cpu_has(X86_FEATURE_NRIPS))
2873 return emulate_on_interception(svm);
2875 err = kvm_rdpmc(&svm->vcpu);
2876 kvm_complete_insn_gp(&svm->vcpu, err);
2881 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2883 unsigned long cr0 = svm->vcpu.arch.cr0;
2887 intercept = svm->nested.intercept;
2889 if (!is_guest_mode(&svm->vcpu) ||
2890 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2893 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2894 val &= ~SVM_CR0_SELECTIVE_MASK;
2897 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2898 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2904 #define CR_VALID (1ULL << 63)
2906 static int cr_interception(struct vcpu_svm *svm)
2912 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2913 return emulate_on_interception(svm);
2915 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2916 return emulate_on_interception(svm);
2918 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2919 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2922 if (cr >= 16) { /* mov to cr */
2924 val = kvm_register_read(&svm->vcpu, reg);
2927 if (!check_selective_cr0_intercepted(svm, val))
2928 err = kvm_set_cr0(&svm->vcpu, val);
2934 err = kvm_set_cr3(&svm->vcpu, val);
2937 err = kvm_set_cr4(&svm->vcpu, val);
2940 err = kvm_set_cr8(&svm->vcpu, val);
2943 WARN(1, "unhandled write to CR%d", cr);
2944 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2947 } else { /* mov from cr */
2950 val = kvm_read_cr0(&svm->vcpu);
2953 val = svm->vcpu.arch.cr2;
2956 val = kvm_read_cr3(&svm->vcpu);
2959 val = kvm_read_cr4(&svm->vcpu);
2962 val = kvm_get_cr8(&svm->vcpu);
2965 WARN(1, "unhandled read from CR%d", cr);
2966 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2969 kvm_register_write(&svm->vcpu, reg, val);
2971 kvm_complete_insn_gp(&svm->vcpu, err);
2976 static int dr_interception(struct vcpu_svm *svm)
2982 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2983 return emulate_on_interception(svm);
2985 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2986 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2988 if (dr >= 16) { /* mov to DRn */
2989 val = kvm_register_read(&svm->vcpu, reg);
2990 kvm_set_dr(&svm->vcpu, dr - 16, val);
2992 err = kvm_get_dr(&svm->vcpu, dr, &val);
2994 kvm_register_write(&svm->vcpu, reg, val);
2997 skip_emulated_instruction(&svm->vcpu);
3002 static int cr8_write_interception(struct vcpu_svm *svm)
3004 struct kvm_run *kvm_run = svm->vcpu.run;
3007 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3008 /* instruction emulation calls kvm_set_cr8() */
3009 r = cr_interception(svm);
3010 if (irqchip_in_kernel(svm->vcpu.kvm)) {
3011 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3014 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3016 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3020 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu)
3022 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3023 return vmcb->control.tsc_offset +
3024 svm_scale_tsc(vcpu, native_read_tsc());
3027 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3029 struct vcpu_svm *svm = to_svm(vcpu);
3032 case MSR_IA32_TSC: {
3033 *data = svm->vmcb->control.tsc_offset +
3034 svm_scale_tsc(vcpu, native_read_tsc());
3039 *data = svm->vmcb->save.star;
3041 #ifdef CONFIG_X86_64
3043 *data = svm->vmcb->save.lstar;
3046 *data = svm->vmcb->save.cstar;
3048 case MSR_KERNEL_GS_BASE:
3049 *data = svm->vmcb->save.kernel_gs_base;
3051 case MSR_SYSCALL_MASK:
3052 *data = svm->vmcb->save.sfmask;
3055 case MSR_IA32_SYSENTER_CS:
3056 *data = svm->vmcb->save.sysenter_cs;
3058 case MSR_IA32_SYSENTER_EIP:
3059 *data = svm->sysenter_eip;
3061 case MSR_IA32_SYSENTER_ESP:
3062 *data = svm->sysenter_esp;
3065 * Nobody will change the following 5 values in the VMCB so we can
3066 * safely return them on rdmsr. They will always be 0 until LBRV is
3069 case MSR_IA32_DEBUGCTLMSR:
3070 *data = svm->vmcb->save.dbgctl;
3072 case MSR_IA32_LASTBRANCHFROMIP:
3073 *data = svm->vmcb->save.br_from;
3075 case MSR_IA32_LASTBRANCHTOIP:
3076 *data = svm->vmcb->save.br_to;
3078 case MSR_IA32_LASTINTFROMIP:
3079 *data = svm->vmcb->save.last_excp_from;
3081 case MSR_IA32_LASTINTTOIP:
3082 *data = svm->vmcb->save.last_excp_to;
3084 case MSR_VM_HSAVE_PA:
3085 *data = svm->nested.hsave_msr;
3088 *data = svm->nested.vm_cr_msr;
3090 case MSR_IA32_UCODE_REV:
3094 return kvm_get_msr_common(vcpu, ecx, data);
3099 static int rdmsr_interception(struct vcpu_svm *svm)
3101 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3104 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3105 trace_kvm_msr_read_ex(ecx);
3106 kvm_inject_gp(&svm->vcpu, 0);
3108 trace_kvm_msr_read(ecx, data);
3110 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3111 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3112 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3113 skip_emulated_instruction(&svm->vcpu);
3118 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3120 struct vcpu_svm *svm = to_svm(vcpu);
3121 int svm_dis, chg_mask;
3123 if (data & ~SVM_VM_CR_VALID_MASK)
3126 chg_mask = SVM_VM_CR_VALID_MASK;
3128 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3129 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3131 svm->nested.vm_cr_msr &= ~chg_mask;
3132 svm->nested.vm_cr_msr |= (data & chg_mask);
3134 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3136 /* check for svm_disable while efer.svme is set */
3137 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3143 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
3145 struct vcpu_svm *svm = to_svm(vcpu);
3149 kvm_write_tsc(vcpu, data);
3152 svm->vmcb->save.star = data;
3154 #ifdef CONFIG_X86_64
3156 svm->vmcb->save.lstar = data;
3159 svm->vmcb->save.cstar = data;
3161 case MSR_KERNEL_GS_BASE:
3162 svm->vmcb->save.kernel_gs_base = data;
3164 case MSR_SYSCALL_MASK:
3165 svm->vmcb->save.sfmask = data;
3168 case MSR_IA32_SYSENTER_CS:
3169 svm->vmcb->save.sysenter_cs = data;
3171 case MSR_IA32_SYSENTER_EIP:
3172 svm->sysenter_eip = data;
3173 svm->vmcb->save.sysenter_eip = data;
3175 case MSR_IA32_SYSENTER_ESP:
3176 svm->sysenter_esp = data;
3177 svm->vmcb->save.sysenter_esp = data;
3179 case MSR_IA32_DEBUGCTLMSR:
3180 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3181 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3185 if (data & DEBUGCTL_RESERVED_BITS)
3188 svm->vmcb->save.dbgctl = data;
3189 mark_dirty(svm->vmcb, VMCB_LBR);
3190 if (data & (1ULL<<0))
3191 svm_enable_lbrv(svm);
3193 svm_disable_lbrv(svm);
3195 case MSR_VM_HSAVE_PA:
3196 svm->nested.hsave_msr = data;
3199 return svm_set_vm_cr(vcpu, data);
3201 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3204 return kvm_set_msr_common(vcpu, ecx, data);
3209 static int wrmsr_interception(struct vcpu_svm *svm)
3211 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3212 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3213 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3216 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3217 if (svm_set_msr(&svm->vcpu, ecx, data)) {
3218 trace_kvm_msr_write_ex(ecx, data);
3219 kvm_inject_gp(&svm->vcpu, 0);
3221 trace_kvm_msr_write(ecx, data);
3222 skip_emulated_instruction(&svm->vcpu);
3227 static int msr_interception(struct vcpu_svm *svm)
3229 if (svm->vmcb->control.exit_info_1)
3230 return wrmsr_interception(svm);
3232 return rdmsr_interception(svm);
3235 static int interrupt_window_interception(struct vcpu_svm *svm)
3237 struct kvm_run *kvm_run = svm->vcpu.run;
3239 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3240 svm_clear_vintr(svm);
3241 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3242 mark_dirty(svm->vmcb, VMCB_INTR);
3244 * If the user space waits to inject interrupts, exit as soon as
3247 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3248 kvm_run->request_interrupt_window &&
3249 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3250 ++svm->vcpu.stat.irq_window_exits;
3251 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3258 static int pause_interception(struct vcpu_svm *svm)
3260 kvm_vcpu_on_spin(&(svm->vcpu));
3264 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3265 [SVM_EXIT_READ_CR0] = cr_interception,
3266 [SVM_EXIT_READ_CR3] = cr_interception,
3267 [SVM_EXIT_READ_CR4] = cr_interception,
3268 [SVM_EXIT_READ_CR8] = cr_interception,
3269 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3270 [SVM_EXIT_WRITE_CR0] = cr_interception,
3271 [SVM_EXIT_WRITE_CR3] = cr_interception,
3272 [SVM_EXIT_WRITE_CR4] = cr_interception,
3273 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3274 [SVM_EXIT_READ_DR0] = dr_interception,
3275 [SVM_EXIT_READ_DR1] = dr_interception,
3276 [SVM_EXIT_READ_DR2] = dr_interception,
3277 [SVM_EXIT_READ_DR3] = dr_interception,
3278 [SVM_EXIT_READ_DR4] = dr_interception,
3279 [SVM_EXIT_READ_DR5] = dr_interception,
3280 [SVM_EXIT_READ_DR6] = dr_interception,
3281 [SVM_EXIT_READ_DR7] = dr_interception,
3282 [SVM_EXIT_WRITE_DR0] = dr_interception,
3283 [SVM_EXIT_WRITE_DR1] = dr_interception,
3284 [SVM_EXIT_WRITE_DR2] = dr_interception,
3285 [SVM_EXIT_WRITE_DR3] = dr_interception,
3286 [SVM_EXIT_WRITE_DR4] = dr_interception,
3287 [SVM_EXIT_WRITE_DR5] = dr_interception,
3288 [SVM_EXIT_WRITE_DR6] = dr_interception,
3289 [SVM_EXIT_WRITE_DR7] = dr_interception,
3290 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3291 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3292 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3293 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3294 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3295 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3296 [SVM_EXIT_INTR] = intr_interception,
3297 [SVM_EXIT_NMI] = nmi_interception,
3298 [SVM_EXIT_SMI] = nop_on_interception,
3299 [SVM_EXIT_INIT] = nop_on_interception,
3300 [SVM_EXIT_VINTR] = interrupt_window_interception,
3301 [SVM_EXIT_RDPMC] = rdpmc_interception,
3302 [SVM_EXIT_CPUID] = cpuid_interception,
3303 [SVM_EXIT_IRET] = iret_interception,
3304 [SVM_EXIT_INVD] = emulate_on_interception,
3305 [SVM_EXIT_PAUSE] = pause_interception,
3306 [SVM_EXIT_HLT] = halt_interception,
3307 [SVM_EXIT_INVLPG] = invlpg_interception,
3308 [SVM_EXIT_INVLPGA] = invlpga_interception,
3309 [SVM_EXIT_IOIO] = io_interception,
3310 [SVM_EXIT_MSR] = msr_interception,
3311 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3312 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3313 [SVM_EXIT_VMRUN] = vmrun_interception,
3314 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3315 [SVM_EXIT_VMLOAD] = vmload_interception,
3316 [SVM_EXIT_VMSAVE] = vmsave_interception,
3317 [SVM_EXIT_STGI] = stgi_interception,
3318 [SVM_EXIT_CLGI] = clgi_interception,
3319 [SVM_EXIT_SKINIT] = skinit_interception,
3320 [SVM_EXIT_WBINVD] = emulate_on_interception,
3321 [SVM_EXIT_MONITOR] = invalid_op_interception,
3322 [SVM_EXIT_MWAIT] = invalid_op_interception,
3323 [SVM_EXIT_XSETBV] = xsetbv_interception,
3324 [SVM_EXIT_NPF] = pf_interception,
3327 static void dump_vmcb(struct kvm_vcpu *vcpu)
3329 struct vcpu_svm *svm = to_svm(vcpu);
3330 struct vmcb_control_area *control = &svm->vmcb->control;
3331 struct vmcb_save_area *save = &svm->vmcb->save;
3333 pr_err("VMCB Control Area:\n");
3334 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3335 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3336 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3337 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3338 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3339 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3340 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3341 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3342 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3343 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3344 pr_err("%-20s%d\n", "asid:", control->asid);
3345 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3346 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3347 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3348 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3349 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3350 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3351 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3352 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3353 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3354 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3355 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3356 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3357 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3358 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3359 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3360 pr_err("VMCB State Save Area:\n");
3361 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3363 save->es.selector, save->es.attrib,
3364 save->es.limit, save->es.base);
3365 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3367 save->cs.selector, save->cs.attrib,
3368 save->cs.limit, save->cs.base);
3369 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3371 save->ss.selector, save->ss.attrib,
3372 save->ss.limit, save->ss.base);
3373 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3375 save->ds.selector, save->ds.attrib,
3376 save->ds.limit, save->ds.base);
3377 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3379 save->fs.selector, save->fs.attrib,
3380 save->fs.limit, save->fs.base);
3381 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3383 save->gs.selector, save->gs.attrib,
3384 save->gs.limit, save->gs.base);
3385 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3387 save->gdtr.selector, save->gdtr.attrib,
3388 save->gdtr.limit, save->gdtr.base);
3389 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3391 save->ldtr.selector, save->ldtr.attrib,
3392 save->ldtr.limit, save->ldtr.base);
3393 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3395 save->idtr.selector, save->idtr.attrib,
3396 save->idtr.limit, save->idtr.base);
3397 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3399 save->tr.selector, save->tr.attrib,
3400 save->tr.limit, save->tr.base);
3401 pr_err("cpl: %d efer: %016llx\n",
3402 save->cpl, save->efer);
3403 pr_err("%-15s %016llx %-13s %016llx\n",
3404 "cr0:", save->cr0, "cr2:", save->cr2);
3405 pr_err("%-15s %016llx %-13s %016llx\n",
3406 "cr3:", save->cr3, "cr4:", save->cr4);
3407 pr_err("%-15s %016llx %-13s %016llx\n",
3408 "dr6:", save->dr6, "dr7:", save->dr7);
3409 pr_err("%-15s %016llx %-13s %016llx\n",
3410 "rip:", save->rip, "rflags:", save->rflags);
3411 pr_err("%-15s %016llx %-13s %016llx\n",
3412 "rsp:", save->rsp, "rax:", save->rax);
3413 pr_err("%-15s %016llx %-13s %016llx\n",
3414 "star:", save->star, "lstar:", save->lstar);
3415 pr_err("%-15s %016llx %-13s %016llx\n",
3416 "cstar:", save->cstar, "sfmask:", save->sfmask);
3417 pr_err("%-15s %016llx %-13s %016llx\n",
3418 "kernel_gs_base:", save->kernel_gs_base,
3419 "sysenter_cs:", save->sysenter_cs);
3420 pr_err("%-15s %016llx %-13s %016llx\n",
3421 "sysenter_esp:", save->sysenter_esp,
3422 "sysenter_eip:", save->sysenter_eip);
3423 pr_err("%-15s %016llx %-13s %016llx\n",
3424 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3425 pr_err("%-15s %016llx %-13s %016llx\n",
3426 "br_from:", save->br_from, "br_to:", save->br_to);
3427 pr_err("%-15s %016llx %-13s %016llx\n",
3428 "excp_from:", save->last_excp_from,
3429 "excp_to:", save->last_excp_to);
3432 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3434 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3436 *info1 = control->exit_info_1;
3437 *info2 = control->exit_info_2;
3440 static int handle_exit(struct kvm_vcpu *vcpu)
3442 struct vcpu_svm *svm = to_svm(vcpu);
3443 struct kvm_run *kvm_run = vcpu->run;
3444 u32 exit_code = svm->vmcb->control.exit_code;
3446 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3447 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3449 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3451 if (unlikely(svm->nested.exit_required)) {
3452 nested_svm_vmexit(svm);
3453 svm->nested.exit_required = false;
3458 if (is_guest_mode(vcpu)) {
3461 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3462 svm->vmcb->control.exit_info_1,
3463 svm->vmcb->control.exit_info_2,
3464 svm->vmcb->control.exit_int_info,
3465 svm->vmcb->control.exit_int_info_err,
3468 vmexit = nested_svm_exit_special(svm);
3470 if (vmexit == NESTED_EXIT_CONTINUE)
3471 vmexit = nested_svm_exit_handled(svm);
3473 if (vmexit == NESTED_EXIT_DONE)
3477 svm_complete_interrupts(svm);
3479 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3480 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3481 kvm_run->fail_entry.hardware_entry_failure_reason
3482 = svm->vmcb->control.exit_code;
3483 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3488 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3489 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3490 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3491 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3492 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3494 __func__, svm->vmcb->control.exit_int_info,
3497 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3498 || !svm_exit_handlers[exit_code]) {
3499 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3500 kvm_run->hw.hardware_exit_reason = exit_code;
3504 return svm_exit_handlers[exit_code](svm);
3507 static void reload_tss(struct kvm_vcpu *vcpu)
3509 int cpu = raw_smp_processor_id();
3511 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3512 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3516 static void pre_svm_run(struct vcpu_svm *svm)
3518 int cpu = raw_smp_processor_id();
3520 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3522 /* FIXME: handle wraparound of asid_generation */
3523 if (svm->asid_generation != sd->asid_generation)
3527 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3529 struct vcpu_svm *svm = to_svm(vcpu);
3531 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3532 vcpu->arch.hflags |= HF_NMI_MASK;
3533 set_intercept(svm, INTERCEPT_IRET);
3534 ++vcpu->stat.nmi_injections;
3537 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3539 struct vmcb_control_area *control;
3541 control = &svm->vmcb->control;
3542 control->int_vector = irq;
3543 control->int_ctl &= ~V_INTR_PRIO_MASK;
3544 control->int_ctl |= V_IRQ_MASK |
3545 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3546 mark_dirty(svm->vmcb, VMCB_INTR);
3549 static void svm_set_irq(struct kvm_vcpu *vcpu)
3551 struct vcpu_svm *svm = to_svm(vcpu);
3553 BUG_ON(!(gif_set(svm)));
3555 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3556 ++vcpu->stat.irq_injections;
3558 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3559 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3562 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3564 struct vcpu_svm *svm = to_svm(vcpu);
3566 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3573 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3576 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3578 struct vcpu_svm *svm = to_svm(vcpu);
3579 struct vmcb *vmcb = svm->vmcb;
3581 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3582 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3583 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3588 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3590 struct vcpu_svm *svm = to_svm(vcpu);
3592 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3595 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3597 struct vcpu_svm *svm = to_svm(vcpu);
3600 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3601 set_intercept(svm, INTERCEPT_IRET);
3603 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3604 clr_intercept(svm, INTERCEPT_IRET);
3608 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3610 struct vcpu_svm *svm = to_svm(vcpu);
3611 struct vmcb *vmcb = svm->vmcb;
3614 if (!gif_set(svm) ||
3615 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3618 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3620 if (is_guest_mode(vcpu))
3621 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3626 static void enable_irq_window(struct kvm_vcpu *vcpu)
3628 struct vcpu_svm *svm = to_svm(vcpu);
3631 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3632 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3633 * get that intercept, this function will be called again though and
3634 * we'll get the vintr intercept.
3636 if (gif_set(svm) && nested_svm_intr(svm)) {
3638 svm_inject_irq(svm, 0x0);
3642 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3644 struct vcpu_svm *svm = to_svm(vcpu);
3646 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3648 return; /* IRET will cause a vm exit */
3651 * Something prevents NMI from been injected. Single step over possible
3652 * problem (IRET or exception injection or interrupt shadow)
3654 svm->nmi_singlestep = true;
3655 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3656 update_db_intercept(vcpu);
3659 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3664 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3666 struct vcpu_svm *svm = to_svm(vcpu);
3668 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3669 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3671 svm->asid_generation--;
3674 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3678 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3680 struct vcpu_svm *svm = to_svm(vcpu);
3682 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3685 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3686 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3687 kvm_set_cr8(vcpu, cr8);
3691 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3693 struct vcpu_svm *svm = to_svm(vcpu);
3696 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3699 cr8 = kvm_get_cr8(vcpu);
3700 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3701 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3704 static void svm_complete_interrupts(struct vcpu_svm *svm)
3708 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3709 unsigned int3_injected = svm->int3_injected;
3711 svm->int3_injected = 0;
3714 * If we've made progress since setting HF_IRET_MASK, we've
3715 * executed an IRET and can allow NMI injection.
3717 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3718 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3719 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3720 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3723 svm->vcpu.arch.nmi_injected = false;
3724 kvm_clear_exception_queue(&svm->vcpu);
3725 kvm_clear_interrupt_queue(&svm->vcpu);
3727 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3730 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3732 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3733 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3736 case SVM_EXITINTINFO_TYPE_NMI:
3737 svm->vcpu.arch.nmi_injected = true;
3739 case SVM_EXITINTINFO_TYPE_EXEPT:
3741 * In case of software exceptions, do not reinject the vector,
3742 * but re-execute the instruction instead. Rewind RIP first
3743 * if we emulated INT3 before.
3745 if (kvm_exception_is_soft(vector)) {
3746 if (vector == BP_VECTOR && int3_injected &&
3747 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3748 kvm_rip_write(&svm->vcpu,
3749 kvm_rip_read(&svm->vcpu) -
3753 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3754 u32 err = svm->vmcb->control.exit_int_info_err;
3755 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3758 kvm_requeue_exception(&svm->vcpu, vector);
3760 case SVM_EXITINTINFO_TYPE_INTR:
3761 kvm_queue_interrupt(&svm->vcpu, vector, false);
3768 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3770 struct vcpu_svm *svm = to_svm(vcpu);
3771 struct vmcb_control_area *control = &svm->vmcb->control;
3773 control->exit_int_info = control->event_inj;
3774 control->exit_int_info_err = control->event_inj_err;
3775 control->event_inj = 0;
3776 svm_complete_interrupts(svm);
3779 #ifdef CONFIG_X86_64
3785 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3787 struct vcpu_svm *svm = to_svm(vcpu);
3789 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3790 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3791 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3794 * A vmexit emulation is required before the vcpu can be executed
3797 if (unlikely(svm->nested.exit_required))
3802 sync_lapic_to_cr8(vcpu);
3804 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3811 "push %%"R"bp; \n\t"
3812 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3813 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3814 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3815 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3816 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3817 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3818 #ifdef CONFIG_X86_64
3819 "mov %c[r8](%[svm]), %%r8 \n\t"
3820 "mov %c[r9](%[svm]), %%r9 \n\t"
3821 "mov %c[r10](%[svm]), %%r10 \n\t"
3822 "mov %c[r11](%[svm]), %%r11 \n\t"
3823 "mov %c[r12](%[svm]), %%r12 \n\t"
3824 "mov %c[r13](%[svm]), %%r13 \n\t"
3825 "mov %c[r14](%[svm]), %%r14 \n\t"
3826 "mov %c[r15](%[svm]), %%r15 \n\t"
3829 /* Enter guest mode */
3831 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3832 __ex(SVM_VMLOAD) "\n\t"
3833 __ex(SVM_VMRUN) "\n\t"
3834 __ex(SVM_VMSAVE) "\n\t"
3837 /* Save guest registers, load host registers */
3838 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3839 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3840 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3841 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3842 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3843 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3844 #ifdef CONFIG_X86_64
3845 "mov %%r8, %c[r8](%[svm]) \n\t"
3846 "mov %%r9, %c[r9](%[svm]) \n\t"
3847 "mov %%r10, %c[r10](%[svm]) \n\t"
3848 "mov %%r11, %c[r11](%[svm]) \n\t"
3849 "mov %%r12, %c[r12](%[svm]) \n\t"
3850 "mov %%r13, %c[r13](%[svm]) \n\t"
3851 "mov %%r14, %c[r14](%[svm]) \n\t"
3852 "mov %%r15, %c[r15](%[svm]) \n\t"
3857 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3858 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3859 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3860 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3861 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3862 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3863 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3864 #ifdef CONFIG_X86_64
3865 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3866 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3867 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3868 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3869 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3870 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3871 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3872 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3875 , R"bx", R"cx", R"dx", R"si", R"di"
3876 #ifdef CONFIG_X86_64
3877 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3881 #ifdef CONFIG_X86_64
3882 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3884 loadsegment(fs, svm->host.fs);
3885 #ifndef CONFIG_X86_32_LAZY_GS
3886 loadsegment(gs, svm->host.gs);
3892 local_irq_disable();
3894 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3895 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3896 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3897 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3899 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3901 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3902 kvm_before_handle_nmi(&svm->vcpu);
3906 /* Any pending NMI will happen here */
3908 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3909 kvm_after_handle_nmi(&svm->vcpu);
3911 sync_cr8_to_lapic(vcpu);
3915 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3917 /* if exit due to PF check for async PF */
3918 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3919 svm->apf_reason = kvm_read_and_reset_pf_reason();
3922 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3923 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3927 * We need to handle MC intercepts here before the vcpu has a chance to
3928 * change the physical cpu
3930 if (unlikely(svm->vmcb->control.exit_code ==
3931 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3932 svm_handle_mce(svm);
3934 mark_all_clean(svm->vmcb);
3939 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3941 struct vcpu_svm *svm = to_svm(vcpu);
3943 svm->vmcb->save.cr3 = root;
3944 mark_dirty(svm->vmcb, VMCB_CR);
3945 svm_flush_tlb(vcpu);
3948 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3950 struct vcpu_svm *svm = to_svm(vcpu);
3952 svm->vmcb->control.nested_cr3 = root;
3953 mark_dirty(svm->vmcb, VMCB_NPT);
3955 /* Also sync guest cr3 here in case we live migrate */
3956 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3957 mark_dirty(svm->vmcb, VMCB_CR);
3959 svm_flush_tlb(vcpu);
3962 static int is_disabled(void)
3966 rdmsrl(MSR_VM_CR, vm_cr);
3967 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3974 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3977 * Patch in the VMMCALL instruction:
3979 hypercall[0] = 0x0f;
3980 hypercall[1] = 0x01;
3981 hypercall[2] = 0xd9;
3984 static void svm_check_processor_compat(void *rtn)
3989 static bool svm_cpu_has_accelerated_tpr(void)
3994 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3999 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4003 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4008 entry->ecx |= (1 << 2); /* Set SVM bit */
4011 entry->eax = 1; /* SVM revision 1 */
4012 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4013 ASID emulation to nested SVM */
4014 entry->ecx = 0; /* Reserved */
4015 entry->edx = 0; /* Per default do not support any
4016 additional features */
4018 /* Support next_rip if host supports it */
4019 if (boot_cpu_has(X86_FEATURE_NRIPS))
4020 entry->edx |= SVM_FEATURE_NRIP;
4022 /* Support NPT for the guest if enabled */
4024 entry->edx |= SVM_FEATURE_NPT;
4030 static int svm_get_lpage_level(void)
4032 return PT_PDPE_LEVEL;
4035 static bool svm_rdtscp_supported(void)
4040 static bool svm_has_wbinvd_exit(void)
4045 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4047 struct vcpu_svm *svm = to_svm(vcpu);
4049 set_exception_intercept(svm, NM_VECTOR);
4050 update_cr0_intercept(svm);
4053 #define PRE_EX(exit) { .exit_code = (exit), \
4054 .stage = X86_ICPT_PRE_EXCEPT, }
4055 #define POST_EX(exit) { .exit_code = (exit), \
4056 .stage = X86_ICPT_POST_EXCEPT, }
4057 #define POST_MEM(exit) { .exit_code = (exit), \
4058 .stage = X86_ICPT_POST_MEMACCESS, }
4060 static struct __x86_intercept {
4062 enum x86_intercept_stage stage;
4063 } x86_intercept_map[] = {
4064 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4065 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4066 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4067 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4068 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4069 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4070 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4071 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4072 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4073 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4074 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4075 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4076 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4077 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4078 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4079 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4080 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4081 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4082 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4083 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4084 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4085 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4086 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4087 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4088 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4089 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4090 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4091 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4092 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4093 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4094 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4095 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4096 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4097 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4098 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4099 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4100 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4101 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4102 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4103 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4104 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4105 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4106 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4107 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4108 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4109 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4116 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4117 struct x86_instruction_info *info,
4118 enum x86_intercept_stage stage)
4120 struct vcpu_svm *svm = to_svm(vcpu);
4121 int vmexit, ret = X86EMUL_CONTINUE;
4122 struct __x86_intercept icpt_info;
4123 struct vmcb *vmcb = svm->vmcb;
4125 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4128 icpt_info = x86_intercept_map[info->intercept];
4130 if (stage != icpt_info.stage)
4133 switch (icpt_info.exit_code) {
4134 case SVM_EXIT_READ_CR0:
4135 if (info->intercept == x86_intercept_cr_read)
4136 icpt_info.exit_code += info->modrm_reg;
4138 case SVM_EXIT_WRITE_CR0: {
4139 unsigned long cr0, val;
4142 if (info->intercept == x86_intercept_cr_write)
4143 icpt_info.exit_code += info->modrm_reg;
4145 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4148 intercept = svm->nested.intercept;
4150 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4153 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4154 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4156 if (info->intercept == x86_intercept_lmsw) {
4159 /* lmsw can't clear PE - catch this here */
4160 if (cr0 & X86_CR0_PE)
4165 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4169 case SVM_EXIT_READ_DR0:
4170 case SVM_EXIT_WRITE_DR0:
4171 icpt_info.exit_code += info->modrm_reg;
4174 if (info->intercept == x86_intercept_wrmsr)
4175 vmcb->control.exit_info_1 = 1;
4177 vmcb->control.exit_info_1 = 0;
4179 case SVM_EXIT_PAUSE:
4181 * We get this for NOP only, but pause
4182 * is rep not, check this here
4184 if (info->rep_prefix != REPE_PREFIX)
4186 case SVM_EXIT_IOIO: {
4190 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4192 if (info->intercept == x86_intercept_in ||
4193 info->intercept == x86_intercept_ins) {
4194 exit_info |= SVM_IOIO_TYPE_MASK;
4195 bytes = info->src_bytes;
4197 bytes = info->dst_bytes;
4200 if (info->intercept == x86_intercept_outs ||
4201 info->intercept == x86_intercept_ins)
4202 exit_info |= SVM_IOIO_STR_MASK;
4204 if (info->rep_prefix)
4205 exit_info |= SVM_IOIO_REP_MASK;
4207 bytes = min(bytes, 4u);
4209 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4211 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4213 vmcb->control.exit_info_1 = exit_info;
4214 vmcb->control.exit_info_2 = info->next_rip;
4222 vmcb->control.next_rip = info->next_rip;
4223 vmcb->control.exit_code = icpt_info.exit_code;
4224 vmexit = nested_svm_exit_handled(svm);
4226 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4233 static struct kvm_x86_ops svm_x86_ops = {
4234 .cpu_has_kvm_support = has_svm,
4235 .disabled_by_bios = is_disabled,
4236 .hardware_setup = svm_hardware_setup,
4237 .hardware_unsetup = svm_hardware_unsetup,
4238 .check_processor_compatibility = svm_check_processor_compat,
4239 .hardware_enable = svm_hardware_enable,
4240 .hardware_disable = svm_hardware_disable,
4241 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4243 .vcpu_create = svm_create_vcpu,
4244 .vcpu_free = svm_free_vcpu,
4245 .vcpu_reset = svm_vcpu_reset,
4247 .prepare_guest_switch = svm_prepare_guest_switch,
4248 .vcpu_load = svm_vcpu_load,
4249 .vcpu_put = svm_vcpu_put,
4251 .set_guest_debug = svm_guest_debug,
4252 .get_msr = svm_get_msr,
4253 .set_msr = svm_set_msr,
4254 .get_segment_base = svm_get_segment_base,
4255 .get_segment = svm_get_segment,
4256 .set_segment = svm_set_segment,
4257 .get_cpl = svm_get_cpl,
4258 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4259 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4260 .decache_cr3 = svm_decache_cr3,
4261 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4262 .set_cr0 = svm_set_cr0,
4263 .set_cr3 = svm_set_cr3,
4264 .set_cr4 = svm_set_cr4,
4265 .set_efer = svm_set_efer,
4266 .get_idt = svm_get_idt,
4267 .set_idt = svm_set_idt,
4268 .get_gdt = svm_get_gdt,
4269 .set_gdt = svm_set_gdt,
4270 .set_dr7 = svm_set_dr7,
4271 .cache_reg = svm_cache_reg,
4272 .get_rflags = svm_get_rflags,
4273 .set_rflags = svm_set_rflags,
4274 .fpu_activate = svm_fpu_activate,
4275 .fpu_deactivate = svm_fpu_deactivate,
4277 .tlb_flush = svm_flush_tlb,
4279 .run = svm_vcpu_run,
4280 .handle_exit = handle_exit,
4281 .skip_emulated_instruction = skip_emulated_instruction,
4282 .set_interrupt_shadow = svm_set_interrupt_shadow,
4283 .get_interrupt_shadow = svm_get_interrupt_shadow,
4284 .patch_hypercall = svm_patch_hypercall,
4285 .set_irq = svm_set_irq,
4286 .set_nmi = svm_inject_nmi,
4287 .queue_exception = svm_queue_exception,
4288 .cancel_injection = svm_cancel_injection,
4289 .interrupt_allowed = svm_interrupt_allowed,
4290 .nmi_allowed = svm_nmi_allowed,
4291 .get_nmi_mask = svm_get_nmi_mask,
4292 .set_nmi_mask = svm_set_nmi_mask,
4293 .enable_nmi_window = enable_nmi_window,
4294 .enable_irq_window = enable_irq_window,
4295 .update_cr8_intercept = update_cr8_intercept,
4297 .set_tss_addr = svm_set_tss_addr,
4298 .get_tdp_level = get_npt_level,
4299 .get_mt_mask = svm_get_mt_mask,
4301 .get_exit_info = svm_get_exit_info,
4303 .get_lpage_level = svm_get_lpage_level,
4305 .cpuid_update = svm_cpuid_update,
4307 .rdtscp_supported = svm_rdtscp_supported,
4309 .set_supported_cpuid = svm_set_supported_cpuid,
4311 .has_wbinvd_exit = svm_has_wbinvd_exit,
4313 .set_tsc_khz = svm_set_tsc_khz,
4314 .write_tsc_offset = svm_write_tsc_offset,
4315 .adjust_tsc_offset = svm_adjust_tsc_offset,
4316 .compute_tsc_offset = svm_compute_tsc_offset,
4317 .read_l1_tsc = svm_read_l1_tsc,
4319 .set_tdp_cr3 = set_tdp_cr3,
4321 .check_intercept = svm_check_intercept,
4324 static int __init svm_init(void)
4326 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4327 __alignof__(struct vcpu_svm), THIS_MODULE);
4330 static void __exit svm_exit(void)
4335 module_init(svm_init)
4336 module_exit(svm_exit)